JP2013150219A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which can be achieved by a standard CMOS process capable of microfabrication and which is capable of a high-voltage operation.SOLUTION: A semiconductor integrated circuit comprises: an output buffer 30 including an output P-channel transistor 31 and an output N-channel transistor 32 which are inserted in series between a high-voltage side power supply node (VPP=10 V) and a low-voltage side power supply node (VSS=0 V); and a level shifter 40 for generating a high-voltage side logic signal having an upper limit voltage VPP=10 V and a lower limit voltage 5 V, and a low-voltage side logic signal having an upper limit voltage VD3=3 V and a lower limit voltage 0 V, from an output signal of an inverter 71 having an upper limit voltage VD3=3 V and a lower limit voltage VS=0 V, and supplying the high-voltage side logic signal and the low-voltage side logic signal to respective gates of the output P-channel transistor 31 and the output N-channel transistor 32.

Description

  The present invention relates to a semiconductor integrated circuit that operates with a plurality of power supply voltages.

  2. Description of the Related Art In recent years, in semiconductor integrated circuits, the withstand voltage of elements has been reduced along with miniaturization of elements such as MOSFETs (Metal Oxide Field Effect Effect Transistors: transistors of metal-oxide film-semiconductor structure; simply referred to as transistors hereinafter). There is a need to lower the power supply voltage of semiconductor integrated circuits. For example, when the processing technology of the device is about 350 nm, the power supply voltage of the semiconductor integrated circuit is 3 V to 5 V. However, as the processing technology is miniaturized to 130 nm and 65 nm, the withstand voltage of the device decreases, and the semiconductor integrated circuit The power supply voltage is decreasing to 1.8V and 1.2V.

  However, in a system including an analog circuit that drives a liquid crystal, a sensor, or the like, a 3V power source or a 5V power source is necessary to operate the analog circuit. For this reason, when configuring an LSI chip including this type of analog circuit, the miniaturized internal circuit is operated with a low voltage power supply such as 1.2 V, and the analog circuit and the input / output interface circuit are driven with 3 V to 5 V. It is necessary to adopt a multi-power supply configuration such as a

  In addition, nonvolatile memories such as flash memory and EEPROM (Electrically Erasable and Programmable Read Only Memory) are used for many purposes because information does not disappear even when the power is turned off. However, this type of nonvolatile memory requires a high voltage for writing and erasing data. Therefore, this type of non-volatile memory also employs a multi-power supply configuration.

JP 2006-140211 A

  Conventionally, logic circuits that require high-speed operation and require finer technology due to the large number of elements are composed of low-voltage transistors with thin oxide films, and input / output interface circuits and high-voltage circuits have thick oxide films. The high voltage transistor was used.

  Thus, under the conventional technology, it was necessary to make a high voltage transistor in addition to the standard transistor corresponding to miniaturization. For this reason, it is necessary to manufacture a transistor by changing a plurality of types of oxide film thicknesses, and the number of processes is large and the process is expensive. In addition, since the manufacturing process is complicated, it is necessary to pay attention to the yield. In addition, since the process is expensive and the yield is low, there is a problem that the price of the product increases.

  In addition, when making a product composed of a single nonvolatile memory, there is only a problem that the price of the memory is increased. However, a so-called embedded (non-volatile memory) in which a nonvolatile memory and a logic circuit or an analog circuit are mixedly mounted on the same chip. In the case of Embedded products, a more important problem arises. In other words, in addition to the fine standard transistor that constitutes the memory, in order to construct a high breakdown voltage transistor with a thick oxide film, the thermal process of the process is changed, and the characteristics of the standard transistor that constitutes the memory also change. Occur. In particular, analog circuits such as memory sense amplifiers are sensitive to transistor characteristics, and each time the transistor characteristics change, tuning is required. For this reason, there is a problem that a large loss occurs in a semiconductor manufacturer having many analog IPs.

  The present invention has been made in view of the above-described circumstances, and an object thereof is to provide a semiconductor integrated circuit that can be realized by a standard CMOS process that can be miniaturized and that can operate at a high voltage. To do.

  The present invention has an output buffer having an output P-channel transistor and an output N-channel transistor inserted in series between a high-potential-side power supply node and a low-potential-side power supply node, and the voltage of the high-potential-side power supply node Alternatively, a first intermediate voltage intermediate between the voltage of the high potential side power supply node and the voltage of the low potential side power supply node is selected and supplied to the gate of the output P-channel transistor as a high potential side logic signal, A second intermediate voltage intermediate between the voltage of the high potential side power supply node and the voltage of the low potential side power supply node or the voltage of the low potential side power supply node is selected, and the output N-channel transistor is selected as the low potential side logic signal. An output circuit of a semiconductor integrated circuit is provided, wherein the output circuit is supplied to the gate of the semiconductor integrated circuit.

  According to the present invention, the gate of the output P-channel transistor is supplied with the voltage of the high potential side power supply node or the first intermediate voltage intermediate between the voltage of the high potential side power supply node and the voltage of the low potential side power supply node. Therefore, the voltage applied between the gate and the substrate of the output P-channel transistor can be relaxed. Further, since the output N-channel transistor is supplied with the second intermediate voltage or the voltage of the low potential side power supply node between the voltage of the high potential side power supply node and the voltage of the low potential side power supply node. The voltage applied between the gate and the substrate of the N-channel transistor can be relaxed.

  Note that Patent Document 1 discloses an input circuit shown in FIG. 12 as an input circuit designed to reduce stress applied to a transistor. In FIG. 12, P channel transistor M4 and N channel transistor M2 inserted in series between high potential side power supply Vpp and ground GND constitute an inverter. A P-channel transistor M3 is interposed between the node to which the input signal IN is applied and the gate of the P-channel transistor M4, and N between the node to which the input signal IN is applied and the gate of the N-channel transistor M2. A channel transistor M1 is interposed. The gates of P-channel transistor M3 and N-channel transistor M1 are supplied with cut-off voltages VSHLD2 and VSHLD1, which are intermediate voltages between power supply voltage Vpp and ground level GND.

  Here, when the threshold voltage of the N-channel transistor M1 is Vthn, if the level of the input signal IN is increased, ideally, when the gate voltage of the N-channel transistor M2 becomes VSHLD1-Vthn, N The channel transistor M1 is turned off, and the gate voltage of the N channel transistor M2 is maintained at VSHLD1-Vthn. Further, when the threshold voltage of the P-channel transistor M3 is Vthp, if the level of the input signal IN is decreased, ideally, when the gate voltage of the P-channel transistor M4 becomes VSHLD2 + Vthp, the P-channel transistor M3 Is turned OFF, and the gate voltage of the P-channel transistor M4 is maintained at VSHLD2 + Vthp.

  However, in practice, a minute current (off-leakage current or subthreshold current) flows through the P-channel transistor M3 and the N-channel transistor M1 even in a situation where the gate-source voltage is smaller than the threshold voltage. Therefore, when a long time has elapsed after the input signal IN is raised to a high voltage and the N-channel transistor M1 is turned off, the gate voltage of the N-channel transistor M2 is charged to the same high voltage as the input signal IN. Therefore, in a situation where the input signal IN is maintained at a high voltage for a long time, it cannot be avoided that an excessive gate-substrate voltage is applied to the N-channel transistor M2. The same applies when the input signal IN falls.

  On the other hand, in the output circuit according to the present invention, as described above, the voltage of the high-potential-side power node or the voltage of the high-potential-side power node and the voltage of the low-potential-side power node is applied to the gate of the output P-channel transistor. An intermediate first intermediate voltage is always applied, and a second intermediate voltage or low potential side intermediate between the voltage of the high potential side power supply node and the voltage of the low potential side power supply node is applied to the gate of the output N-channel transistor. The voltage of the power supply node is always given. Accordingly, the voltage applied between the gate and the substrate of the output P-channel transistor and the voltage applied between the gate and the substrate of the output N-channel transistor can be moderated constantly.

It is a figure which shows the oxide film thickness of the transistor in the MOS integrated circuit corresponding to various power supply voltages, and the limiting pressure | voltage resistance of the oxide film. It is sectional drawing which shows the structure of the CMOS circuit manufactured by the standard CMOS process. It is sectional drawing which shows the structural example of the high voltage | pressure-resistant CMOS circuit which expanded the LDD area | region of both the drain and the source, and improved the proof pressure. It is sectional drawing which shows the structural example of the high voltage | pressure-resistant CMOS circuit which expanded only the LDD area | region of the drain and improved the proof pressure. 1 is a circuit diagram showing a configuration of an output circuit of a semiconductor integrated circuit according to a first embodiment of the present invention. It is a circuit diagram which shows the structure of the output circuit of the semiconductor integrated circuit which is 2nd Embodiment of this invention. It is a circuit diagram which shows the structure of the output circuit of the semiconductor integrated circuit which is 3rd Embodiment of this invention. It is a circuit diagram which shows the structure of the output circuit of the semiconductor integrated circuit which is 4th Embodiment of this invention. It is a circuit diagram which shows the structure of the high voltage logic circuit which is 5th Embodiment of this invention. It is a circuit diagram which shows the structure of the output circuit of the semiconductor integrated circuit which is 6th Embodiment of this invention. It is a circuit diagram which shows the structure of the output circuit of the semiconductor integrated circuit which is 7th Embodiment of this invention. FIG. 11 is a circuit diagram showing a configuration of an input circuit disclosed in Patent Document 1.

  Embodiments of the present invention will be described below with reference to the drawings.

<High breakdown voltage technology used in the present invention>
Each embodiment of the present invention uses a high withstand voltage technique that is generally used in CMOS circuits. Therefore, prior to the description of the embodiments of the present invention, a technique for increasing the breakdown voltage of the CMOS circuit will be described.

  FIG. 1 shows the oxide film thickness of a transistor in a MOS integrated circuit corresponding to various power supply voltages and the limiting breakdown voltage (voltage that breaks down the gate oxide film in a certain time). Usually, in order to realize a MOS integrated circuit capable of guaranteeing operation for 10 years, the electric field applied to the oxide film is set to about 5 MeV (megaelectron volts), but the upper limit of the electric field that can be applied to the oxide film Is set to approximately 8 MeV.

  FIG. 2 is a cross-sectional view showing a configuration of a CMOS circuit manufactured by a standard CMOS process. This CMOS circuit employs an LDD (Lightly Doped Drain) structure in order to suppress the generation of hot electrons and improve the reliability of the transistor. This LDD structure is a structure in which a low-concentration impurity region is provided between a source, a drain and a channel so that a high electric field is not concentrated here. In order to form a transistor having an LDD structure, a side wall (generally an oxide film) is added to the side wall of the gate of the transistor, and n− or p− is set using the gate with the side wall added as a mask. Injected by implantation. In this case, the transistor can be manufactured by self-alignment, and the required area of the transistor is not increased. For example, when a CMOS circuit having a gate breakdown voltage of 5V is realized by the configuration shown in FIG. 2, the oxide film is set to a thickness of about 90 mm (angstrom), and the breakdown voltage (TDDB: Time Dependent Dielectric Breakdown) is set to about 6V. . In this case, the drain breakdown voltage (Breakdown) is about 7V.

FIG. 3 is a cross-sectional view illustrating a configuration example of an HVDMOS (High Voltage Drain Metal Oxide Semiconductor) transistor in which the breakdown voltages of both the drain and the source of the CMOS circuit illustrated in FIG. 2 are improved. In this high voltage CMOS circuit, the LDD region (n ⁻ or p ⁻ region) in FIG. 2 is wide. By doing so, the drain breakdown voltage can be easily increased to 10 V or more. However, this configuration has the disadvantage that the gate and the diffusion region need to be sufficiently wide, and the layout area becomes large. As shown in FIG. 3, the structure of a P-channel transistor and an N-channel transistor in which both the drain and source LDD regions are expanded is called a double-sided high breakdown voltage structure.

  FIG. 4 is a cross-sectional view showing a configuration example of an HVDMOS transistor adopting a high breakdown voltage structure in which only the LDD region on the drain side of each channel transistor of the CMOS circuit shown in FIG. 2 is expanded. This configuration example has an advantage that the area increase is suppressed as compared with the configuration example of FIG. The structure of the P-channel transistor and the N-channel transistor shown in FIG. 4 is called a one-side high breakdown voltage structure.

<First Embodiment>
FIG. 5 is a circuit diagram showing the configuration of the output circuit of the CMOS LSI according to the first embodiment of the present invention. In FIG. 5, the output P-channel transistor 31 and the output N-channel transistor 32 are both transistors having a single-side high breakdown voltage structure in which only the LDD region of the drain is expanded. The output buffer 30 is a 3V output buffer composed of the output P-channel transistor 31 and the output N-channel transistor 32. Here, the output P-channel transistor 31 has a source and a substrate (NWell) connected to the high-potential power supply node to which the voltage VDD = 3V is applied, and the output N-channel transistor 32 has a low potential to which the voltage VSS = 0V is applied. A source and a substrate (PWell) are connected to the side power supply node. The drains of the output P-channel transistor 31 and the output N-channel transistor 32 are commonly connected, and this common connection point is an output node that generates the output signal OUT of the output circuit.

  In this embodiment, the voltage VDD of the high potential side power supply node VDD = 3 V or an intermediate voltage VCC between the voltage of the high potential side power supply node and the voltage of the low potential side power supply node is selected and used as the high potential side logic signal VGp. This is supplied to the gate of the output P-channel transistor 31. In this embodiment, the intermediate voltage VCC or the low potential side power supply node voltage VSS = 0V is selected and supplied to the gate of the output N channel transistor as the low potential side logic signal VGn.

  More specifically, the output circuit according to the present embodiment has the first pre-driver 10 and the second pre-driver 20 in the preceding stage of the output buffer 30. Here, the first pre-driver 10 is composed of a CMOS inverter to which the voltage VDD = 3V is applied as the high potential side power supply voltage and the intermediate voltage VCC = 1.2V is applied as the low potential side power supply voltage. The CMOS inverter of the first pre-driver 10 is a circuit that inverts and outputs the input signal INU, and outputs a high potential side logic signal VGp that sets 1.2V to a low level and 3V to a high level. Further, the second pre-driver 20 is configured by a CMOS inverter to which the intermediate voltage VCC = 1.2V is applied as the high potential side power supply voltage and the voltage VSS = 0V is applied as the low potential side power supply voltage. The CMOS inverter of the second pre-driver 20 is a circuit that inverts and outputs the input signal INL, and outputs a low potential side logic signal VGn having 0V as a low level and 1.2V as a high level.

  Next, the operation of this embodiment will be described. In this embodiment, when the output signal OUT = 3V of logic “1” is output from the output circuit, the input signal INU for the first predriver 10 is 3V, and the input signal INL for the second predriver 20 is 1.. 2V. As a result, the gate voltage VGp for the output P-channel transistor 31 is 1.2 V, the gate voltage VGn for the output N-channel transistor 32 is 0 V, the output P-channel transistor 31 is ON, and the output N-channel transistor 32 is OFF. Thus, the output signal OUT becomes 3V. Further, when the output signal OUT = 0V of logic “0” is output from the output circuit, the input signal INU for the first pre-driver 10 is set to 1.2V, and the input signal INL for the second pre-driver 20 is set to 0V. The As a result, the gate voltage VGp for the output P-channel transistor 31 is 3 V, the gate voltage VGn for the output N-channel transistor 32 is 1.2 V, the output P-channel transistor 31 is OFF, and the output N-channel transistor 32 is ON. Thus, the output signal OUT becomes 0V.

  Here, the stress applied to the output P-channel transistor 31 is examined. First, when the output signal OUT is set to 3V, since the output P-channel transistor 31 has a gate voltage VGp of 1.2V and a substrate (NWELL) voltage of 3V, the gate-substrate (NWell) voltage VGB is 3V-1. .2V = 1.8V. Since the gate-substrate voltage VGB is relaxed in this way, there is no problem.

  When the output signal OUT is set to 0V, since the gate voltage VGp is 3V and the voltage of the substrate (NWell) is 3V, the gate-substrate (NWell) voltage VGB is 0V, and the withstand voltage is not a problem. Since the voltage of NWell is 3V, a stress of 3V is applied to the PN junction between the drain (0V) of output P-channel transistor 31 and NWell. However, since the output P-channel transistor 31 has a one-side high breakdown voltage structure, this level of stress is not a problem.

  Next, the stress applied to the output N-channel transistor 32 will be examined. When the output signal OUT is set to 3V, the gate voltage VGn of the output N-channel transistor 32 is 0V and the voltage of the substrate (PWell) is 0V. Therefore, the gate-substrate voltage VGB is 0V, which is not a problem. On the other hand, when the output signal OUT is set to 0V, since the gate voltage VGn is 1.2V and the substrate voltage is 0V, the gate-substrate voltage VGB of the output N-channel transistor 32 is 1.2V. Since the gate-substrate voltage VGB is relaxed in this way, there is no problem.

  As described above, in this embodiment, the output buffer 30 that outputs a high voltage from 0 V to 3 V can be configured by a standard MOS transistor having a gate breakdown voltage of 1.2 V.

Second Embodiment
FIG. 6 is a circuit diagram showing a configuration of an output circuit of a CMOS LSI according to the second embodiment of the present invention. In the present embodiment, in the circuit configuration of the first embodiment (FIG. 5), a MOS transistor having a gate breakdown voltage of about 5V is used, and the output buffer 30, the first pre-driver 10 and the second pre-driver 20 are used. The output buffer 30 is operated at a power supply voltage of 10V by changing each power supply voltage applied to the power supply voltage.

  In FIG. 6, the output P-channel transistor 31 has a source and a substrate (NWell) connected to the high potential side power supply node to which the voltage VPP = 10V is applied, and the output N-channel transistor 32 has a low voltage to which the voltage VSS = 0V is applied. A source and a substrate (PWell) are connected to the potential side power supply node. The drains of the output P-channel transistor 31 and the output N-channel transistor 32 are commonly connected to the output node of the output signal OUT.

  In the present embodiment, the high potential side power supply node voltage VPP = 10V or the first intermediate voltage VD5 between the high potential side power supply node voltage and the low potential side power supply node voltage VSS = 0V is selected, The potential side logic signal VGp is supplied to the gate of the output P-channel transistor 31. In the present embodiment, the second intermediate voltage VD3 = 3V between the voltage VPP = 10V of the high potential side power supply node and the voltage VSS = 0V of the low potential side power supply node, or the voltage VSS of the low potential side power supply node = 0V is selected and supplied to the gate of the output N-channel transistor 32 as the low potential side logic signal VGn.

  More specifically, the first pre-driver 10 in the previous stage of the output buffer 30 is supplied with the voltage VPP = 10V as the high potential side power supply voltage VD10 and the first intermediate voltage VD5 = 5V as the low potential side power supply voltage. The CMOS inverter is configured. The second pre-driver 20 is configured by a CMOS inverter to which the first intermediate voltage VD3 = 3V is applied as the high potential side power supply voltage and the voltage VSS = 0V is applied as the low potential side power supply voltage VS0.

  Next, the operation of this embodiment will be described. In this embodiment, when the output signal OUT = 10V of logic “1” is output from the output circuit, the input signal INU for the first predriver 10 is 10V, and the input signal INL for the second predriver 20 is 3V. Is done. As a result, the gate voltage VGp for the output P-channel transistor 31 is 5 V, the gate voltage VGn for the output N-channel transistor 32 is 0 V, the output P-channel transistor 31 is ON, and the output N-channel transistor 32 is OFF. The output signal OUT becomes 10V. Further, when the output signal OUT = 0V of logic “0” is output from the output circuit, the input signal INU for the first pre-driver 10 is set to 5V, and the input signal INL for the second pre-driver 20 is set to 0V. As a result, the gate voltage VGp for the output P-channel transistor 31 is 10 V, the gate voltage VGn for the output N-channel transistor 32 is 3 V, the output P-channel transistor 31 is OFF, and the output N-channel transistor 32 is ON. The output signal OUT becomes 0V.

  Here, the stress applied to the output P-channel transistor 31 is examined. Since the output P-channel transistor 31 has a gate voltage VGp of 5V and a substrate (NWell) voltage of 10V when the output signal OUT is 10V, the gate-substrate voltage VGB is 5V and voltage relaxation is performed. No problem. On the other hand, when the output signal OUT is 0 V, the output P-channel transistor 31 has a gate VGp of 10 V and a substrate (NWell) voltage of 10 V, so the gate-substrate voltage VGB is 0 V, and there is no problem with the breakdown voltage. When the output signal OUT is 0V, a stress of 10V is applied between the drain of the output P-channel transistor 31 and NWell, but there is no problem because the withstand voltage of the output P-channel transistor 31 is 10V or more. .

  Next, the stress applied to the output N-channel transistor 32 will be examined. In the output N-channel transistor 32, when the output signal OUT is 10V, the gate voltage VGn is 0V and the substrate (PWell) voltage is 0V. Therefore, the gate-substrate voltage VGB is 0V, and no voltage is applied. On the other hand, when the output signal OUT is 0V, the output N-channel transistor 32 has a gate voltage VGn of 3V and a substrate voltage of 0V. Therefore, the gate-substrate voltage VGB is 3V, and voltage relaxation is performed. There is no.

  As described above, according to this embodiment, the output buffer 30 that outputs a high voltage from 0 V to 10 V can be configured by a MOS transistor having a gate breakdown voltage of 5 V.

<Third Embodiment>
FIG. 7 is a circuit diagram showing a configuration of an output circuit of a CMOS LSI according to the third embodiment of the present invention. In this embodiment, a level shifter 40 is added to the previous stage of the first predriver 10 and the second predriver 20 in the second embodiment (FIG. 6), and an inverter 71 is further added to the previous stage.

  The inverter 71 and the inverter 72 in the level shifter 40 are both CMOS inverters, and are supplied with the high potential side power supply voltage VD3 = 3V and the low potential side power supply voltage VS = 0V. The inverter 71 logically inverts and outputs an input signal IN having an amplitude from 0V to 3V, and the inverter 72 logically inverts and outputs the output signal of the inverter 71. When the input signal IN is “0” (0V), the output signal of the inverter 71 is 3V and the output signal of the inverter 72 is 0V. When the input signal IN is “1” (3V), the output signal of the inverter 71 is 0V and the output signal of the inverter 72 is 3V.

  In the level shifter 40, the P-channel transistors 41 and 42 are transistors having a gate breakdown voltage of 5V. Each source of P channel transistors 41 and 42 is connected to a high potential side power supply node to which power supply voltage VPP = 10 V is applied. P channel transistors 41 and 42 have their respective drains connected to their gates.

  Each of the P-channel transistors 43 and 44 is a one-side high breakdown voltage transistor in which only the drain LDD region is expanded. The source of the P-channel transistor 43 is connected to the common connection node N 1 between the drain of the P-channel transistor 41 and the gate of the P-channel transistor 42. The source of the P channel transistor 44 is connected to the common connection node N 2 of the drain of the P channel transistor 42 and the gate of the P channel transistor 41. The voltage generated at the node N2 is supplied to the first pre-driver 10 as the high potential side logic signal INU. A bias voltage VBIAS2 is applied to the gates of the P-channel transistors 43 and 44. This bias voltage VBIAS2 is a voltage lowered from 5V by the threshold voltage Vthp of the P-channel transistors 43 and 44.

  Therefore, the P-channel transistor 43 is turned OFF because the voltage between the gate and the source becomes smaller than the threshold voltage Vthp when the voltage of the node N1 is made lower than 5V. Further, the P-channel transistor 44 is turned OFF because the voltage between the gate and the source becomes smaller than the threshold voltage Vthp when the voltage at the node N2 is made lower than 5V. P channel transistors 43 and 44 to which bias voltage VBIAS2 is applied to the gate in this way serve to lower the lower limit voltage of nodes N1 and N2 to 5V.

  N-channel transistors 45 and 46 and inverters 71 and 72 have a current path between one drain of P-channel transistor 43 or 44 and a low-potential-side power supply node (VSS = 0 V) according to low-potential-side logic signal INL. The switch means for forming is configured. Further details are as follows.

  Each of N-channel transistors 45 and 46 is a one-side high breakdown voltage transistor in which only the LDD region of the drain extends, and each drain is connected to each drain of P-channel transistors 43 and 44, respectively. The source of N channel transistor 45 is connected to output node N3 of inverter 71, and the source of N channel transistor 46 is connected to output node N4 of inverter 72. The voltage generated at the output node N4 of the inverter 72 is supplied to the second pre-driver 20 as the low potential side logic signal INL. A bias voltage VBIAS3 = 3V is applied to the gates of the N-channel transistors 45 and 46.

  Therefore, when the input signal IN is “0” (0 V), the output signal of the inverter 71 is 3 V, and the output signal of the inverter 72 is 0 V, the N-channel transistor 45 is OFF and the N-channel transistor 46 is ON. Further, when the input signal IN is “1” (3 V), the output signal of the inverter 71 is 0 V, and the output signal of the inverter 72 is 3 V, the N-channel transistor 45 is ON and the N-channel transistor 46 is OFF.

  P channel transistor 47 has its source and drain connected to the source and drain of P channel transistor 41, respectively. The P channel transistor 48 has its source and drain connected to the source and drain of the P channel transistor 42, respectively. A bias voltage VBIAS1 is applied to each gate of the P-channel transistors 47 and 48. The bias voltage VBIAS1 is a voltage shifted from the voltage VPP = 10V to the low potential side power supply voltage VSS = 0V side by the threshold voltage Vthp of the P-channel transistors 47 and 48.

  A slight drain current flows through P-channel transistors 47 and 48 to which the bias voltage VBIAS1 is applied at the gate. In the circuit shown in FIG. 7, when leak current flows through P channel transistors 43 and 44, the voltages at nodes N1 and N2 drop. P-channel transistors 47 and 48 compensate for voltage drops at nodes N1 and N2 due to leakage current by replenishing nodes N1 and N2 with a small drain current flowing therethrough.

  Next, the operation of this embodiment will be described. In FIG. 7, since the bias voltage VBIAS2 described above is applied to the gates of the P-channel transistors 43 and 44, the voltages at the nodes N1 and N2 are between 10V and 5V. A bias voltage VBIAS3 of 3V is input to the gates of the N-channel transistors 45 and 46. Therefore, the voltage at the output node N4 of the inverter 72 is 3V or less, and normal operation is possible.

  When the input signal IN becomes “1” (3V), the node N3 becomes 0V, the node N4 becomes 3V, and the low potential side logic signal INL for the second pre-driver 20 becomes 3V. Accordingly, the gate voltage VGn = 0V is supplied to the output N-channel transistor 32. Since the node N3 is 0V and the node N4 is 3V, the N-channel transistor 45 is ON, the N-channel transistor 46 is OFF, the P-channel transistor 43 is ON, and the P-channel transistor 44 is OFF. Therefore, the node N1 is 5V, the node N2 is 10V, and the high potential side logic signal INU for the first pre-driver 10 is 10V. Accordingly, the gate voltage VGp = 5V is supplied from the first pre-driver 10 to the output P-channel transistor 31. As a result, in the output buffer 30, the output P-channel transistor 31 is turned on, the output N-channel transistor 32 is turned off, and the output signal OUT becomes 10V.

  On the other hand, when the input signal IN becomes “0” (0V), the node N3 becomes 3V, the node N4 becomes 0V, and the low potential side logic signal INL for the second pre-driver 20 becomes 0V. Since the node N3 is 3V and the node N4 is 0V, the N channel transistor 45 is OFF, the N channel transistor 46 is ON, the P channel transistor 43 is OFF, and the P channel transistor 44 is ON. Therefore, the node N1 is 10V, the node N2 is 5V, and the high potential side logic signal INU for the first pre-driver 10 is 5V. Therefore, the gate voltage VGp = 10 V is supplied from the first pre-driver 10 to the output P-channel transistor 31. As a result, in the output buffer 30, the output P-channel transistor 31 is turned off, the output N-channel transistor 32 is turned on, and the output signal OUT becomes 0V.

  In the present embodiment, in the above operation, the gate-substrate voltage VGB applied to all the transistors can be 5 V or less, and an output signal OUT having an amplitude from 0 V to 10 V can be obtained.

  In the present embodiment, transistors 47 and 48 functioning as constant current sources are provided in order to prevent the voltages at the nodes N1 and N2 from being lowered due to the leakage current. However, another circuit may be used as the constant current source, and a simple resistor may be used instead of the transistors 47 and 48 as long as the control of the leakage current does not become a problem.

<Fourth embodiment>
FIG. 8 is a circuit diagram showing a configuration of an output circuit of a CMOS LSI according to the fourth embodiment of the present invention. In the present embodiment, the first predriver 10 and the second predriver 20 are omitted from the third embodiment (FIG. 7), and the voltage at the node N1 is supplied to the output P-channel transistor 31 as the gate voltage VGp. The voltage at the node N3 is supplied to the output N-channel transistor 32 as the gate voltage VGn. According to the present embodiment, the number of elements can be reduced by the amount corresponding to the first pre-driver 10 and the second pre-driver 20, and the same effect as in the third embodiment can be obtained.

<Fifth Embodiment>
FIG. 9 is a circuit diagram showing a configuration of a high voltage logic circuit according to a fifth embodiment of the present invention. In this high voltage logic circuit, the output buffers 300, 310, 320 and 330 are circuits corresponding to the output buffer 30 of the first to fourth embodiments, and include a high potential side power supply node (power supply voltage VDD) and a low potential. It comprises an output P-channel transistor and an output N-channel transistor inserted in series between the side power supply nodes (power supply voltage VSS).

  The inverters 81, 82, and 83 are CMOS circuits to which a second intermediate voltage, which will be described later, is applied as the high potential side power supply voltage and the voltage VSS of the low potential side power supply node is applied as the low potential side power supply voltage. Inverters 81, 82, and 83 logically invert input signals IN0, IN1, and IN3, respectively, and output them. The level shifters 400, 410, and 420 are level shifters having the same configuration as that of the level shifter 40 of FIG. 7, and the output signals of the inverters 81, 82, and 83 are input thereto. Based on the output signal of the inverter 81, the level shifter 400 generates a first intermediate voltage (this voltage VPP at the high potential side power supply node or between the voltage VPP at the high potential side power supply node and the voltage VSS at the low potential side power supply node (this In the example, VD5 (= VPP / 2) is selected and output as the high-potential side logic signal INU0, and the second between the voltage VPP of the high-potential-side power supply node and the voltage VSS of the low-potential-side power supply node. Is selected as an intermediate voltage (VD3 (<VPP / 2) in this example) or the voltage VSS of the low potential side power supply node, and is output as the low potential side logic signal INL0. Similarly, the level shifter 410 outputs the high potential side logic signal INU1 and the low potential side logic signal INL1 based on the output signal of the inverter 82, and the level shifter 420 outputs the high potential side logic signal INU2 and the low potential side logic signal INU2 based on the output signal of the inverter 83. The low potential side logic signal INL2 is output.

  The logic circuits 100, 110, 120, and 130 are high potential side logic circuits that perform a logical operation using the high potential side logic signal generated by the level shifter 400, 410, or 420. The logic circuits 200, 210, 220, and 230 are low potential side logic circuits that perform a logical operation using the low potential side logic signal generated by the level shifter 400, 410, or 420.

  In this example, the set of the high potential side logic circuit 100 and the low potential side logic circuit 200 constitutes a NAND circuit. More specifically, the high-potential side logic circuit 100 performs a NAND operation on the high-potential side logic signals INU0 and INU1, and outputs a high-potential side logic signal having an upper limit voltage VPP and a lower limit voltage VD5 as a logic signal indicating the operation result. Output to the gate of the output P-channel transistor of the output buffer 300. The low-potential side logic circuit 200 performs a NAND operation on the low-potential side logic signals INL0 and INL1, and outputs a low-potential side logic signal having an upper limit voltage VD3 and a lower limit voltage VSS as a logic signal indicating the calculation result. Output to the gate of the output N-channel transistor.

  A set of the high potential side logic circuit 110 and the low potential side logic circuit 210 similarly constitutes a NAND circuit. The high potential side logic circuit 110 outputs a high potential side logic signal indicating the NAND operation result of the high potential side logic signals INU1 and INU2 to the gate of the output P channel transistor of the output buffer 310. The low potential side logic circuit 210 outputs a low potential side logic signal indicating the NAND operation result of the low potential side logic signals INL1 and INL2 to the gate of the output N-channel transistor of the output buffer 310.

  A set of the high potential side logic circuit 120 and the low potential side logic circuit 220 constitutes a NOR circuit. The high-potential side logic circuit 120 drives the output P-channel transistor of the output buffer 320 based on the NOR operation result of the high-potential side logic signals INU0 and INU2, and the latter low-potential side logic circuit 220 is connected to the low-potential side logic signal INL0. And the output N-channel transistor of the output buffer 320 is driven based on the NOR operation result of INL2.

  A set of the high potential side logic circuit 130 and the low potential side logic circuit 230 forms an inverter. That is, the high-potential side logic circuit 130 drives the output P-channel transistor of the output buffer 330 based on the logic inversion result of the high-potential side logic signal INU1, and the latter low-potential side logic circuit 230 is driven by the low-potential side logic signal INL1. The output N-channel transistor of the output buffer 330 is driven based on the logical inversion result.

  Note that the logic circuit illustrated in FIG. 9 is merely an example, and the high voltage logic circuit illustrated in FIG. 9 can be realized for any logic circuit, not limited to the illustrated circuit.

  The present embodiment is particularly effective for a high voltage logic circuit that performs a logical operation for driving a large number of output buffers based on a small number of input signals. According to the present embodiment, when such a high voltage logic circuit is configured, the number of level shifters having a large area can be reduced, and the overall area of the high voltage logic circuit can be reduced.

<Sixth Embodiment>
FIG. 10 is a circuit diagram showing a configuration of an output circuit of a CMOS LSI according to the sixth embodiment of the present invention. In the present embodiment, the level shifter 40 in the fifth embodiment is changed to a simplified level shifter 50. In this level shifter 50, P-channel transistors 51, 52, 53, 54, 57 and 58 have the same configuration as the P-channel transistors 41, 42, 43, 44, 47 and 48 of the level shifter 40. It operates in the same way. N channel transistors 55 and 56 have their drains connected to the drains of P channel transistors 53 and 54, respectively, and low potential side power supply voltage VSS = 0 V is applied to each source. The gate of N channel transistor 55 is connected to output node N 3 of inverter 71, and the gate of N channel transistor 56 is connected to output node N 4 of inverter 72.

  According to the present embodiment, the drain currents of the N-channel transistors 55 and 56 do not flow into the output nodes N3 and N4 of the inverters 71 and 72, but flow into the low potential side power supply node (VSS = 0V). Therefore, the voltage generated at the node N4 is completely swung from 0V to 3V. Therefore, in the present embodiment, the second pre-driver 20 in the fifth embodiment is unnecessary, and the voltage generated at the node N4 is supplied to the output N-channel transistor 32 as the gate voltage VGn. In addition, since it is not necessary to pass current to output nodes N3 and N4 of inverters 71 and 72, the transistor size of inverters 71 and 72 can be reduced, and the area of the output circuit can be reduced.

<Seventh embodiment>
FIG. 11 is a circuit diagram showing a configuration of an output circuit of a CMOS LSI according to the seventh embodiment of the present invention. In the present embodiment, the output buffer 30 in the third embodiment (FIG. 7) is changed to the output buffer 60 to relieve stress applied to each transistor constituting the output buffer.

  In the third embodiment, when the output P-channel transistor 31 is 0V, 0V is applied to the drain and 10V is applied to the gate, and the largest stress is applied. Further, when the output signal OUT is 10V, the output N-channel transistor 32 is applied with 10V on the drain and 0V on the gate, and is subjected to the greatest stress.

  Here, when the gate oxide films of the output P-channel transistor 31 and the output N-channel transistor 32 are set to 90 mm and the drain node profile is set to a low concentration, there is no problem with the withstand voltage of 10 V, but the drain-gate leakage current is May increase.

  Therefore, in the output buffer 60 in the present embodiment, as shown in FIG. 11, P-channel transistors 61 and 62 are inserted in series between the high potential side power supply node (VPP) and the output signal VOUT generation node, N-channel transistors 64 and 63 are inserted in series between the low potential side power supply node (VSS) and the generation node of output signal VOUT.

  Here, the P-channel transistor 61 and the N-channel transistor 64 are transistors each having a gate breakdown voltage of 5V. In the P-channel transistor 61, the source and the substrate (NWell) are connected to the high potential side power supply node (VPP), and the output signal of the first pre-driver 10 is given to the gate. Further, the source and substrate (PWell) of the N channel transistor 64 are connected to the low potential side power supply node (VSS), and the output signal of the second pre-driver 20 is given to the gate.

  Each of the P-channel transistor 62 and the N-channel transistor 63 is a one-side high breakdown voltage transistor in which only the drain LDD region is expanded. The source and substrate (NWell) of the P channel transistor 62 are connected to the drain of the P channel transistor 61. The N channel transistor 63 has a source and a substrate (NWell) connected to the drain of the N channel transistor 64. The drains of the P-channel transistor 62 and the N-channel transistor 63 are connected to each other, and the connection node between the drains is an output node that generates the output signal OUT.

  P-channel transistor 62 and N-channel transistor 63 are supplied with bias voltage VDD5 = VPP / 2 = 5V at their gates, and function as voltage relaxing transistors.

  According to the present embodiment, in the process in which the P-channel transistor 61 changes from ON to OFF and the output signal OUT falls, the drain voltage of the P-channel transistor 61 decreases to 5V + Vthp (Vthp is the threshold voltage of the P-channel transistor 62). ), The P-channel transistor 62 is turned OFF. For this reason, the drain voltage of the P-channel transistor 61 does not become lower than 5V + Vthp. In the process in which the N-channel transistor 64 changes from ON to OFF and the output signal OUT rises, when the drain voltage of the N-channel transistor 64 increases to 5V-Vthn (Vthn is the threshold voltage of the N-channel transistor 63), The N channel transistor 63 is turned off. For this reason, the drain voltage of the N-channel transistor 64 does not become higher than 5V-Vthn.

  As described above, according to this embodiment, the voltage between the gate and the drain of the P-channel transistor 61 and the N-channel transistor 64 is limited to a voltage value smaller than 5V regardless of whether the output signal OUT is 0V or 10V. Is done. For this reason, the gate leakage current of the P-channel transistor 61 and the N-channel transistor 64 is reduced.

<Other embodiments>
Although the first to seventh embodiments of the present invention have been described above, other embodiments are conceivable for the present invention. For example:

(1) Although the voltage VD3 is generated in addition to the voltage VD5 in FIGS. 6 to 11, the voltage VD3 and the voltage VD5 may be the same voltage.

(2) In each of the above embodiments, a single-side high voltage structure transistor is used to increase the breakdown voltage, but a double-side high voltage structure transistor may be used instead.

(3) In the third to seventh embodiments, the low potential side logic signal having the same upper limit voltage and lower limit voltage as the input logic signal is output, and the upper limit voltage and lower limit voltage are higher than the input logic signal. A level shifter that outputs a logic signal on the high potential side was used. That is, the level shifter outputs a high potential side logic signal obtained by shifting the input logic signal to the high potential side. However, instead of doing so, a level shifter that outputs a high-potential side logic signal having the same upper limit voltage and lower limit voltage as the input logic signal and outputs a low-potential side logic signal obtained by shifting the input logic signal to the low potential side. May be used. Such a level shifter replaces the high potential side power supply node (VPP) and the low potential side power supply node (VSS) in the level shifter 40 shown in FIG. 7 or the level shifter 50 shown in FIG. This can be realized by changing the N channel transistor to a P channel transistor.

31, 41, 42, 43, 44, 47, 48, 61, 62... P-channel transistor, 32, 45, 46, 63, 64... N-channel transistor, 30, 60. 1 pre-driver, 20 ... second pre-driver, 40, 50, 400, 410, 420 ... level shifter, 71, 72, 81, 82, 83 ... inverter, 100, 110, 120, 130 ... high Potential side logic circuit, 200, 210, 220, 230... Low potential side logic circuit.

Claims (19)

An output buffer having an output P-channel transistor and an output N-channel transistor inserted in series between the high-potential-side power supply node and the low-potential-side power supply node;
The output P-channel is selected as a high-potential-side logic signal by selecting a voltage of the high-potential-side power supply node or a first intermediate voltage intermediate between the voltage of the high-potential-side power supply node and the voltage of the low-potential-side power supply node. To the gate of the transistor,
A second intermediate voltage intermediate between the voltage of the high-potential-side power supply node and the voltage of the low-potential-side power supply node or the voltage of the low-potential-side power supply node is selected, and the output N channel is selected as a low-potential-side logic signal. An output circuit of a semiconductor integrated circuit, wherein the output circuit is supplied to a gate of a transistor.   The output circuit according to claim 1, wherein the first intermediate voltage and the second intermediate voltage are the same voltage. An output buffer having an output P-channel transistor and an output N-channel transistor inserted in series between the high-potential-side power supply node and the low-potential-side power supply node;
The high-potential-side power supply node voltage is the high-potential-side power-supply voltage, the first intermediate voltage between the high-potential-side power-supply node voltage and the low-potential-side power-supply node voltage is the low-potential-side power-supply voltage, A first pre-driver for supplying an output signal to the gate of the output P-channel transistor;
A second intermediate voltage intermediate between the voltage of the high potential power supply node and the voltage of the low potential power supply node is set as a high potential power supply voltage, and the voltage of the low potential power supply node is set as a low potential power supply voltage. And a second pre-driver for supplying an output signal to the gate of the output N-channel transistor.   4. The output P-channel transistor and the output N-channel transistor are each constituted by a transistor having a one-side high breakdown voltage structure in which only a low-concentration drain region of a drain is widened. The output circuit according to claim.   4. The output P-channel transistor and the output N-channel transistor are each constituted by a transistor having a double-sided high breakdown voltage structure in which both drain and source lightly doped drain regions are expanded. An output circuit according to claim 1.   6. The device according to claim 1, wherein the first and second intermediate voltages are ½ or less of a voltage between the high potential side power supply node and the low potential side power supply node. The output circuit described in 1. An output buffer having an output P-channel transistor and an output N-channel transistor inserted in series between a high-potential-side power supply node and a low-potential-side power supply node;
Based on the input logic signal, a voltage of the high potential side power supply node or a first intermediate voltage intermediate between the voltage of the high potential side power supply node and the voltage of the low potential side power supply node is selected. A signal is supplied to the gate of the output P-channel transistor as a signal, and a second intermediate voltage between the voltage of the high-potential-side power supply node and the voltage of the low-potential-side power supply node or the voltage of the low-potential-side power supply node And a level shifter that supplies a low-potential-side logic signal to the gate of the output N-channel transistor. An output buffer having an output P-channel transistor and an output N-channel transistor inserted in series between the high-potential-side power supply node and the low-potential-side power supply node;
Based on the input logic signal, a voltage of the high potential side power supply node or a first intermediate voltage intermediate between the voltage of the high potential side power supply node and the voltage of the low potential side power supply node is selected. A second intermediate voltage between the voltage of the high potential side power supply node and the voltage of the low potential side power supply node or the voltage of the low potential side power supply node is output as a signal, A level shifter that outputs as
The high-potential-side power supply node voltage is set to the high-potential-side power supply voltage, the first intermediate voltage is set to the low-potential-side power supply voltage, and the gate of the output P-channel transistor is driven based on the high-potential-side logic signal. A first pre-driver;
The second intermediate voltage is a high-potential-side power supply voltage, the low-potential-side power supply node voltage is a low-potential-side power supply voltage, and the gate of the output N-channel transistor is driven based on the low-potential-side logic signal. An output circuit of a semiconductor integrated circuit, comprising: a second pre-driver. The level shifter is
First and second P-channel transistors each having a source connected to the high-potential power supply node and each other's drain connected to each gate;
Each source is connected to each drain of the first and second P-channel transistors, and a bias voltage obtained by subtracting each threshold voltage from the first intermediate voltage is applied to each gate. P-channel transistors of
Based on the input logic signal, a current path is formed between one drain of the third P-channel transistor or the fourth P-channel transistor and the low-potential side power supply node, whereby the first P-channel transistor Switching means for changing each drain voltage of the channel transistor and the second P-channel transistor within a range from the first intermediate voltage to the voltage of the high-potential-side power supply node;
9. The output circuit according to claim 8, wherein one drain voltage of the first P-channel transistor or the second P-channel transistor is output as the high potential side logic signal. The switch means includes
The first and second N-channel transistors are connected to the drains of the third and fourth P-channel transistors, respectively, and the second intermediate voltage is applied to the respective gates. 10. The current path is formed between one source of the first N-channel transistor or the second N-channel transistor and the low-potential side power supply node based on a side logic signal. Output circuit. The switch means includes
The first and second N-channel transistors each having a drain connected to each drain of the third and fourth P-channel transistors and each source connected to the low-potential side power supply node, 10. The output circuit according to claim 9, wherein each gate voltage is generated based on a signal, wherein one of the first N-channel transistor and the second N-channel transistor is turned on and the other is turned off.   A current path for leakage current flowing through the third P-channel transistor is provided in parallel with the first P-channel transistor, and a current path for leakage current flowing through the fourth P-channel transistor is provided for the second P-channel transistor. 12. The output circuit according to claim 9, wherein the output circuit is provided in parallel.   The current path of the leakage current flowing through the third P-channel transistor and the current path of the leakage current flowing through the fourth P-channel transistor are respectively parallel to the first P-channel transistor and the second P-channel transistor. A gate voltage for supplying a drain current corresponding to the leakage current is applied to each gate of the fifth and sixth P-channel transistors, which is composed of connected fifth and sixth P-channel transistors. The output circuit according to claim 12. One or a plurality of output buffers operated by a power supply voltage between the high potential side power supply node and the low potential side power supply node;
Based on an input logic signal to each, a voltage of the high potential side power supply node or a first intermediate voltage between the voltage of the high potential side power supply node and the voltage of the low potential side power supply node is selected. A second intermediate voltage between the high-potential-side power node voltage and the low-potential-side power node voltage or the low-potential-side power node voltage is selected and One or more level shifters that output as logic signals;
A high-potential-side logic circuit that outputs a high-potential-side logic signal that drives the one or more output buffers by performing a logical operation on the high-potential-side logic signal output by the one or more level shifters;
A low-potential-side logic circuit that outputs a low-potential-side logic signal that drives the one or more output buffers by performing a logical operation on the low-potential-side logic signal output by the one or more level shifters. High voltage logic circuit characterized by The level shifter is
First and second P-channel transistors each having a source connected to the high-potential power supply node and each other's drain connected to each gate;
Each source is connected to each drain of the first and second P-channel transistors, and a bias voltage obtained by subtracting each threshold voltage from the first intermediate voltage is applied to each gate. P-channel transistors of
By forming a current path between one drain of the third P-channel transistor or the fourth P-channel transistor and the low-potential side power supply node based on the input logic signal, the first P-channel Switching means for changing each drain voltage of the transistor and the second P-channel transistor within a range from the first intermediate voltage to the voltage of the high potential side power supply node,
15. The high voltage logic circuit according to claim 14, wherein the drain voltage of one of the first P channel transistor or the second P channel transistor is output as the high potential side logic signal.   The output buffer includes an output P-channel transistor and an output N-channel transistor interposed in series between the high-potential-side power supply node and the low-potential-side power supply node. High voltage logic circuit. An output buffer having an output P-channel transistor and an output N-channel transistor inserted in series between the high-potential-side power supply node and the low-potential-side power supply node;
Based on the input logic signal, a voltage of the high potential side power supply node or a first intermediate voltage intermediate between the voltage of the high potential side power supply node and the voltage of the low potential side power supply node is selected. A second intermediate voltage between the voltage of the high potential side power supply node and the voltage of the low potential side power supply node or the voltage of the low potential side power supply node is output as a signal, A level shifter that outputs to the gate of the output N-channel transistor,
A pre-driver that uses the high-potential-side power supply node as a high-potential-side power-supply voltage, the first intermediate voltage as a low-potential-side power-supply voltage, and transmits the high-potential-side logic signal to the gate of the output P-channel transistor. And
The level shifter is
First and second P-channel transistors each having a source connected to the high-potential power supply node and each other's drain connected to each gate;
Each source is connected to each drain of the first and second P-channel transistors, and a bias voltage obtained by subtracting each threshold voltage from the first intermediate voltage is applied to each gate. P-channel transistors of
First and second N-channel transistors each having a drain connected to each drain of the third and fourth P-channel transistors and each source connected to the low-potential side power supply node;
An output circuit of a semiconductor integrated circuit, wherein each gate voltage for generating one of the first N-channel transistor and the second N-channel transistor and turning the other OFF is generated based on the input logic signal. In an output buffer that operates with a power supply voltage between a high potential side power supply node and a low potential side power supply node,
A source is connected to the high potential side power supply node, a voltage of the high potential side power supply node is set as an upper limit voltage, and a first intermediate voltage between the high potential side power supply node and the low potential side power supply node is set as a lower limit voltage. An output P-channel transistor to which a high-potential-side logic signal is applied to the gate;
A source is connected to the low potential side power supply node, a second intermediate voltage intermediate between the high potential side power supply node and the low potential side power supply node is set as an upper limit voltage, and a voltage of the low potential side power supply node is set as a lower limit voltage An output N-channel transistor to which a low-potential-side logic signal is applied to the gate;
A drain-source resistance of the output P-channel transistor and a drain-source resistance of the output N-channel transistor are interposed between the drain of the output P-channel transistor and the drain of the output N-channel transistor. To change the transmission of the output node of the output buffer, the drain voltage of the output P-channel transistor is limited to a predetermined voltage value or more, and the drain voltage of the output N-channel transistor is predetermined. An output buffer comprising: voltage relaxation means for limiting to a voltage value or less. The voltage relaxation means is
A voltage relaxation P-channel transistor that is interposed between the drain of the output P-channel transistor and the output node of the output buffer, and to which a gate voltage of a predetermined voltage value is applied;
19. A voltage relaxation N-channel transistor interposed between a drain of the output N-channel transistor and an output node of the output buffer, to which a gate voltage having a predetermined voltage value is applied. Output buffer described in.

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