CN111600594A - Level conversion circuit with anti-protection - Google Patents

Level conversion circuit with anti-protection Download PDF

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Publication number
CN111600594A
CN111600594A CN202010440930.4A CN202010440930A CN111600594A CN 111600594 A CN111600594 A CN 111600594A CN 202010440930 A CN202010440930 A CN 202010440930A CN 111600594 A CN111600594 A CN 111600594A
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voltage
drain
protection
gate
module
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CN111600594B (en
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张超
郭智文
汪坚雄
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SENTRONIC TECHNOLOGY (SHANGHAI) CO LTD
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SENTRONIC TECHNOLOGY (SHANGHAI) CO LTD
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention discloses a level conversion circuit with reverse protection, which comprises a low-voltage input module, a high-voltage protection module, a PMOS load module with reverse connection protection and an output protection module; the low-voltage input module is used for inputting a low-voltage differential signal LV _ INP/LV _ INN to be converted into a circuit and generating high and low levels to be input into the high-voltage protection module; the high-voltage protection module is used for preventing a low-voltage MOS device in the low-voltage input module from being broken down by a high-voltage level and inputting the high-voltage level and the low-voltage level into the PMOS load module with reverse connection protection; the PMOS load module with the reverse connection protection is used for moving a low-voltage level to a high-voltage level in level conversion, and is also used for protecting a circuit when a chip ground is connected with the high voltage in a reverse way so as to avoid chip damage; the output protection module is used for protecting the output circuit and outputting a high-voltage differential signal HV _ OUTP/HV _ OUTN. The invention has the advantages of simple structure, low power consumption, small area, and capability of preventing the power supply and the ground from damaging the chip, and can be used for an analog integrated circuit.

Description

Level conversion circuit with anti-protection
The technical field is as follows:
the invention relates to the technical field of electronic circuits, in particular to a level conversion circuit with reverse protection.
Background art:
fig. 1 is a schematic diagram of a conventional level shift circuit, as shown in fig. 1, the level shift circuit includes: the inverter, an NMOS transistor N1, an NMOS transistor N2, a PMOS transistor P1 and a PMOS transistor P2. The inverter is used for receiving an input signal Vin and outputting an inverted signal; the grid electrode of the NMOS tube N1 is connected to a power supply Vdd, the source electrode of the NMOS tube N1 is connected with the output end of the inverter, and the drain electrode of the NMOS tube N1 is connected with the grid electrode of the PMOS tube P2; the gate of the NMOS transistor N2 is connected with the output end of the inverter, the source thereof is grounded Vss, and the drain thereof is connected to the output end Vout of the level conversion circuit; the grid electrode of the PMOS pipe P1 is connected to the output end Vout of the level conversion circuit, the source electrode thereof is connected to the voltage source Vpp, and the drain electrode thereof is connected with the drain electrode of the NMOS pipe N1; the gate of the PMOS transistor P2 is connected to the drain of the NMOS transistor N1, the source thereof is connected to the voltage source Vpp, and the drain thereof is connected to the output terminal Vout of the level shifter circuit.
When the input signal Vin is at a high level value, the NMOS transistor N2 is turned off, and at this time, the voltage applied to the gate of the PMOS transistor P2 is at a low level, the NPMOS transistor P2 is turned on, and the voltage value of the voltage source Vpp is output; when the input signal Vin is at a low level, a high level is formed after passing through the inverter and is applied to the gate of the NMOS transistor N2, the NMOS transistor N2 is turned on, the output terminal outputs the ground voltage Vss, at this time, the output terminal is at a low level, the PMOS transistor P1 is turned on, and the voltage source Vpp quickly charges the node NA of the drain of the NMOS transistor N1.
If the existing level conversion circuit needs to convert a high-voltage level circuit, all MOS (metal oxide semiconductor) tubes need to be high-voltage MOS tubes, so that the MOS tube elements are prevented from generating leakage current under the high-voltage condition, and the MOS tube elements are ensured to be capable of maintaining normal work. And if the voltage source Vpp is reversely connected with the ground, the current in the PMOS transistors P1 and P2 flows from the drains of P1 and P2 to the substrate, burning the transistors and damaging the chip.
The invention content is as follows:
in view of the disadvantages of the prior art, an embodiment of the present invention provides a level shifter with anti-latch protection to solve the above-mentioned problems in the prior art.
In order to achieve the purpose, the invention provides the following technical scheme:
a level shift circuit with anti-protection, comprising:
the low-voltage input module, the high-voltage protection module, the PMOS load module with reverse connection protection and the output protection module;
the low-voltage input module is used for inputting a low-voltage differential signal LV _ INP/LV _ INN to be converted into a circuit and generating high and low levels to be input into the high-voltage protection module;
the high-voltage protection module is used for inputting high and low levels into a PMOS load module with reverse connection protection;
the PMOS load module with the reverse connection protection is used for moving the low-voltage level to the high-voltage level HV _ VDD and protecting the circuit when the chip ground is connected with the high voltage in a reverse way;
the output protection module is used for protecting the output circuit; the input is a high voltage level after level conversion, and a high voltage differential signal HV _ OUTP/HV _ OUTN is output.
As a further aspect of the present invention, the low voltage input module includes two low voltage NMOS devices NM1 and NM 2;
the source of the low-voltage NMOS device NM1 is connected to the chip ground LV _ GND, the gate of the low-voltage NMOS device NM1 is connected to the low-voltage differential input terminal LV _ INP, and the drain of the low-voltage NMOS device NM3 is connected to the source of the high-voltage protection module; the source of the low-voltage NMOS device NM2 is connected to the chip ground LV _ GND, and the gate is connected to the low-voltage differential input terminal LV _ INN; the drain is connected to the source of the NMOS device NM4 in the high voltage protection module.
As a further aspect of the present invention, the high voltage protection module includes two high voltage NMOS devices NM3 and NM 4;
the grid electrode of the NM3 is connected to a low-voltage power supply input end LV-VDD, and the drain electrode of the NM3 is connected to the drain electrodes of PMOS devices in the output protection module and the PMOS load module with reverse connection protection;
the gate of the NM4 is connected to a low voltage power input LV _ VDD; the drain is connected to the drains of the PMOS devices in the output protection module and the PMOS load module with reverse connection protection.
As a further aspect of the present invention, the PMOS load module with reverse connection protection includes three high voltage PMOS devices PM1, PM2, and PM 3;
the drain of the PM1 is connected with the drain of the NM3, the source is connected to a high-voltage power input end HV _ VDD, and the gate is connected to the drain of the PM 2;
the drain of the PM2 is connected with the drain of the NM4, the source is connected to a high-voltage power input terminal HV _ VDD, and the gate is connected to the drain of the PM 1.
As a further aspect of the present invention, PM1 turns on when the PM1 gate voltage decreases; the voltage at the drain of PM1 is raised, the drain voltage of PM2 is lowered due to the connection of the drain of PM1 to the gate of PM2, and the speed of the reduction of the gate voltage of PM1 is increased due to the connection of the gate of PM1 to the drain of PM2, thus forming a positive feedback structure.
As a further aspect of the present invention, when the gate voltage of PM2 is decreased, PM2 is turned on, the voltage at the drain of PM2 is raised, the drain voltage of PM2 is decreased due to the connection of the drain of PM2 to the gate of PM1, and the speed of decrease of the gate voltage of PM2 is increased due to the connection of the gate of PM2 to the drain of PM1, so as to form a positive feedback structure.
As a further scheme of the invention, the high-voltage PMOS device PM3 is in a forward conducting structure, the source of the PM3 is connected to the high-voltage power supply input end HV _ VDD, the drain of the PM3 is in short circuit with the gate and the substrate, a diode structure with the source directed to the substrate is formed by utilizing a PN junction between the P-type doped source and the N-type doped substrate of the PMOS device, and the channel is disconnected when the power supply and the ground are reversely connected by utilizing the unidirectional conductivity of the diode, so that the chip is protected.
As a further scheme of the invention, the drain of the high-voltage PMOS device PM3 is shorted with the gate and the substrate, and then is connected to the substrate of PM1 and PM 2; when the power supply and the ground are reversely connected, the path is disconnected, the substrates of the PM1 and the PM2 are equivalent to high voltage, reverse bias of drains in the PM1 and the PM2 and PN junctions of the substrates is guaranteed, current is prevented from flowing from the drains of the PM1 and the PM2 to the substrates to damage PMOS devices, and the chip is protected.
As a further aspect of the present invention, the output protection packet block includes two resistors R1, R2; one end of the resistor R1 is connected to the drain of the high-voltage NMOS device NM3 and the drain of the high-voltage PMOS device PM1, and the other end of the resistor R1 is connected to the high-voltage differential output end HV _ OUTP; one end of the resistor R2 is connected to the drain of the high-voltage NMOS device NM4 and the drain of the high-voltage PMOS device PM2, and the other end is connected to the high-voltage differential output terminal HV _ OUTN.
As a further aspect of the present invention, the output protection module includes NMOS devices NM5 and NM6, the drain of NM5 is shorted together with the gate and the substrate, and then respectively connected to the drain of PM 1; the drain electrode of the NM6 is shorted with the grid electrode and the substrate together and is respectively connected with the drain electrode of the PM 2; the source high voltage differential output ends of NM5 and NM6 are respectively connected with HV _ OUTP and HV _ OUTP.
The invention has the beneficial effects that:
1. the invention provides a level conversion circuit with reverse protection, which can reduce the power consumption and the realization complexity of the circuit, and simultaneously can prevent large current generated when a power supply and a ground are reversely connected, thereby avoiding chip damage.
2. The high-voltage protection module can separate a high-voltage area from a low-voltage area, and a low-voltage MOS tube in the low-voltage input module is prevented from being broken down by a high-voltage level.
3. The invention has the function of reverse connection protection, the drain electrode of a high-voltage PMOS pipe PM3 in a PMOS load module of the reverse connection protection is in short circuit with the grid electrode and the substrate, a diode structure with the source electrode pointing to the substrate is formed by utilizing the PN junction between the P-type doped source electrode and the N-type doped substrate of the PMOS device, and the damage to the PMOS device caused by the current flowing from the PM1 and PM2 drain electrodes to the substrate is avoided by utilizing the unidirectional conductivity of the diode, thereby protecting the chip.
4. The high-voltage PMOS pipe PM3 in the reverse connection protection PMOS load module adopts a method that the drain electrode, the grid electrode and the substrate are in short circuit to form a diode, and compared with a method that the diode is directly inserted, the chip area can be effectively saved.
To more clearly illustrate the structural features and effects of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
Description of the drawings:
fig. 1 is a circuit diagram of a conventional level shift circuit.
Fig. 2 is a block diagram of the architecture of the present invention.
Fig. 3 is a circuit schematic of a first embodiment of the present invention.
FIG. 4 is a cross-sectional view of a PMOS diode.
Fig. 5 is a circuit schematic of a second embodiment of the invention.
The specific implementation mode is as follows:
the invention will be described more fully and clearly in connection with the accompanying drawings and the accompanying knowledge, and it is to be understood that the circuit diagrams described are merely exemplary embodiments of the invention, and are not intended to represent all exemplary embodiments.
Referring to fig. 2 to 5, a level shift circuit with reverse protection can reduce the power consumption and the implementation complexity of the circuit, and can prevent a large current from being generated when a power supply and a ground are reversely connected, thereby avoiding chip damage.
The method specifically comprises the following steps: the low-voltage input module, the high-voltage protection module, the PMOS load module with reverse connection protection and the output protection module.
The low-voltage input module is used for inputting a low-voltage level to be converted into the whole circuit; the input end of the module is a low-voltage differential input end LV _ INP/LV _ INN; the high-voltage protection module is used for preventing a low-voltage MOS tube in the low-voltage input module from being broken down by a high-voltage level, and the low-voltage input module can work normally; the input of the module is a low voltage power signal. The PMOS load module with the reverse connection protection is used for moving a low-voltage level to a high-voltage level in level conversion, and is also used for protecting a circuit when a chip ground is connected with the high voltage in a reverse way so as to avoid chip damage; the module adopts PMOS connected into positive feedback structure as the load of the whole circuit; the input of the module is a high-voltage power supply input end HV _ VDD, and the output of the module is connected with a high-voltage protection module and an output protection module; the output protection module is used for protecting an output circuit, the input of the module is a high-voltage level after level conversion, and the output of the module is a high-voltage differential output end HV _ OUTP/HV _ OUTN.
Preferably, the low voltage input module includes two low voltage NMOS devices NM1 and NM2, wherein: the sources of NM1 and NM2 are both connected to chip ground LV _ GND; the gates of NM1 and NM2 are connected to low voltage differential inputs LV _ INP and LV _ INN, respectively; the drains of NM1 and NM2 are connected to the sources of NMOS devices in the high voltage protection module, respectively.
Preferably, the high voltage protection module includes two high voltage NMOS devices NM3 and NM4, wherein: the sources of NM3 and NM4 are connected to the drains of NM1 and NM2 in the low voltage input module, respectively; the gates of NM3 and M4 are commonly connected to a low voltage power input LV _ VDD; the drains of NM3 and NM4 are connected to the drains of PMOS devices in the output protection module and the PMOS load module with reverse-connect protection, respectively.
Preferably, the PMOS load module with reverse connection protection comprises three high voltage PMOS devices PM1, PM2 and PM3,
wherein: the PM1 and the PM2 form a PMOS load connected in a positive feedback structure, the drain of the PM1 is connected to the drain of the NM3 (one end of the R1), the source is connected to the high-voltage power input terminal HV _ VDD, the gate is connected to the drain of the PM2 to form a positive feedback structure, specifically, the gate of the PM1 of the high-voltage PMOS device is connected to the drain of the PM2, and the gate of the PM2 is connected to the drain of the PM 1. When the gate voltage of PM1 decreases, PM1 turns on; the voltage at the drain of PM1 is raised, the drain voltage of PM2 is lowered due to the connection of the drain of PM1 to the gate of PM2, and the speed of lowering the gate voltage of PM1 is increased due to the connection of the gate of PM1 to the drain of PM2, thus constituting a positive feedback structure; the drain of the PM2 is connected to the drain of the NM4 (one end of R2), the source is connected to a high-voltage power supply input terminal HV _ VDD, the gate is connected to the drain of the PM1 to form a positive feedback structure, specifically, the gate of the high-voltage PMOS device PM1 is connected to the drain of the PM2, and the gate of the PM2 is connected to the drain of the PM 1; when the gate voltage of PM2 is reduced, PM2 is conducted, the voltage at the drain of PM2 is raised, the drain voltage of PM2 is reduced due to the fact that the drain of PM2 is connected to the gate of PM1, the speed of reduction of the gate voltage of PM2 is increased due to the fact that the gate of PM2 is connected to the drain of PM1, and therefore a positive feedback structure is formed.
Preferably, the PM3 is a forward conducting structure, the source of the PM3 is connected to the high voltage power input terminal HV _ VDD, the drain of the PM3 is shorted to the gate and the substrate, a diode structure is formed by a PN junction between the P-type doped source and the N-type doped substrate of the PMOS device, and the drain, the gate and the substrate of the PM3 are further connected to the substrates of the PM1 and PM2 to provide substrate voltages for all the PMOS devices in the structure. The method specifically comprises the following steps: the PM3 is a forward conducting structure, the source of the PM3 is connected to a high-voltage power supply input end HV _ VDD, the drain of the PM3 is in short circuit with the grid and the substrate, a diode structure with the source pointing to the substrate is formed by utilizing a PN junction between the P-type doped source and the N-type doped substrate of the PMOS device, and the circuit is disconnected when the power supply and the ground are reversely connected by utilizing the unidirectional conductivity of the diode so as to protect the chip; the drain of the high voltage PMOS device PM3 is shorted to the gate and substrate and then connected to the substrate of PM1, PM 2. When the power supply and the ground are reversely connected, the path is disconnected, the substrates of the PM1 and the PM2 are equivalent to high voltage, reverse bias of drains in the PM1 and the PM2 and PN junctions of the substrates is guaranteed, current is prevented from flowing from the drains of the PM1 and the PM2 to the substrates to damage PMOS devices, and the chip is protected.
Preferably, the output protection pack comprises two resistors R1, R2, wherein: one end of R1 is connected to the drain of NM3, and the other end is connected to the high voltage differential output terminal HV _ OUTP; one end of R2 is connected to the drain of NM4, and the other end is connected to the high voltage differential output terminal HV _ OUTN. The high-voltage protection module can separate a high-voltage area from a low-voltage area, so that a low-voltage MOS tube in the low-voltage input module is prevented from being broken down by a high-voltage level; the drain electrode of a high-voltage PMOS pipe PM3 in the reverse connection protection PMOS load module is in short circuit with the grid electrode and the substrate, a diode structure with the source electrode pointing to the substrate is formed by utilizing a PN junction between the P-type doped source electrode and the N-type doped substrate of the PMOS device, and the damage to the PMOS device caused by the current flowing from the PM1 and PM2 drain electrodes to the substrate is avoided by utilizing the unidirectional conductivity of the diode, so that the chip is protected; the high-voltage PMOS pipe PM3 in the reverse connection protection PMOS load module adopts a method that a drain electrode, a grid electrode and a substrate are in short circuit to form a diode, and compared with a method that the diode is directly inserted, the chip area can be effectively saved.
Example 1
Referring to fig. 3, the circuit of the present invention includes: the low-voltage input module, the high-voltage protection module, the output protection module and the PMOS load module with reverse connection protection are arranged on the output side of the output protection module; the input end of the low-voltage input module is a low-voltage differential input end LV _ INP/LV _ INN. The input of the high-voltage protection module is a low-voltage power supply signal. The input of the output protection module is a high-voltage level after level conversion, and the output is a high-voltage differential output end HV _ OUTP/HV _ OUTN. The input of the PMOS load module with the reverse connection protection is a high-voltage power supply input end HV _ VDD, and the output and high-voltage protection modules are connected with the output protection module.
The low-voltage input module is used for inputting low-voltage levels to be converted into the whole circuit; the high-voltage protection module is used for preventing a low-voltage MOS tube in the low-voltage input module from being broken down by a high-voltage level and ensuring that the low-voltage input module can work normally; the output protection module is used for protecting the output circuit; the PMOS load module with the reverse connection protection is used for moving a low level to a high level in level conversion, and is also used for protecting a circuit when a chip ground is connected with the high voltage in a reverse mode, so that the chip is prevented from being damaged.
Referring to fig. 3, the low voltage input module includes two low voltage NMOS devices NM1 and NM2, wherein: the sources of NM1 and NM2 are both connected to chip ground LV _ GND; the gates of NM1 and NM2 are connected to low voltage differential inputs LV _ INP and LV _ INN, respectively. When LV _ INP is high, NM1 turns on, pulling the voltage at node a down to the chip ground LV _ GND.
Referring to fig. 3, the high voltage protection module includes two high voltage NMOS devices NM3 and NM4, wherein: the sources of NM3 and NM4 are connected to the drains of NM1 and NM2 in the low voltage input module, respectively; the gates of NM3 and M4 are commonly connected to a low voltage power input LV _ VDD; since the voltage at node a is pulled low, NM3 turns on, pulling the voltage at node C to the chip ground LV _ GND. In the present invention, the point a is located between the drain of NM1 and the source of NM3 or a junction thereof, and similarly, the point B is located between the drain of NM2 and the source of NM4 or a junction thereof.
Referring to fig. 3, the PM1 gate is connected to the drain of PM2, and the PM2 gate is connected to the drain of PM1 (node C). When the gate voltage of PM1 decreases, PM1 turns on; the voltage at the drain of PM1 (node C) is raised, the drain voltage of PM2 is lowered because the drain of PM1 is connected to the gate of PM2, the speed of lowering the gate voltage of PM1 is increased because the gate of PM1 is connected to the drain of PM2, and similarly as the PM2 gate voltage is lowered, PM2 is turned on, the voltage at the drain of PM2 (node D) is raised, the drain of PM2 is connected to the gate of PM1, the voltage at the drain of PM2 (node D) is lowered, and the speed of lowering the gate voltage of PM2 is increased because the gate of PM2 is connected to the drain of PM1 (node C). Therefore, a positive feedback structure is formed, and the sources of the PM1 and PM2 are connected to the high-voltage power input end HV _ VD.
Since the drain of NM3 (node C) is low level of LV _ GND, PM2 turns on to pull the drain of PM2 (node D) high, and since the drain of PM2 (node D) is connected to the drain of NM4, the drain of PM2 (node D) is raised faster due to the positive feedback loading structure. Finally, the voltage output of the node D is the high voltage power input terminal HV _ VDD. Similarly, the drain (node C) output of PM1 is the chip ground LV _ GND.
Since the gate of the PM1 is connected to the drain of the PM2 (node D), when node D is raised continuously, the PM1 transistor is also gradually turned off, and the PM1 transistor is already completely turned off when the output to node D is the high voltage power input terminal HV _ VDD-VTHP, and the drain of the PM1 transistor (node C) is the ground LV _ GND. Therefore, the high-voltage differential signal is output after output protection.
When the voltage at node D rises to HV _ VDD, the voltage at node B rises continuously until the output voltage at node B is LV _ VDD-VTHN, NM4 is turned off, PM2 can raise the voltage at the drain of NM4 (node D) to HV _ VDD
Referring to fig. 4, wherein the source of PM3 is connected to high voltage power input HV _ VDD, the gate, substrate, and drain are shorted together, a source-to-drain diode structure is formed by the PN junction between the P-doped source and N-doped substrate of the PMOS device, and the gate, substrate, and drain of PM3 are shorted together to provide substrate voltages of PM1 and PM 2. The chip can be effectively protected when the power supply and the ground are reversely connected.
In the invention, the specific method for power supply and ground reverse protection comprises the following steps: when the power supply and the ground are reversely connected, the path is disconnected, the substrates of the PM1 and the PM2 are equivalent to high voltage, reverse bias of drains in the PM1 and the PM2 and PN junctions of the substrates is guaranteed, current is prevented from flowing from the drains of the PM1 and the PM2 to the substrates to damage PMOS devices, and the chip is protected.
The above steps are all conclusions when LV _ INP is high level and LV _ INN is low level, at this time, the level output of node C is chip ground LV _ GND, and the level output of node D is high voltage power supply level HV _ VDD.
Similarly, when LV _ INP is low and LV _ INN is high, the opposite is true, and at this time, node C outputs the high voltage power supply level HV _ VDD and node D outputs the chip ground LV _ GND.
Nodes C and D vary between the high voltage supply level HV _ VDD and the chip ground LV _ GND in the interval in which LV _ INP and LV _ INN vary at high and low levels
Referring to fig. 3, the output protection packet block includes two resistors R1, R2, which output the levels of the node C and the node D as the high voltage differential output terminals HV _ OUTP/HV _ OUTP, respectively. And realizing level shift.
Example 2:
the low voltage input module, the high voltage protection module and the PMOS load module with reverse connection protection of the present invention are the same as in embodiment 1.
Referring to fig. 5, the output protection module includes two NMOS devices NM5 and NM 6. The drains of NM5 and NM6 are shorted together with the gate and the substrate, and then connected to node C and node D, respectively. The source high voltage differential output terminals HV _ OUTP/HV _ OUTP of the devices NM5 and NM6 are connected. The NM5 and NM6 output the levels of the node C and node D as high voltage differential output terminals HV _ OUTP/HV _ OUTP, respectively.
The drains of the devices NM5 and NM6 are shorted together with the gate and the substrate to form an active resistance structure. The drain current ID of the NMOS device is related to the gate-source voltage VGS (neglecting the second order effect):
Figure BDA0002504121370000111
since the drains and gates of NM5 and NM6 are shorted together, there are:
VDS＝VGS (2)
substituting equation (2) into equation (1) yields:
Figure BDA0002504121370000112
since there is no current in the gate of the MOS device, the drain current flows to the source completely, and the resistance R obtained by shifting the term of equation (3) is:
Figure BDA0002504121370000113
it can be seen that NM5 and NM6 are active resistors, and their resistance values are related to the size of the device, so that the resistance values can be controlled by controlling the width-to-length ratio of the device.
In summary, the present invention provides a level shifter with anti-protection, which has the advantages of simple structure, low power consumption, small area, and capability of preventing the power and ground from damaging the chip, and can be used for analog integrated circuits.
The technical principle of the present invention has been described above with reference to specific embodiments, which are merely preferred embodiments of the present invention. The protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. Other embodiments of the invention will occur to those skilled in the art without the exercise of inventive faculty, and such will fall within the scope of the invention.

Claims (8)

1. A level shift circuit with anti-protection, comprising:
the low-voltage input module, the high-voltage protection module, the PMOS load module with reverse connection protection and the output protection module;
the low-voltage input module is used for inputting a low-voltage differential signal LV _ INP/LV _ INN to be converted into a circuit and generating high and low levels to be input into the high-voltage protection module;
the high-voltage protection module is used for inputting high and low levels into a PMOS load module with reverse connection protection;
the PMOS load module with the reverse connection protection is used for moving the low-voltage level to the high-voltage level HV _ VDD and protecting the circuit when the chip ground is connected with the high voltage in a reverse way;
the output protection module is used for protecting the output circuit; the input is a high voltage level after level conversion, and a high voltage differential signal HV _ OUTP/HV _ OUTN is output.
2. The level shift circuit with reverse protection of claim 1, wherein the PMOS load module with reverse protection comprises three high voltage PMOS devices PM1, PM2, and PM 3;
the drain of the PM1 is connected with the drain of the NM3, the source is connected to a high-voltage power input end HV _ VDD, and the gate is connected to the drain of the PM 2;
the drain of the PM2 is connected with the drain of the NM4, the source is connected to a high-voltage power input terminal HV _ VDD, and the gate is connected to the drain of the PM 1.
3. The level shifter circuit with reverse protection as claimed in claim 2, wherein when the gate voltage of PM1 is lowered, PM1 is turned on; the voltage at the drain of PM1 is raised, the drain voltage of PM2 is lowered due to the connection of the drain of PM1 to the gate of PM2, and the speed of the reduction of the gate voltage of PM1 is increased due to the connection of the gate of PM1 to the drain of PM2, thus forming a positive feedback structure.
4. The level shift circuit with reverse protection as claimed in claim 2, wherein when the gate voltage of PM2 is decreased, PM2 is turned on, the voltage at the drain of PM2 is raised, the drain voltage of PM2 is decreased because the drain of PM2 is connected to the gate of PM1, and the speed of decrease of the gate voltage of PM2 is increased because the gate of PM2 is connected to the drain of PM1, so as to form a positive feedback structure.
5. The level shifter circuit with reverse protection as claimed in claim 2, wherein the high voltage PMOS device PM3 is a forward conducting structure, the source of PM3 is connected to the high voltage power input terminal HV _ VDD, the drain of PM3 is shorted to the gate and the substrate, a PN junction between the P-doped source and the N-doped substrate of the PMOS device is used to form a diode structure with the source pointing to the substrate, and the diode is used to conduct current in one direction to open the path when the power and ground are connected in reverse to protect the chip.
6. The level shifter circuit with reverse protection as claimed in claim 2, wherein the drain of the high voltage PMOS device PM3 is shorted to the gate and the substrate, and then connected to the substrate of PM1, PM 2; when the power supply and the ground are reversely connected, the path is disconnected, the substrates of the PM1 and the PM2 are equivalent to high voltage, reverse bias of drains in the PM1 and the PM2 and PN junctions of the substrates is guaranteed, current is prevented from flowing from the drains of the PM1 and the PM2 to the substrates to damage PMOS devices, and the chip is protected.
7. The level shifter circuit with reverse protection as claimed in claim 2, wherein said output protection module comprises two resistors R1, R2; one end of the resistor R1 is connected to the drain of the high-voltage NMOS device NM3 and the drain of the high-voltage PMOS device PM1, and the other end of the resistor R1 is connected to the high-voltage differential output end HV _ OUTP; one end of the resistor R2 is connected to the drain of the high-voltage NMOS device NM4 and the drain of the high-voltage PMOS device PM2, and the other end is connected to the high-voltage differential output terminal HV _ OUTN.
8. The level shift circuit with anti-reverse protection of claim 2, wherein the output protection module comprises NMOS devices NM5 and NM6, the drain of NM5 is shorted together with the gate and the substrate, and then connected to the drain of PM1 respectively; the drain electrode of the NM6 is shorted with the grid electrode and the substrate together and is respectively connected with the drain electrode of the PM 2; the source high voltage differential output ends of NM5 and NM6 are respectively connected with HV _ OUTP and HV _ OUTP.
CN202010440930.4A 2020-05-22 2020-05-22 Level conversion circuit with reverse connection protection Active CN111600594B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113890333A (en) * 2021-09-29 2022-01-04 赛卓电子科技（上海）有限公司 High-voltage stabilizing circuit with anti-reflection protection

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CN1355607A (en) * 2000-11-30 2002-06-26 点晶科技股份有限公司 Circuit with protection to error-polarity connection of power supply
CN102638034A (en) * 2012-04-01 2012-08-15 杭州科岛微电子有限公司 Reverse connection protection high pressure circuit of power supply
CN103824855A (en) * 2014-03-20 2014-05-28 绍兴光大芯业微电子有限公司 Complementary metal-oxide-semiconductor (CMOS) adjustment integrated circuit structure with power supply transposition protection function
CN108599130A (en) * 2018-07-27 2018-09-28 上海南麟电子股份有限公司 A kind of esd protection circuit and its implementation with reverse-connection preventing circuit
CN109245535A (en) * 2018-11-20 2019-01-18 广州市力驰微电子科技有限公司 Level switch module suitable for power management

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Publication number Priority date Publication date Assignee Title
CN1355607A (en) * 2000-11-30 2002-06-26 点晶科技股份有限公司 Circuit with protection to error-polarity connection of power supply
CN102638034A (en) * 2012-04-01 2012-08-15 杭州科岛微电子有限公司 Reverse connection protection high pressure circuit of power supply
CN103824855A (en) * 2014-03-20 2014-05-28 绍兴光大芯业微电子有限公司 Complementary metal-oxide-semiconductor (CMOS) adjustment integrated circuit structure with power supply transposition protection function
CN108599130A (en) * 2018-07-27 2018-09-28 上海南麟电子股份有限公司 A kind of esd protection circuit and its implementation with reverse-connection preventing circuit
CN109245535A (en) * 2018-11-20 2019-01-18 广州市力驰微电子科技有限公司 Level switch module suitable for power management

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113890333A (en) * 2021-09-29 2022-01-04 赛卓电子科技（上海）有限公司 High-voltage stabilizing circuit with anti-reflection protection

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