CN112186726A - ESD protection circuit, power supply and chip - Google Patents
ESD protection circuit, power supply and chip Download PDFInfo
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- CN112186726A CN112186726A CN202011367832.9A CN202011367832A CN112186726A CN 112186726 A CN112186726 A CN 112186726A CN 202011367832 A CN202011367832 A CN 202011367832A CN 112186726 A CN112186726 A CN 112186726A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
- H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
- H02H9/025—Current limitation using field effect transistors
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
- H02H9/047—Free-wheeling circuits
Abstract
The application relates to an ESD protection circuit, a power supply and a chip. The ESD protection circuit comprises a first diode, a second diode, a third diode, a fourth diode and an ESD clamping circuit; the anode of the first diode is respectively connected with the grounding end, the anode of the third diode and the output end of the ESD clamping circuit, and the cathode of the first diode is connected with the anode of the second diode and is used for being connected with a first power supply; the cathode of the second diode is respectively connected with the cathode of the fourth diode and the input end of the ESD clamping circuit; the cathode of the third diode is connected with the anode of the fourth diode and is used for connecting a second power supply; the ESD clamping circuit comprises a voltage bias circuit, a detection circuit, a maintaining circuit, a trigger circuit, a turn-off circuit and a discharge circuit; the voltage bias circuit design saves the circuit area and reduces the static power consumption of the voltage bias circuit. When an ESD event is detected, the discharge circuit is actively started to discharge ESD current. The chip outputs potential control during noise interference, and the high-burr resistance effect is good.
Description
Technical Field
The present application relates to the field of integrated circuit technologies, and in particular, to an ESD protection circuit, a power supply, and a chip.
Background
ESD (Electro-Static discharge) failure has become a current primary problem affecting the reliability of integrated circuit designs. An ESD event may occur in each link of chip manufacturing, testing, scribing, packaging, assembling, transporting, board-level and system-level assembling, finished product using and the like, because inevitable contact friction behavior between equipment and materials can generate a large amount of charge accumulation, if accumulated charges are not discharged timely, pins contacting the chip can flow into the chip along the pins, transient ESD current generated in the process can reach more than several amperes, the reliability of a gate oxide of an internal device can be threatened, the defects of the gate oxide and even the breakdown of the oxide layer can be formed, or internal metal wiring or the device can be directly heated and burnt, the IV curve of the device can be deviated by a light person, and the chip can be permanently failed by a heavy person.
In the implementation process, the inventor finds that at least the following problems exist in the conventional technology: the traditional ESD protection device has the problem of poor protection effect.
Disclosure of Invention
In view of the above, it is desirable to provide an ESD protection circuit, a power supply, and a chip that have excellent protection effects.
In order to achieve the above object, in one aspect, an embodiment of the present invention provides an ESD protection circuit, including a first diode, a second diode, a third diode, a fourth diode, and an ESD clamp circuit;
the anode of the first diode is respectively connected with the grounding end, the anode of the third diode and the output end of the ESD clamping circuit, and the cathode of the first diode is connected with the anode of the second diode and is used for being connected with a first power supply; the cathode of the second diode is respectively connected with the cathode of the fourth diode and the input end of the ESD clamping circuit; the cathode of the third diode is connected with the anode of the fourth diode and is used for connecting a second power supply;
the ESD clamping circuit comprises a voltage bias circuit, a detection circuit, a maintaining circuit, a trigger circuit, a turn-off circuit and a discharge circuit;
the detection circuit comprises a first inverter and a first RC circuit; the first RC circuit comprises a first resistor and a first capacitor; one end of the first resistor is connected with the cathode of the second diode, and the other end of the first resistor is respectively connected with one end of the first capacitor and the input end of the first phase inverter; the other end of the first capacitor is connected with the midpoint end of the voltage bias circuit; the first end of the voltage bias circuit is connected with the cathode of the second diode, and the second end of the voltage bias circuit is connected with the anode of the first diode;
the maintaining circuit comprises a first MOS tube, a second MOS tube, a third MOS tube, a second RC circuit and a second phase inverter; the second RC circuit comprises a second resistor and a second capacitor;
the grid electrode of the first MOS tube is connected with the output end of the first phase inverter, the drain electrode of the first MOS tube is connected with the drain electrode of the third MOS tube, and the source electrode of the first MOS tube is connected with the midpoint end of the voltage bias circuit; the grid electrode of the second MOS tube is respectively connected with the grid electrode of the third MOS tube, the first control end of the bleeder circuit and the output end of the second inverter, the source electrode is connected with the midpoint end of the voltage bias circuit, and the drain electrode is connected with one end of the second capacitor; the source electrode of the third MOS tube is connected with the cathode of the second diode and one end of the second resistor; the other end of the second resistor is connected with the input end of the second inverter and the other end of the second capacitor respectively;
the trigger circuit comprises a fourth MOS tube, a fifth MOS tube and a third resistor; the grid electrode of the fourth MOS tube is connected with the source electrode of the second MOS tube, the source electrode is connected with the grid electrode of the second MOS tube, and the drain electrode is respectively connected with the second control end of the bleeder circuit, one end of the third resistor and the grid electrode of the fifth MOS tube; the drain electrode of the fifth MOS tube is connected with the midpoint end of the voltage bias circuit, and the source electrode of the fifth MOS tube is grounded; the other end of the third resistor is grounded;
the turn-off circuit is used for conducting connection between the drain electrode of the fourth MOS tube and the ground according to the enabling signal of the chip; the bleeder circuit is used for receiving signals of the first control end and the second control end, and conducting the connection between the cathode of the second diode and the ground, and the connection between the cathode of the fourth diode and the ground.
In one embodiment, the voltage bias circuit comprises a first voltage division circuit and a second voltage division circuit;
one end of the first voltage division circuit is connected with the cathode of the second diode, and the other end of the first voltage division circuit is connected with one end of the second voltage division circuit and the other end of the first capacitor; the other end of the second voltage division circuit is grounded;
in one embodiment, the first voltage division circuit comprises a sixth MOS transistor and a seventh MOS transistor; the second voltage division circuit comprises an eighth MOS tube and a ninth MOS tube;
the source electrode of the sixth MOS tube is connected with the cathode of the second diode, and the drain electrode of the sixth MOS tube is respectively connected with the grid electrode of the sixth MOS tube and the source electrode of the seventh MOS tube; the drain electrode of the seventh MOS tube is respectively connected with the source electrode of the seventh MOS tube and the source electrode of the eighth MOS tube; the drain electrode of the eighth MOS tube is respectively connected with the drain electrode of the eighth MOS tube and the source electrode of the ninth MOS tube; the grid electrode and the drain electrode of the ninth MOS tube are both grounded; the drain electrode of the seventh MOS tube is a midpoint end.
In one embodiment, the turn-off circuit comprises a tenth MOS tube and an enabling switch;
the source electrode of the tenth MOS tube is grounded, the drain electrode of the tenth MOS tube is connected with the drain electrode of the fourth MOS tube, and the grid electrode of the tenth MOS tube is connected with the chip through the enabling switch.
In one embodiment, the bleeder circuit comprises an eleventh MOS transistor and a twelfth MOS transistor;
the drain electrode of the eleventh MOS tube is connected with the cathode of the second diode, the source electrode of the eleventh MOS tube is connected with the drain electrode of the twelfth MOS tube, and the grid electrode of the eleventh MOS tube is connected with the output end of the second phase inverter; the source electrode of the twelfth MOS tube is grounded, and the grid electrode of the twelfth MOS tube is connected with the drain electrode of the fourth MOS tube.
In one embodiment, the eleventh MOS transistor and the twelfth MOS transistor are both N-MOS transistors.
In one embodiment, the cascode structures of the eleventh MOS transistor and the twelfth MOS transistor are in contact with the corresponding P + substrate.
In one embodiment, the first MOS tube is an N-MOS tube; the second MOS tube is an N-MOS tube; the third MOS tube is a P-MOS tube.
In one aspect, embodiments of the present invention further provide a power supply including the ESD protection circuit according to any one of the above embodiments.
In another aspect, an embodiment of the present invention further provides a chip including the ESD protection circuit as described in any one of the above.
One of the above technical solutions has the following advantages and beneficial effects:
the ESD protection circuit comprises a first diode, a second diode, a third diode, a fourth diode and an ESD clamping circuit; the anode of the first diode is respectively connected with the grounding end, the anode of the third diode and the output end of the ESD clamping circuit, and the cathode of the first diode is connected with the anode of the second diode and is used for being connected with a first power supply; the cathode of the second diode is respectively connected with the cathode of the fourth diode and the input end of the ESD clamping circuit; the cathode of the third diode is connected with the anode of the fourth diode and is used for connecting a second power supply; the ESD clamping circuit comprises a voltage bias circuit, a detection circuit, a maintaining circuit, a trigger circuit, a turn-off circuit and a discharge circuit; the first power supply and the second power supply share one ESD clamping circuit to discharge positive high-voltage static electricity, the circuit area is saved through the design of the voltage bias circuit, and meanwhile, the static power consumption of the voltage bias circuit is reduced. In the detection circuit, the parameter setting of the first RC circuit can ensure that the voltage at the vrc end does not suddenly change when the rising edge of the power supply is detected, and the voltage can be kept low when the power supply is quickly powered on. In the maintaining circuit, the level signal at the output end of the second inverter is maintained for a certain time, which can be determined by the parameters of the second RC circuit, so that the first control end of the bleeding circuit is in a high level state. The trigger circuit ensures that the second control end of the bleeder circuit is in a high level state, so that the bleeder circuit keeps a bleeder state. And finally, a turn-off circuit is introduced into the clamping circuit, so that when the chip system works normally, an enable signal is output to close the ESD clamping circuit, and the power noise interference resistance of the ESD protection circuit is improved.
Drawings
The foregoing and other objects, features and advantages of the application will be apparent from the following more particular description of preferred embodiments of the application, as illustrated in the accompanying drawings. Like reference numerals refer to like parts throughout the drawings, and the drawings are not intended to be drawn to scale in actual dimensions, emphasis instead being placed upon illustrating the subject matter of the present application.
FIG. 1 is a block diagram of a conventional ESD protection circuit in one embodiment;
FIG. 2 is a first schematic block diagram of an ESD protection circuit according to one embodiment;
FIG. 3 is a block diagram of an ESD clamp according to one embodiment;
FIG. 4 is a first schematic block diagram of a voltage bias circuit in one embodiment;
FIG. 5 is a second schematic block diagram of a voltage bias circuit in one embodiment;
fig. 6 is a block diagram of the bleeder circuit in one embodiment.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are set forth in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, a first resistance may be referred to as a second resistance, and similarly, a second resistance may be referred to as a first resistance, without departing from the scope of the present application. The first resistance and the second resistance are both resistances, but they are not the same resistance.
It is to be understood that "connection" in the following embodiments is to be understood as "electrical connection", "communication connection", and the like if the connected circuits, modules, units, and the like have communication of electrical signals or data with each other.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.
In the conventional technology, an ESD clamp is mainly disposed at a power port, and as shown in fig. 1, when a chip normally operates, the ESD clamp is turned off. When an ESD event occurs, the ESD circuit is started to discharge ESD energy PC to be a clamping circuit. Currently, there are two types of ESD discharge: 1) active discharge, wherein the ESD discharge circuit is kept open all the time in the ESD event process; 2) and passive discharge, namely starting the ESD discharge circuit when triggering the parasitic transistor characteristic of the ESD device and entering a snapback (voltage retrace, reduced withstand voltage) state.
However, the conventional technical solutions have the following problems: the conventional high voltage tolerant power clamp architecture clamps the power to the chip common ground, as shown in fig. 1, and the conventional architecture has the following disadvantages:
1) the clamp circuit adopts active discharge, is usually sensitive to a rising edge and cannot support the power supply to be quickly electrified; in addition, the power source burr resistance is poor, the ESD tube is easily turned on by mistake due to the fact that burrs are superposed on a power source, snapback Voltag (return voltage) exists in the ESD tube, and Latch (Latch) is easily caused, so that power consumption is increased, and even chips are burnt.
2) The clamp circuit adopts passive bleeding, can lead to trigger voltage too high, is unfavorable for protecting internal circuit, owing to rely on ESD device to get into dark snapback (turn back) and bleed in addition, this leads to the holding voltage ratio lower, is caught by high burr trigger Latch easily, leads to the chip to burn out.
3) The traditional power port for directly supplying power externally needs to withstand higher voltage than internal IO voltage, and the problem of withstand voltage needs to be solved by adding a mask (mask plate), so that the process cost is increased; or a cascade structure (cascode structure) is adopted, but in order to ensure the reliability of the gate oxide layer of the ESD discharge tube, voltage bias is required, which results in that a voltage bias circuit is required for each power supply port, and static loss is increased.
The ESD protection circuit provided by the application can effectively solve the problems.
In one embodiment, as shown in fig. 2, there is provided an ESD protection circuit including a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, and an ESD clamp PC;
the anode of the first diode D1 is connected to the ground, the anode of the third diode D3 and the output terminal of the ESD clamp circuit, respectively, and the cathode is connected to the anode of the second diode D2 and is used for connecting to the first power supply VBUS; the cathode of the second diode D2 is connected to the cathode of the fourth diode D4 and the input terminal of the ESD clamp circuit, respectively; the cathode of the third diode D3 is connected to the anode of the fourth diode D4 and is used for connecting the second power source VBAT;
as shown in fig. 3, the ESD clamp circuit includes a voltage bias circuit 10, a detection circuit 20, a sustain circuit 30, a trigger circuit 40, a shutdown circuit 50, and a bleed circuit 60;
the detection circuit 20 includes a first inverter INV1 and a first RC circuit 101; the first RC circuit 101 comprises a first resistor R1 and a first capacitor C1; one end of the first resistor R1 is connected to the cathode of the second diode D2, and the other end is connected to one end of the first capacitor C1 and the input end of the first inverter INV1, respectively; the other end of the first capacitor C1 is connected to the midpoint end of the voltage bias circuit 10; the first end of the voltage bias circuit 10 is connected to the cathode of the second diode D2, and the second end is connected to the anode of the first diode D1;
the maintaining circuit 30 includes a first MOS transistor MN1, a second MOS transistor MN2, a third MOS transistor MP1, a second RC circuit, and a second inverter INV 2; the second RC circuit comprises a second resistor R2 and a second capacitor C2;
the gate of the first MOS transistor MN1 is connected to the output end of the first inverter INV1, the drain is connected to the drain of the third MOS transistor MP1, and the source is connected to the midpoint of the voltage bias circuit 10; the gate of the second MOS transistor MN2 is connected to the gate of the third MOS transistor MP1, the first control end of the bleeder circuit 60, and the output end of the second inverter INV2, respectively, the source is connected to the midpoint end of the voltage bias circuit 10, and the drain is connected to one end of the second capacitor C2; the source of the third MOS transistor MP1 is connected to the cathode of the second diode D2 and one end of the second resistor R2; the other end of the second resistor R2 is connected to the input end of the second inverter INV2 and the other end of the second capacitor C2, respectively;
the trigger circuit 40 comprises a fourth MOS transistor MP2, a fifth MOS transistor MN3 and a third resistor R3; the gate of the fourth MOS transistor MP2 is connected to the source of the second MOS transistor MN2, the source is connected to the gate of the second MOS transistor MN2, and the drain is connected to the second control end of the bleeder circuit 60, one end of the third resistor R3, and the gate of the fifth MOS transistor MN3, respectively; the drain electrode of the fifth MOS transistor MN3 is connected to the midpoint end of the voltage bias circuit 10, and the source electrode is grounded; the other end of the third resistor is grounded;
the turn-off circuit 50 is used for turning on or off the connection between the drain of the fourth MOS transistor MP2 and the ground according to the enable signal of the chip; the bleeder circuit is used for receiving signals of the first control end and the second control end, and conducting the connection between the cathode of the second diode and the ground, and the connection between the cathode of the fourth diode and the ground.
Specifically, the first power source may be a battery VBAT, and the second power source may be an external serial power source VBUS. In this embodiment, the first power supply and the second power supply share a clamp circuit. Two more diodes are arranged, so that one ESD clamping circuit is saved, the circuit area is saved, and the static power consumption of the voltage bias circuit is reduced. In one specific example, the first and third diodes are N +/PWELL diodes and the second and fourth diodes are P +/NWELL diodes. Note that an intersection VCC between the cathode of the second diode, the cathode of the fourth diode, and the input terminal of the ESD clamp circuit is a virtual power domain. When a positive high-voltage electrostatic ESD event occurs at any power supply port, the ESD event is discharged to the virtual power supply domain VCC through the P +/NW diode (D2 or D4). When ESD events of negative high voltage static electricity occur at any power supply port, the ESD is discharged to the ground through the N +/NW diode (D1 or D3).
The ESD clamp circuit comprises a voltage bias circuit, a detection circuit, a maintaining circuit, a trigger circuit, a turn-off circuit and a discharge circuit. Specifically, a voltage bias circuit is used to provide a midpoint voltage, which in one particular example satisfies Vmid = VCC/2.
The detection circuit comprises a first inverter and a first RC circuit and is used for quickly powering up the power supply. The time parameter can be confirmed by the parameter setting of the first RC circuit. It should be noted that the trigger rising edge of ESD is within 10 ns. The time parameter can be controlled around 25ns by the choice of the parameters of the first resistor and the first capacitor in the first RC-circuit. One end (vrc) of the first capacitor is connected with the first resistor, and the other end is connected with the midpoint end of the voltage bias circuit. Specifically, the first capacitor C1 ensures that the voltage at vrc does not change abruptly when detecting the rising edge of the power supply during fast power-up, and can maintain a low voltage during fast power-up. The input end of the first inverter INV1 is connected to the terminal vrc of the first capacitor, and when the voltage at the terminal vrc is low, the output end Vout of the first inverter INV1 outputs high level, otherwise, outputs low level. In this embodiment, the first RC circuit is used for monitoring the rising edge of the power supply, and the RC time constant is changed by adjusting the resistance of the first resistor and the first capacitance (specifically, according to the time constant calculation formula: τ = RC), so as to ensure insensitivity to normal power supply power-up.
The holding circuit is used for holding the high level output by the first inverter INV1, outputting the high level at Vout, starting the holding circuit, and outputting the high level at the output end of the second inverter. In one particular example, the hold time is approximately 600ns, thereby ensuring that the bleeding circuit is fully bleeding. When the output end Vout of the first inverter outputs a high level, the first MOS transistor MN1 is turned on, so that the input end of the second inverter INV2 is at a low level, thereby ensuring that the second inverter outputs a high level. The output end of the second inverter is connected with the grid electrode of the second MOS tube. Therefore, the second MOS transistor is turned on and the third MOS transistor is turned off, and the voltage at the input end vrc2 of the second inverter INV2 is not suddenly changed to the high level by the second capacitor in the second RC circuit, so that the low level of vrc2 can be maintained, and the output end vhg of the second inverter INV2 outputs the high level. In one embodiment, the first MOS tube is an N-MOS tube; the second MOS tube is an N-MOS tube; the third MOS tube is a P-MOS tube.
The trigger circuit is used for ensuring that the bleeder circuit is in a bleeder state. The source of the fourth MOS transistor is connected to the gate of the second MOS transistor MN2, that is, to the midpoint of the voltage bias circuit. When an ESD event occurs, the voltage at the output end vhg of the second inverter INV2 is higher than the midpoint Vmid of the voltage bias circuit, so the source voltage of the fourth MOS transistor MP2 is higher than the gate voltage, and MP2 is turned on. The drain vlg of the fourth MOS transistor MP2 outputs a high level, the fifth MOS transistor MN3 is turned on, and the voltage Vmid at the midpoint of the voltage bias circuit is pulled down to VSS, so that the fourth MOS transistor is ensured to be in a conductive state, that is, the drain of the fourth MOS transistor MP2 outputs a high level, and the bleeder circuit is always in a bleeder state.
And the turn-off circuit is used for turning on the connection between the drain electrode of the fourth MOS tube and the ground according to the signal of the chip. When the chip works normally, a high level signal is output to the turn-off circuit, so that the voltage at the vlg end is always VSS, and ESD false triggering caused by power supply noise can be avoided.
Further, the voltage bias circuit may be any circuit capable of providing a bias voltage in the art. The bleeder circuit may be any circuit in the art capable of performing electrostatic discharge according to the first control terminal and the second control terminal. And conducting the connection between the VCC end and the VSS end through the high and low levels of the first control end and the second control end.
It should be noted that when an ESD event of positive high voltage static electricity occurs at any power port (i.e. the port of the first power source or the port of the second power source), the ESD event is discharged to the virtual power domain VCC through the P +/NW diode (D2 or D4), the R1C1 of the first RC circuit in the detection circuit needs to charge the C1, the voltage does not change abruptly, i.e. vrc is at low level, the output voltage vout through the inverter INV1 is at high level, so that the sustain module is turned on, MN1 in the sustain module is turned on, the drain terminal is at low level relative to the VCC voltage, i.e. vrc2 is at low level, the output voltage vhg through the inverter INV2 is at VCC voltage, the gate terminals of MP1 and MN2 are pulled high, so that MP1 is turned off and MN2 is turned on, and the delay circuit formed by R2 and C2 is turned on at the same time, so that the. Also because vhg reaches the VCC voltage far higher than vmid voltage at this time, so that MP2 is turned on, the tube voltage drop of MP2 is about 0.3V, so that the gate voltage vlg of the second bleeder is about equal to the gate voltage vhg of the first bleeder, while the gate terminal of MN3 is high, MN3 is turned on, vmid is pulled to VSS through MN3 feedback, and the gate terminal of MP2 is continuously low, so that MP2 keeps on state. Therefore, during an ESD event, the voltages of the gates (gates) of the first discharging tube MB1 and the second discharging tube MB2 of the discharging circuit are both VCC, and the turn-on time is about 600ns, which is enough to discharge the ESD completely.
According to the ESD protection circuit, the first power supply and the second power supply share the ESD clamping circuit to discharge positive high-voltage static electricity, the circuit area is saved through the circuit design, and meanwhile the static power consumption of the voltage bias circuit is reduced. In the detection circuit, whether the normal power supply is powered on or the ESD event can be distinguished through parameter setting of the first RC circuit. In the maintaining circuit, the level signal at the output end of the second inverter is maintained for a certain time, which can be determined by the parameters of the second RC circuit, so that the first control end of the bleeding circuit is in a high level state. The trigger circuit ensures that the second control end of the bleeder circuit is in a high level state, so that the bleeder circuit keeps a bleeder state. And finally, a turn-off circuit is introduced into the clamping circuit, so that when the chip system works normally, an enable signal is output to close the ESD clamping circuit, and the power noise interference resistance of the ESD protection circuit is improved. Under a 2.5V device, a 5V ESD power supply clamp can be realized and supported, the normal 5V work of a chip is ensured, and all devices of the ESD power supply clamp circuit are in a safe working area; when an ESD event is detected, the discharge circuit is actively started to discharge ESD current, and when noise interference is detected, high burrs caused by plugging and unplugging in the 5.0V USB power supply process can be prevented through the control of the chip output potential; meanwhile, the circuit is suitable for a multi-power-supply control ESD protection circuit and can support multiplexing high-speed 3.3V IO communication of 5V power supply pins.
In one embodiment, as shown in fig. 4, the voltage bias circuit 10 includes a first voltage dividing circuit 101 and a second voltage dividing circuit 103;
one end of the first voltage divider circuit 101 is connected to the cathode of the second diode D2 (not shown in fig. 4), and the other end is connected to one end of the second voltage divider circuit 103 and the other end of the first capacitor C1 (not shown in fig. 4), respectively; the other end of the second voltage dividing circuit 103 is grounded VSS (t is not shown in fig. 4);
specifically, the first voltage dividing circuit and the second voltage dividing circuit are connected in series, one end of the voltage bias circuit is connected to VCC, the other end of the voltage bias circuit is connected to VSS, and the intersection point of the first voltage dividing circuit and the second voltage dividing circuit is the midpoint. The voltage value of the midpoint end is obtained according to the voltage division of the first voltage division circuit and the second voltage division circuit.
The first voltage dividing circuit and the second voltage dividing circuit may have any structures as long as the voltage division is the same.
In one embodiment, as shown in fig. 5, the first voltage dividing circuit includes a sixth MOS transistor MP3 and a seventh MOS transistor MP 4; the second voltage division circuit comprises an eighth MOS transistor MP5 and a ninth MOS transistor MP 6;
the source electrode of the sixth MOS transistor MP3 is connected to the cathode of the second diode, and the drain electrode of the sixth MOS transistor MP3 is connected to the gate electrode of the sixth MOS transistor MP3 and the source electrode of the seventh MOS transistor MP4, respectively; the drain electrode of the seventh MOS transistor MP4 is connected to the source electrode of the seventh MOS transistor MP4 and the source electrode of the eighth MOS transistor MP5, respectively; the drain electrode of the eighth MOS transistor MP5 is connected to the drain electrode of the eighth MOS transistor MP5 and the source electrode of the ninth MOS transistor MP6, respectively; the gate and the drain of the ninth MOS transistor MP6 are both grounded; the drain of the seventh MOS transistor MP4 is a midpoint terminal. It is to be understood that the first voltage dividing circuit and the second voltage dividing circuit may also take other forms, and are not limited to the forms already mentioned in the above embodiments, as long as the functions of voltage division can be achieved. In a specific example, the number of the MOS transistors in the first voltage division circuit may be any, and the connection relationship between the MOS transistors may refer to the connection relationship between the sixth MOS transistor and the seventh MOS transistor. Correspondingly, the number of the MOS transistors in the second voltage division circuit should be the same as that of the MOS transistors in the first voltage division circuit.
In one embodiment, the turn-off circuit comprises a tenth MOS tube and an enabling switch;
the source electrode of the tenth MOS tube is grounded, the drain electrode of the tenth MOS tube is connected with the drain electrode of the fourth MOS tube, and the grid electrode of the tenth MOS tube is connected with the chip through the enabling switch.
Specifically, the source electrode of the tenth MOS transistor is grounded, the drain electrode is connected to the source electrode of the fourth MOS transistor, and the gate electrode is connected to the chip through the enable switch. The tenth MOS tube pulls down the voltage at the end vlg to VSS according to the enable signal output by the chip, so that the bleeder circuit cannot operate. Specifically, when the enable signal EN =1 is asserted, the connection between the drain of the fourth MOS transistor and the ground is turned on.
In one embodiment, as shown in fig. 6, the bleeder circuit comprises an eleventh MOS transistor MB1 and a twelfth MOS transistor MB 2;
the drain of the eleventh MOS transistor MB1 is connected to the cathode of the second diode D2 (not shown in fig. 6), the source is connected to the drain of the twelfth MOS transistor MB2, and the gate is connected to the output terminal of the second inverter; the source of the twelfth MOS transistor MB2 is grounded, and the gate is connected to the drain of the fourth MOS transistor.
Specifically, the bleeder circuit controls the connection between VCC and VSS through an eleventh MOS transistor MB1 and a twelfth MOS transistor MB 2. The grid electrode of the eleventh MOS tube is connected with the output end of the second phase inverter, and the grid electrode of the twelfth MOS tube is connected with the drain electrode of the fourth MOS tube. In this embodiment, only the gate of the eleventh MOS transistor and the gate of the twelfth MOS transistor need to be kept at a high level, and the communication between VCC and VSS can be conducted, so that the discharging is performed.
In one embodiment, the eleventh MOS transistor and the twelfth MOS transistor are both N-MOS transistors.
In one embodiment, the cascode structures of the eleventh MOS transistor and the twelfth MOS transistor are in contact with the corresponding P + substrate.
Specifically, optimize and let out the pipe (also eleventh MOS pipe and twelfth MOS pipe), the cascade constitutional unit of every pipe that lets out corresponds a p + substrate contact for there is not snapback (voltage is turned back) in the pipe of letting out, overcomes that traditional scheme lets out the pipe and has snapback to the sensitive problem of high burr, has promoted power port anti-burr ability simultaneously.
In one embodiment, there is also provided a power supply comprising an ESD protection circuit as in any above.
In one embodiment, there is also provided a chip including the ESD protection circuit as described in any of the above.
It should be noted that, when the dual power supplies share one clamp circuit, the following four situations can be divided to ensure the normal operation of the circuit:
the first condition is as follows: when the power supply is normally powered on (VBUS or VBAT is powered on), the rising time is generally ms, which is much longer than the RC time constant formed by R1 and C1, so the node vrc follows the VCC voltage, so the inverter INV1 outputs a low level, thus the inactive output of the module is maintained at a low level, i.e., vhg = vmid, so MP2 is turned off, so vlg is pulled down to VSS through the resistor R3, and the second ESD bleeder MB2 (i.e., the twelfth MOS transistor) is turned off, so that all the transistors of the whole ESD clamp circuit are in a safe working area, and the normal operation of the chip is not affected.
Case two: when one power supply (a battery) supplies power and the other power supply (an interface charging power supply) is powered on instantly, the ESD release circuit cannot be triggered by mistake without considering the power-on speed. Specifically, VBAT battery supplies power, the chip operates normally at this time, VBUS is inserted into 5.0V USB to charge the battery, and the system on chip has a voltage of about 3V, so that EN is at a high level, and therefore the gate voltage vlg of the second bleeder (i.e., the twelfth MOS transistor) is pulled to VSS (i.e., 0V), and at this time, the second bleeder MB2 is not turned on.
Case three: when an ESD event of positive high voltage static electricity occurs at any power port, the ESD event is discharged to the virtual power domain VCC through the P +/NW diode (D2 or D4), the output voltage vout of the detection module (i.e. the detection circuit) is at a high level, so that the sustain module (i.e. the sustain circuit) is turned on, the output voltage vhg of the sustain module is a VCC voltage, so that the MP1 is turned off and the MN2 is turned on, and the delay circuit formed by R2 and C2 is turned on at the same time, so that the ESD discharge time is about 600 ns. Since vhg is much higher than vmid, MP2 is turned on, so that the gate voltage vlg of the second bleeder is approximately equal to the gate voltage vhg of the first bleeder (i.e., the eleventh MOS transistor), and vmid is pulled to VSS through MN3 feedback, so that MP2 keeps on state. Therefore, during an ESD event, the voltages of the gates (gates) of the first and second discharging pipes of the discharging circuit are both VCC, and the turn-on time is about 600ns, which is enough to discharge the ESD completely.
Case four: when the ESD event of negative high-voltage static electricity occurs at the power supply port, negative ESD current is discharged through the N +/PW diode (D1 or D3).
In the description herein, references to the description of "some embodiments," "other embodiments," "desired embodiments," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. An ESD protection circuit is characterized by comprising a first diode, a second diode, a third diode, a fourth diode and an ESD clamping circuit;
the anode of the first diode is respectively connected with a grounding end, the anode of the third diode and the output end of the ESD clamping circuit, and the cathode of the first diode is connected with the anode of the second diode and is used for being connected with a first power supply; the cathode of the second diode is respectively connected with the cathode of the fourth diode and the input end of the ESD clamping circuit; the cathode of the third diode is connected with the anode of the fourth diode and is used for connecting a second power supply;
the ESD clamping circuit comprises a voltage bias circuit, a detection circuit, a maintaining circuit, a trigger circuit, a turn-off circuit and a discharge circuit;
the detection circuit comprises a first inverter and a first RC circuit; the first RC circuit comprises a first resistor and a first capacitor; one end of the first resistor is connected with the cathode of the second diode, and the other end of the first resistor is respectively connected with one end of the first capacitor and the input end of the first phase inverter; the other end of the first capacitor is connected with the midpoint end of the voltage bias circuit; the first end of the voltage bias circuit is connected with the cathode of the second diode, and the second end of the voltage bias circuit is connected with the anode of the first diode;
the maintaining circuit comprises a first MOS tube, a second MOS tube, a third MOS tube, a second RC circuit and a second phase inverter; the second RC circuit comprises a second resistor and a second capacitor;
the grid electrode of the first MOS tube is connected with the output end of the first phase inverter, the drain electrode of the first MOS tube is connected with the drain electrode of the third MOS tube, and the source electrode of the first MOS tube is connected with the midpoint end of the voltage bias circuit; the grid electrode of the second MOS tube is respectively connected with the grid electrode of the third MOS tube, the first control end of the bleeder circuit and the output end of the second inverter, the source electrode is connected with the midpoint end of the voltage bias circuit, and the drain electrode is connected with one end of the second capacitor; the source electrode of the third MOS tube is connected with the cathode of the second diode and one end of the second resistor; the other end of the second resistor is respectively connected with the input end of the second inverter and the other end of the second capacitor;
the trigger circuit comprises a fourth MOS transistor, a fifth MOS transistor and a third resistor; the grid electrode of the fourth MOS tube is connected with the source electrode of the second MOS tube, the source electrode of the fourth MOS tube is connected with the grid electrode of the second MOS tube, and the drain electrode of the fourth MOS tube is respectively connected with the second control end of the bleeder circuit, one end of the third resistor and the grid electrode of the fifth MOS tube; the drain electrode of the fifth MOS tube is connected with the midpoint end of the voltage bias circuit, and the source electrode of the fifth MOS tube is grounded; the other end of the third resistor is grounded;
the turn-off circuit is used for switching on or off the connection between the drain electrode of the fourth MOS tube and the ground according to an enabling signal of the chip; the bleeder circuit is used for receiving signals from the first control end and the second control end, and conducting the connection between the cathode of the second diode and the ground, and the connection between the cathode of the fourth diode and the ground.
2. The ESD protection circuit of claim 1, wherein the voltage bias circuit comprises a first voltage divider circuit and a second voltage divider circuit;
one end of the first voltage division circuit is connected with the cathode of the second diode, and the other end of the first voltage division circuit is connected with one end of the second voltage division circuit; the other end of the second voltage division circuit is grounded.
3. The ESD protection circuit of claim 2, wherein the first voltage divider circuit comprises a sixth MOS transistor and a seventh MOS transistor; the second voltage division circuit comprises an eighth MOS transistor and a ninth MOS transistor;
the source electrode of the sixth MOS tube is connected with the cathode of the second diode, and the drain electrode of the sixth MOS tube is respectively connected with the grid electrode of the sixth MOS tube and the source electrode of the seventh MOS tube; the drain electrode of the seventh MOS tube is respectively connected with the source electrode of the seventh MOS tube and the source electrode of the eighth MOS tube; the drain electrode of the eighth MOS tube is respectively connected with the drain electrode of the eighth MOS tube and the source electrode of the ninth MOS tube; the grid electrode and the drain electrode of the ninth MOS tube are both grounded; and the drain electrode of the seventh MOS tube is the midpoint end.
4. The ESD protection circuit of claim 1, wherein the turn-off circuit comprises a tenth MOS transistor and an enable switch;
and the source electrode of the tenth MOS tube is grounded, the drain electrode of the tenth MOS tube is connected with the drain electrode of the fourth MOS tube, and the grid electrode of the tenth MOS tube is connected with the chip through the enabling switch.
5. The ESD protection circuit of claim 1, wherein the bleeder circuit comprises an eleventh MOS transistor and a twelfth MOS transistor;
the drain electrode of the eleventh MOS tube is connected with the cathode of the second diode, the source electrode of the eleventh MOS tube is connected with the drain electrode of the twelfth MOS tube, and the grid electrode of the eleventh MOS tube is connected with the output end of the second phase inverter; and the source electrode of the twelfth MOS tube is grounded, and the grid electrode of the twelfth MOS tube is connected with the drain electrode of the fourth MOS tube.
6. The ESD protection circuit of claim 5, wherein the eleventh MOS transistor and the twelfth MOS transistor are both N-MOS transistors.
7. The ESD protection circuit of claim 6, wherein the cascode structures of the eleventh MOS transistor and the twelfth MOS transistor are in contact with the corresponding P + substrate.
8. The ESD protection circuit of claim 1, wherein the first MOS transistor is an N-MOS transistor; the second MOS tube is an N-MOS tube; the third MOS tube is a P-MOS tube.
9. A power supply comprising an ESD protection circuit as claimed in any one of claims 1 to 8.
10. A chip comprising the ESD protection circuit of any one of claims 1 to 8.
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| CN113075441A (en) * | 2021-05-12 | 2021-07-06 | 国硅集成电路技术(无锡)有限公司 | Input voltage detection circuit and interface circuit thereof |
| CN114597204A (en) * | 2022-05-10 | 2022-06-07 | 芯翼信息科技(上海)有限公司 | Protective circuit |
| CN116470476A (en) * | 2023-02-24 | 2023-07-21 | 北京中电华大电子设计有限责任公司 | Electrostatic discharge circuit and electronic device |
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