CN106877303A - The power clamp electrostatic discharge circuit of tunable trigger voltage, chip and communication terminal - Google Patents
The power clamp electrostatic discharge circuit of tunable trigger voltage, chip and communication terminal Download PDFInfo
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- CN106877303A CN106877303A CN201710214456.1A CN201710214456A CN106877303A CN 106877303 A CN106877303 A CN 106877303A CN 201710214456 A CN201710214456 A CN 201710214456A CN 106877303 A CN106877303 A CN 106877303A
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- transistor
- trigger
- electrostatic discharge
- nmos pass
- latch
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
- H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/042—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage comprising means to limit the absorbed power or indicate damaged over-voltage protection device
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
- H03F1/303—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters using a switching device
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Logic Circuits (AREA)
Abstract
Power clamp electrostatic discharge circuit, chip and communication terminal the invention discloses a kind of tunable trigger voltage.The power clamp electrostatic discharge circuit includes timer, trigger, latch, bleeder circuit, the output end of timer is connected with the input of trigger, the first phase inverter is provided between the output end of timer and latch input, the output end of trigger is connected with another input of latch, and the output end of latch is connected with bleeder circuit；One end of first resistor output end respectively with trigger, another input of latch are connected, and other end output end respectively with latch, leadage circuit are connected.The power clamp electrostatic discharge circuit has adjustable trigger voltage, can complete quick static electricity discharge electric current to realize comprehensively protection circuit element.
Description
Technical field
The present invention relates to a kind of power clamp electrostatic discharge circuit of tunable trigger voltage, also relate to include the power supply
The IC chip of clamper electrostatic discharge circuit and corresponding communication terminal, belong to technical field of radio frequency integrated circuits.
Background technology
Most of radio-frequency power amplifier is fabricated by based on SiGe BiCMOS technologies, its operating voltage range from
Change between 3V to 6V.It is optimal to provide usually using envelope-tracking method in the radio system being powered using battery
Radio-frequency performance, and can realize reducing its power consumption.When using envelope-tracking method, envelope-tracking power supply voltage is continuous adjustment
, and the spike of supply voltage can be avoided the occurrence of while peak efficiencies are obtained in the energy needed for particular moment provides.
Using this radio-frequency modulations technology, the rise time of spike within 20ns, enables crest voltage to reach and cell voltage phase
Same height.
In the circuit design of current radio-frequency power amplifier, static discharge (being abbreviated as ESD, similarly hereinafter) power supply is introduced
Clamp technology, it can suppress zooming high voltage spike, and occur to touch when voltage is higher than supply voltage (3~6V)
Hair, carries out power clamp.Meanwhile, also there is low breakdown voltage comprising some in the circuit design process of radio-frequency power amplifier
Cmos device, these cmos devices work under the conditions of 1.8V and 3.3V.In order in suppressing RF power amplifier circuit
Due to voltage spikes and related device is protected, need to add with low trigger voltage in the design of RF power amplifier circuit
Power clamp device.
In sum, in a complete mixed signal RF IC design, radio-frequency power amplifier, attached I/
O devices and other peripheral circuits may have different source voltage requirements, in order to more comprehensively protection circuit element,
Need the various power clamp electrostatic discharge circuits with different trigger voltages of exploitation.But different power clamp static discharge electricity
Road needs specially to be customized according to power supply requirement, causes its development to have very big workload.So, in order that power supply
Clamper electrostatic discharge circuit realizes preferable service behaviour, designs a kind of power clamp static discharge with tunable trigger voltage
Circuit is significant in the design application of mixed signal RF IC.
The content of the invention
Primary technical problem to be solved by this invention is that the power clamp electrostatic for providing a kind of tunable trigger voltage is put
Circuit.
Another technical problem to be solved by this invention is to provide a kind of including the power clamp electrostatic discharge circuit
IC chip and corresponding communication terminal.
In order to realize foregoing invention purpose, the present invention uses following technical schemes：
A kind of first aspect according to embodiments of the present invention, there is provided the power clamp static discharge electricity of tunable trigger voltage
Road, including timer, trigger, latch, bleeder circuit, the output end of the timer connect with the input of the trigger
Connect, the first phase inverter, the trigger are provided between the output end of the timer and an input of the latch
Output end be connected with another input of the latch, the output end of the latch is connected with the bleeder circuit；
One end of first resistor output end respectively with the trigger, another input of the latch are connected, the other end point
Output end, the leadage circuit not with the latch are connected.
Wherein more preferably, the timer uses RC clock circuits, and the RC clock circuits are by a resistance and an electricity
Appearance is in series, and one end of the resistance is connected with supply voltage, and the other end of the resistance connects with the top crown of the electric capacity
Connect, the bottom crown ground connection of the electric capacity；
The timer is used to detect that differentiation is esd pulse or normal power supply electrifying pulse, and according to testing result
It is turned on and off the power clamp electrostatic discharge circuit.
Wherein more preferably, the trigger is by resitstance voltage divider, the second nmos pass transistor, the second PMOS transistor and two
Pole pipe is constituted；The resitstance voltage divider is made up of second resistance with 3rd resistor, one end of the second resistance and the described 3rd
Resistance one end connection, this one end that the second resistance is connected with the 3rd resistor respectively with the 2nd NMOS crystal
The drain electrode of pipe, the anode of the diode are connected and intersect at same node, the negative electrode of the diode and the latch
One end connection of another input and the first resistor, the other end of the second resistance and the 2nd PMOS crystal
The drain electrode connection of pipe, the other end of the 3rd resistor, the source electrode of second nmos pass transistor are grounded respectively, and described second
The grid of nmos pass transistor, the source electrode of second PMOS transistor are connected with supply voltage respectively, the 2nd PMOS crystal
The grid of pipe is connected with the output end of the timer, by changing the equivalent resistance of the resitstance voltage divider, makes the triggering
Device adjusts trigger voltage.
Wherein more preferably, the trigger is made up of MOSFET divider and diode；The MOSFET divider are by
Bi-NMOS transistor, the second PMOS transistor composition, the grid of second PMOS transistor and the output end of the timer
Connection, the source electrode of second PMOS transistor is connected with supply voltage, the drain electrode of second PMOS transistor respectively with institute
Anode, the grid of second nmos pass transistor and the drain electrode for stating diode are connected and intersect at same node, and described second
The source ground of nmos pass transistor, the negative electrode of the diode another input, described first respectively with the latch
One end connection of resistance, by changing the size of second nmos pass transistor, second PMOS transistor, makes the triggering
Device adjusts trigger voltage.
Wherein more preferably, the trigger is used to distinguish the due to voltage spikes during esd event and normal power supply, when just
When often during power supply, the power clamp electrostatic discharge circuit is closed；Exceed threshold voltage when there is esd event and trigger voltage
When, open the power clamp electrostatic discharge circuit；
The diode is used to isolate the trigger when the latch is transitioned into opening, plays uncoupling
Effect.
Wherein more preferably, the latch is by the 3rd nmos pass transistor, the 3rd PMOS transistor and the second phase inverter group
Into；The grid of the 3rd PMOS transistor is connected with the output end of first phase inverter, the 3rd PMOS transistor
Drain electrode is connected with the drain electrode of the 3rd nmos pass transistor, the grid of the 3rd nmos pass transistor respectively with the trigger
One end connection of the negative electrode of diode, the first resistor, the input of second phase inverter and the 3rd PMOS crystal
The source electrode connection of pipe, the output end of second phase inverter connects with the other end of the bleeder circuit, the first resistor respectively
Connect, the source electrode of the 3rd PMOS transistor is connected with supply voltage, the source ground of the 3rd nmos pass transistor；
The latch is used to export ESD trigger signals, bleeder circuit is provided electricity when receiving the ESD trigger signals
Low impedance path between source and ground, with static electricity discharge electric current, and the feedback mechanism extension vent discharge for passing through the latch
The opening time on road, realization protects internal circuit not damaged by static discharge.
Wherein more preferably, second phase inverter is as both the 4th nmos pass transistor and the 4th PMOS transistor complementary type
Composition；The grid of the 4th nmos pass transistor is joined together to form described with the grid of the 4th PMOS transistor M8
The input of two phase inverters, the input is connected with supply voltage, the drain electrode and the described 4th of the 4th PMOS transistor
The drain electrode of nmos pass transistor is joined together to form the output end of second phase inverter, the source electrode of the 4th nmos pass transistor
Ground connection.
Wherein more preferably, the leadage circuit uses Darlington transistor, and the Darlington transistor is by least two NPN transistors
Composition, the emitter stage of the first NPN transistor is directly coupled to the base stage of the second NPN transistor, the first NPN type crystal
Pipe is connected supply voltage respectively with the colelctor electrode of second NPN transistor, and the emitter stage of second NPN transistor connects
Ground, the base stage of first NPN transistor output end respectively with the second phase inverter, the other end of the first resistor connect
Connect.
Wherein more preferably, the input of first phase inverter is connected with the output end of the timer, for realizing putting
The ESD trigger signals of the big timer output；The output end of first phase inverter is brilliant with the 3rd PMOS of the latch
The grid connection of body pipe, is embodied as the latch and provides driving force, drives the latch to complete feedback and regenerative process.
Wherein more preferably, first phase inverter is as the first PMOS transistor and both the first nmos pass transistors complementary type
Composition, the grid of first PMOS transistor is joined together to form described first with the grid of first nmos pass transistor
The input of phase inverter, the source electrode of first PMOS transistor is connected with supply voltage, the leakage of first PMOS transistor
Pole is joined together to form the output end of first phase inverter, a NMOS with the drain electrode of first nmos pass transistor
The source ground of transistor.
Second aspect according to embodiments of the present invention, there is provided a kind of IC chip, which includes above-mentioned adjustable tactile
The power clamp electrostatic discharge circuit of the pressure that generates electricity.
The third aspect according to embodiments of the present invention, there is provided a kind of communication terminal, which includes above-mentioned adjustable triggering electricity
The power clamp electrostatic discharge circuit of pressure.
The power clamp electrostatic discharge circuit of tunable trigger voltage provided by the present invention, is on the one hand detected by timer
Whether there is esd event, and trigger voltage is adjusted by trigger, make this power clamp electrostatic discharge circuit that there is different touching
Generate electricity pressure, meanwhile, drive bleeder circuit to complete quick leakage current to realize comprehensively protection circuit element by latch.Separately
On the one hand, the due to voltage spikes during esd event and normal power supply can be distinguished by this power clamp electrostatic discharge circuit,
When during normal power supply, this power clamp electrostatic discharge circuit can be closed, only exceed threshold value there is esd event and voltage
During voltage, this power clamp electrostatic discharge circuit can just be unlocked, and improve the reliability of trigger mechanism.
Brief description of the drawings
Fig. 1 is the operation principle block diagram of the power clamp electrostatic discharge circuit of tunable trigger voltage provided by the present invention；
Fig. 2 is that the first embodiment of the power clamp electrostatic discharge circuit of tunable trigger voltage provided by the present invention is illustrated
Figure；
Fig. 3 is that the second embodiment of the power clamp electrostatic discharge circuit of tunable trigger voltage provided by the present invention is illustrated
Figure.
Specific embodiment
Technology contents of the invention are described in further detail with specific embodiment below in conjunction with the accompanying drawings.
As shown in figure 1, the power clamp electrostatic discharge circuit of tunable trigger voltage provided by the present invention includes timer
1st, trigger 3, latch 4, bleeder circuit 5.Wherein, the output end of timer 1 is connected with the input of trigger 3, meanwhile,
Be additionally provided with the first phase inverter 2 between the output end of timer 1 and an input of latch 4, the output end of trigger 3 with
Another input connection of latch 4, the output end of latch 4 is connected with bleeder circuit 5.One end difference of first resistor R1
Another input of output end, latch 4 with trigger 3 is connected, the other end of first resistor R1 respectively with latch 4
Output end, leadage circuit connection.This power clamp electrostatic discharge circuit has adjustable trigger voltage, can be used for mixing more
The esd event protection of bipolar device and cmos device in signal integrated circuit design.Meanwhile, this power clamp static discharge
Circuit can also distinguish between the due to voltage spikes of power supply and esd event, improve the reliability of trigger mechanism.
In power clamp electrostatic discharge circuit provided by the present invention, timer 1 can use RC clock circuits, the RC
Clock circuit is in series by a resistance R and an electric capacity C, wherein can connect one end of resistance R and supply voltage VDD
Connect, the other end of resistance R is connected with the top crown of electric capacity C, the bottom crown ground connection of electric capacity C, and resistance R and electric capacity C is with node A
As output end.Electric capacity C can be PIP (polycrystalline electric capacity) electric capacity, or MIM (metal capacitance) electric capacity.Timer 1 is used for
Detection differentiation is esd pulse or normal power supply electrifying pulse.When power supply normally goes up electricity, now timer 1 will ensure this
Power clamp electrostatic discharge circuit is not turned on；When an esd event occurs, timer 1 will can quickly detect esd pulse letter
Number, and guide and open the working condition of the power clamp electrostatic discharge circuit, so that static electricity discharge electric current, protects chip internal
Circuit.
As shown in Figures 2 and 3, the first phase inverter 2 can be by the first PMOS transistor M2 and the first nmos pass transistor M1 bis-
Person's complementary type is constituted.Wherein, the grid of the first PMOS transistor M2 links together with the grid of the first nmos pass transistor M1
The input of the first phase inverter 2 is formed, the source electrode of the first PMOS transistor M2 is connected with supply voltage VDD, a PMOS crystal
The drain electrode of pipe M2 is joined together to form the output end of the first phase inverter 2, a NMOS with the drain electrode of the first nmos pass transistor M1
The source ground of transistor M1.It is connected with the input of the first phase inverter 2 by by the output end of timer 1, it is possible to achieve put
The ESD trigger signals of the output of big timer 1；Connect by by an input of the output end of the first phase inverter 2 and latch 4
Connect, driving force can be provided for latch 4, so as to drive latch 4 to complete feedback and regenerative process.
In power clamp electrostatic discharge circuit provided by the present invention, first embodiment shown in Figure 2, trigger
3 can be made up of resitstance voltage divider, the second nmos pass transistor M3, the second PMOS transistor M4 and diode D.Wherein, resistance
Divider is made up of second resistance R2 with 3rd resistor R3, and one end of second resistance R2 is connected with one end of 3rd resistor R3, and
And this one end for being connected with 3rd resistor R3 of second resistance R2 drain electrode, diode D also respectively with the second nmos pass transistor M3
Anode connect and intersect at same node, using the negative electrode of diode D as the output end of trigger 3, the output end with latch
One end connection of another input and first resistor R1 of device 4.The other end of second resistance R2 and the second PMOS transistor
The source electrode of the drain electrode connection of M4, the other end of 3rd resistor R3 and the second nmos pass transistor M3 is grounded respectively, and the 2nd NMOS is brilliant
The source electrode of the grid of body pipe M3 and the second PMOS transistor M4 is connected with supply voltage VDD respectively, the second PMOS transistor M4
Grid be connected with the output end of timer 1 as the input of trigger 3.Trigger 3 can be dropped using above-mentioned parallel organization
Low trigger voltage is to technique change and the sensitiveness of operation temperature.Supply voltage VDD is reached when the electric capacity C in timer 1 charges
When, state is off by the second PMOS transistor M4 of the control trigger 3 of timer 1, so as to reduce trigger 3 just
Leakage current during often working.Also, by changing the equivalent resistance of resitstance voltage divider, trigger 3 can be made in electricity very wide
Trigger voltage is adjusted in the range of pressure.
Second embodiment shown in Figure 3, trigger 3 can also be made up of MOSFET divider with diode D.
MOSFET divider are made up of the second nmos pass transistor M3, the second PMOS transistor M4, wherein, the grid of the second PMOS transistor M4
Pole is connected with the output end of timer 1, and the source electrode of the second PMOS transistor M4 is connected with supply voltage VDD, the 2nd PMOS crystal
The drain electrode anode respectively with diode D of pipe M4, the grid of the second nmos pass transistor M3 and drain electrode are connected and intersect at same section
Point, now, the grid of the second nmos pass transistor M3 and drain electrode are in short circuit state；The source ground of the second nmos pass transistor M3,
The same negative electrode using diode D as trigger 3 output end, the output end respectively with another input of latch 4 with
And one end connection of first resistor R1.By changing the size of the second nmos pass transistor M3, the second PMOS transistor M4, can make
Trigger 3 adjusts trigger voltage in voltage range very wide.
So, the due to voltage spikes during esd event and normal power supply can be distinguished by trigger 3, in normal power supply
Period, this power clamp electrostatic discharge circuit can be closed, only exceed threshold voltage there is esd event and trigger voltage
When, this power clamp electrostatic discharge circuit can just be unlocked, and improve the reliability of trigger mechanism.
As shown in Figures 2 and 3, in power clamp electrostatic discharge circuit provided by the present invention, latch 4 is by the 3rd
Nmos pass transistor M5, the 3rd PMOS transistor M6, resistance RL and the second phase inverter composition.Wherein, resistance RL, the 3rd PMOS are brilliant
Body pipe M6, the 3rd nmos pass transistor M5 are sequentially connected in series, and resistance RL connects power supply.The grid of the 3rd PMOS transistor M6 is used as latch
4 input is connected with the output end of the first phase inverter 2, drain electrode and the 3rd nmos pass transistor of the 3rd PMOS transistor M6
The drain electrode connection of M5, the grid of the 3rd nmos pass transistor M5 is as another input of latch 4 respectively with the two of trigger 3
One end connection of the negative electrode, first resistor R1 of pole pipe D.The node that 3rd PMOS transistor M6 is connected with resistance RL is used as intersecting coupling
The output end of NAND gate is closed, the input of the second phase inverter is connected to.Second phase inverter is by the 4th nmos pass transistor M7 and the 4th
Both PMOS transistor M8 complementary types are constituted.The grid of the 4th nmos pass transistor M7 and the grid of the 4th PMOS transistor M8 connect
It is connected together to form the input of the second phase inverter, the source electrode of the input of the second phase inverter and the 3rd PMOS transistor M6 connects
Connect；The drain electrode of the 4th PMOS transistor M8 is joined together to form the defeated of the second phase inverter with the drain electrode of the 4th nmos pass transistor M7
Go out end, the other end of the output end of the second phase inverter respectively with bleeder circuit 5, first resistor R1 is connected, from there through resistance R1
It is connected to the input (i.e. the grid of the 3rd nmos pass transistor M5) of cross-couplings NAND gate.The source of the 3rd PMOS transistor M6
Pole, the grid of the 4th nmos pass transistor M7, the grid of the 4th PMOS transistor M8 and source electrode are connected with supply voltage VDD respectively,
The source electrode of the 3rd nmos pass transistor M5, the source electrode of the 4th nmos pass transistor M7 are grounded respectively.Wherein, the effect of first resistor R1
It is：When the state of the latch 4 that changes of esd event, the conducting resistance of the 4th nmos pass transistor M7 will not constitute triggering
The ohmic load of device 3, and the presence of first resistor R1 does not interfere with the feedback and regenerative process of latch 4 yet.When latch 4
When being transitioned into opening, can realize being isolated latch 4 with trigger 3 by the diode D of trigger 3, quite
In the effect of uncoupling, effectively prevent due to the load effect of 3rd resistor R3 and the second nmos pass transistor M3, make the 3rd
The grid voltage of nmos pass transistor M5 is clamped at relatively low numerical value, so as to latch 4 cannot be opened.Exported by latch 4
ESD trigger signals, can be used for driving bleeder circuit 5 carries out static electricity discharge electric current, and extends vent discharge by its feedback mechanism
The opening time on road, so as to realize protecting internal circuit not damaged by static discharge.
Leadage circuit can use Darlington transistor, and wherein Darlington transistor can be using composite joint mode, can be by least
The colelctor electrode of two NPN transistors links together.As shown in FIG. 1 to 3, with Darlington transistor by two NPN transistors
It is described as a example by composition, the emitter stage of the first NPN transistor Q1 is directly coupled to the base of the second NPN transistor Q2
Pole, the first NPN transistor Q1 is connected supply voltage VDD, the second NPN type respectively with the colelctor electrode of the second NPN transistor Q2
The grounded emitter of transistor Q2, the base stage of the first NPN transistor Q1 respectively with the output end of the second phase inverter and first
The other end connection of resistance R1.The ESD trigger signals that latch 4 is exported are received by leadage circuit, to provide power supply with ground
Between low impedance path, realize static electricity discharge electric current.
Below by taking the power clamp electrostatic discharge circuit shown in Fig. 2 as an example, the course of work of the invention is carried out specifically
It is bright.
When an esd event occurs, supply voltage VDD is raised, now the rise time of the time constant of timer 1 and ESD
Compare, time constant is very big, so the charging voltage of electric capacity is still close to zero.The relatively low charging voltage of electric capacity causes a PMOS
Transistor M2, the second PMOS transistor M4, the 3rd PMOS transistor M6 are unlocked.Due to the second nmos pass transistor M3 grid with
Supply voltage VDD is connected, so the second nmos pass transistor M3 is always held at opening, so as to reduce in 3rd resistor R3
The voltage difference VR3 at the voltage difference VR3 at two ends, 3rd resistor R3 two ends can be expressed as：
Now, the voltage Vgs5 between the grid and source electrode of the 3rd nmos pass transistor M5 can be expressed as：
Vgs5=VR3-VD (2)
Wherein, VD is the forward conduction voltage drop of diode D.
When the gate source voltage Vgs5 of the 3rd nmos pass transistor M5 reaches threshold voltage, the regeneration of latch 4 will be opened
Journey, base current can be provided by the 4th PMOS transistor M8 for the Darlington transistor of bleeder circuit 5, to provide power supply with ground
Between low impedance path, realize static electricity discharge electric current.Simultaneously under the feedback effect of latch 4, this power clamp electrostatic can be made
Discharge circuit can hold about the opening time of two microseconds, with the rising of the charging voltage of the electric capacity C of latch 4, can be with
The 3rd PMOS transistor M6 of shut-off is realized, so that latch 4 is closed.
After upper electricity, supply voltage VDD gradually stablizes, and now, the electric capacity C in timer 1 charges and reaches supply voltage VDD,
State is off by the second PMOS transistor M4 of the control trigger 3 of timer 1, becomes the leakage current in trigger 3
Obtain very small.During power amplifier normal work, even when due to voltage spikes is produced in the case of envelope-tracking, due to
The effect of parasitic capacitance of CMOS transistor and bipolar device, the leakage current of trigger 3 is again smaller than total displacement current.
Because the threshold voltage for turning on the 3rd nmos pass transistor M5 keeps constant, so in the forward conduction of diode D
In the case that pressure drop VD keeps constant, the voltage difference VR3 at 3rd resistor R3 two ends also keeps invariable.When second resistance R2's
When resistance changes, the supply voltage VDD for triggering this power clamp electrostatic discharge circuit can change therewith, so as to reach
Adjust the purpose of trigger voltage.For example, the resistance of the second resistance R2 of resitstance voltage divider, 3rd resistor R3 is respectively set as into 5k
Ω and 3k Ω, trigger voltage is respectively 5.8V and 6.4V at 25 DEG C and 110 DEG C, and trigger current reaches 1.2A.
When this power clamp electrostatic discharge circuit uses the circuit structure shown in Fig. 3, by changing the 2nd NMOS crystal
The size of pipe M3, the second PMOS transistor M4, can make trigger adjust trigger voltage in voltage range very wide, the process
It is similar with said process, will not be repeated here.For example, the grid L long of the second PMOS transistor M4 of MOSFET divider is taken into 3 μ
M, grid width W take 2 μm, and the grid L long of the second nmos pass transistor M3 takes 0.7 μm, and grid width W takes 1 μm, and trigger voltage is at 25 DEG C to 110 DEG C
In the range of be basically unchanged and be maintained at 5.9V.
Power clamp electrostatic discharge circuit provided by the present invention, on the one hand detects whether ESD things by timer
Part, and trigger voltage is adjusted by trigger, make this power clamp electrostatic discharge circuit that there are different trigger voltages, meanwhile,
Bleeder circuit is driven to complete quick leakage current to realize comprehensively protection circuit element by latch.On the other hand, pass through
This power clamp electrostatic discharge circuit can distinguish the due to voltage spikes during esd event and normal power supply, in the normal power supply phase
Between, this power clamp electrostatic discharge circuit can be closed, only when there is esd event and voltage exceedes threshold voltage, this electricity
Source clamper electrostatic discharge circuit can just be unlocked, and improve the reliability of trigger mechanism.
The power clamp electrostatic discharge circuit of tunable trigger voltage provided by the present invention can be used in ic core
In piece (such as radio frequency front end chip).For the concrete structure of the power clamp electrostatic discharge circuit in the radio frequency front end chip,
Just no longer detail one by one herein.
In addition, during above-mentioned power clamp electrostatic discharge circuit can be used on communication terminal, as the weight of radio circuit
Want part.Communication terminal mentioned here refers to that can be used in mobile environment, support GSM, EDGE, TD_SCDMA,
The computer equipment of various communication standards such as TDD_LTE, FDD_LTE, including mobile phone, notebook computer, panel computer, car
Carry computer etc..Additionally, technical scheme provided by the present invention is also applied for the occasion of other radio circuit applications, for example communicate base
Stand.
Power clamp electrostatic discharge circuit above to tunable trigger voltage provided by the present invention, chip and communication terminal
It has been described in detail.It is right on the premise of without departing substantially from true spirit for those of ordinary skill in the art
Any obvious change that it is done, will all belong to the protection domain of patent right of the present invention.
Claims (12)
1. the power clamp electrostatic discharge circuit of a kind of tunable trigger voltage, it is characterised in that including timer, trigger, latch
Device, bleeder circuit；
The output end of the timer is connected with the input of the trigger, the output end of the timer and the latch
An input between be provided with the first phase inverter, another input of the output end of the trigger and the latch
Connection, the output end of the latch is connected with the bleeder circuit；
One end of first resistor output end respectively with the trigger, another input of the latch are connected, another
End output end respectively with the latch, the leadage circuit are connected.
2. power clamp electrostatic discharge circuit as claimed in claim 1, it is characterised in that：
The timer is realized using RC clock circuits, for detecting that differentiation is electrostatic discharge pulses or normal power supply electrifying
Pulse, and the power clamp electrostatic discharge circuit is turned on and off according to testing result.
3. power clamp electrostatic discharge circuit as claimed in claim 1, it is characterised in that：
The trigger is made up of resitstance voltage divider, the second nmos pass transistor, the second PMOS transistor and diode；The electricity
Resistance divider is made up of second resistance with 3rd resistor, and one end of the second resistance is connected with one end of the 3rd resistor,
This one end that the second resistance is connected with 3rd resistor drain electrode, described two respectively with second nmos pass transistor
The anode of pole pipe is connected and intersects at same node, another input of the negative electrode of the diode and the latch and
One end connection of the first resistor, the other end of the second resistance is connected with the drain electrode of second PMOS transistor, institute
The other end of 3rd resistor, the source electrode of second nmos pass transistor is stated to be grounded respectively, the grid of second nmos pass transistor,
The source electrode of second PMOS transistor is connected with supply voltage respectively, grid and the timing of second PMOS transistor
The output end connection of device, by changing the equivalent resistance of the resitstance voltage divider, makes the trigger regulation trigger voltage.
4. power clamp electrostatic discharge circuit as claimed in claim 1, it is characterised in that：
The trigger is made up of MOSFET divider and diode；The MOSFET divider are by the second nmos pass transistor,
Two PMOS transistors are constituted, and the grid of second PMOS transistor is connected with the output end of the timer, and described second
The source electrode of PMOS transistor is connected with supply voltage, second PMOS transistor drain electrode respectively with the sun of the diode
Pole, the grid of second nmos pass transistor and drain electrode are connected and intersect at same node, the source of second nmos pass transistor
Pole is grounded, and the negative electrode of the diode another input respectively with the latch, one end of the first resistor are connected,
By changing the size of second nmos pass transistor, second PMOS transistor, make the trigger regulation trigger voltage.
5. the power clamp electrostatic discharge circuit as described in claim 3 or 4, it is characterised in that：
The trigger is for the due to voltage spikes during distinguishing electrostatic discharge event and normal power supply；When during normal power supply
When, close the power clamp electrostatic discharge circuit；When there is electrostatic discharge event and trigger voltage exceedes threshold voltage, open
Open the power clamp electrostatic discharge circuit.
6. power clamp electrostatic discharge circuit as claimed in claim 1, it is characterised in that：
The latch is made up of the 3rd nmos pass transistor, the 3rd PMOS transistor and the second phase inverter；3rd PMOS
The grid of transistor is connected with the output end of first phase inverter, the drain electrode and the described 3rd of the 3rd PMOS transistor
The drain electrode connection of nmos pass transistor, the grid of the 3rd nmos pass transistor negative electrode respectively with the diode of the trigger,
One end connection of the first resistor, the input of second phase inverter is connected with the source electrode of the 3rd PMOS transistor,
The other end of the output end of second phase inverter respectively with the bleeder circuit, the first resistor is connected, and the described 3rd
The source electrode of PMOS transistor is connected with supply voltage, the source ground of the 3rd nmos pass transistor.
7. power clamp electrostatic discharge circuit as claimed in claim 6, it is characterised in that：
Second phase inverter is made up of the 4th nmos pass transistor with both the 4th PMOS transistors complementary type；Described 4th
The grid of nmos pass transistor is joined together to form the defeated of second phase inverter with the grid of the 4th PMOS transistor M8
Enter end, the input is connected with supply voltage, drain electrode and the 4th nmos pass transistor of the 4th PMOS transistor
Drain electrode is joined together to form the output end of second phase inverter, the source ground of the 4th nmos pass transistor.
8. power clamp electrostatic discharge circuit as claimed in claim 1, it is characterised in that：
The leadage circuit uses Darlington transistor, the Darlington transistor to be made up of at least two NPN transistors, the first NPN type
The emitter stage of transistor is directly coupled to the base stage of the second NPN transistor, first NPN transistor and described second
The colelctor electrode of NPN transistor connects supply voltage, the grounded emitter of second NPN transistor, described first respectively
The base stage of NPN transistor output end respectively with the second phase inverter, the other end of the first resistor are connected.
9. power clamp electrostatic discharge circuit as claimed in claim 1, it is characterised in that：
The input of first phase inverter is connected with the output end of the timer, for amplifying the quiet of the timer output
Discharge of electricity trigger signal；The output end of first phase inverter is connected with the grid of the 3rd PMOS transistor of the latch,
For the latch provides driving force, the latch is driven to complete feedback and regenerative process.
10. power clamp electrostatic discharge circuit as claimed in claim 9, it is characterised in that：
First phase inverter is made up of the first PMOS transistor with both the first nmos pass transistors complementary type, and described first
The grid of PMOS transistor is joined together to form the input of first phase inverter with the grid of first nmos pass transistor
End, the source electrode of first PMOS transistor is connected with supply voltage, the drain electrode of first PMOS transistor and described first
The drain electrode of nmos pass transistor is joined together to form the output end of first phase inverter, the source electrode of first nmos pass transistor
Ground connection.
11. a kind of IC chips, it is characterised in that included in the IC chip any in claim 1~10
Power clamp electrostatic discharge circuit described in one.
12. a kind of communication terminals, it is characterised in that included in the communication terminal in claim 1~10 described in any one
Power clamp electrostatic discharge circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710214456.1A CN106877303A (en) | 2017-04-01 | 2017-04-01 | The power clamp electrostatic discharge circuit of tunable trigger voltage, chip and communication terminal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710214456.1A CN106877303A (en) | 2017-04-01 | 2017-04-01 | The power clamp electrostatic discharge circuit of tunable trigger voltage, chip and communication terminal |
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| CN106877303A true CN106877303A (en) | 2017-06-20 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201710214456.1A Withdrawn CN106877303A (en) | 2017-04-01 | 2017-04-01 | The power clamp electrostatic discharge circuit of tunable trigger voltage, chip and communication terminal |
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| CN109872991A (en) * | 2017-12-05 | 2019-06-11 | 三星电子株式会社 | ESD protection circuit and integrated circuit including it |
| CN112186726A (en) * | 2020-11-30 | 2021-01-05 | 珠海市杰理科技股份有限公司 | ESD protection circuit, power supply and chip |
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| CN116345424A (en) * | 2023-05-31 | 2023-06-27 | 深圳市锦锐科技股份有限公司 | Strengthen singlechip ESD high anti-interference circuit |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109872991A (en) * | 2017-12-05 | 2019-06-11 | 三星电子株式会社 | ESD protection circuit and integrated circuit including it |
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| CN113629052A (en) * | 2021-10-12 | 2021-11-09 | 微龛(广州)半导体有限公司 | ESD protection structure with adjustable trigger voltage and preparation method thereof |
| CN116345424A (en) * | 2023-05-31 | 2023-06-27 | 深圳市锦锐科技股份有限公司 | Strengthen singlechip ESD high anti-interference circuit |
| CN116345424B (en) * | 2023-05-31 | 2023-08-04 | 深圳市锦锐科技股份有限公司 | Strengthen singlechip ESD high anti-interference circuit |
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Application publication date: 20170620 |