CN112186097B - Structure for optimizing writing performance of magnetic random access memory and preparation method thereof - Google Patents
Structure for optimizing writing performance of magnetic random access memory and preparation method thereof Download PDFInfo
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Abstract
The invention discloses a structure for optimizing writing performance of a magnetic random access memory, which comprises a writing accelerator, wherein the writing accelerator is positioned at the lower side of a bottom electrode of the magnetic random access memory and the upper side of a bottom electrode through hole, and the writing accelerator is directly connected with the bottom electrode and the bottom electrode through hole. The invention also discloses a preparation method of the structure for optimizing the writing performance of the magnetic random access memory, which comprises the following steps: step one: providing a surface-polished CMOS substrate with metal connection lines Mx; step two: manufacturing a bottom electrode through hole on the CMOS substrate after planarization treatment and grinding the bottom electrode through hole; step three: patterning, defining and etching a write accelerator metal on the bottom electrode through hole, filling a write accelerator dielectric medium, and flattening the write accelerator dielectric medium by adopting chemical mechanical planarization; step four: and sequentially depositing a bottom electrode, a magnetic tunnel junction multilayer film and a top electrode on the write accelerator, manufacturing a magnetic tunnel junction memory cell, and finally manufacturing bit line connection on the top electrode.
Description
Technical Field
The invention relates to the technical field of magnetic random access memories (Magnetic Random Access Memory, MRAM), in particular to a structure for optimizing the writing performance of the Magnetic Random Access Memories (MRAM) and a preparation method thereof.
Background
In recent years, MRAM using magnetic tunnel junctions (Magnetic Tunnel Junction, MTJ) is considered as a future solid-state nonvolatile memory, which has the characteristics of high-speed reading and writing, high capacity and low power consumption, and ferromagnetic MTJ is generally a sandwich structure, in which there is a Free Layer (FL) that can change the magnetization direction to record different data; an insulating tunnel Barrier Layer (BL) located in the middle; the magnetic Reference Layer (RL) is located at the other side of the tunnel barrier Layer, and its magnetization direction is unchanged, specifically, it may be a Bottom Pinned (Bottom Pinned) structure formed by sequentially stacking the Reference Layer (RL), the Barrier Layer (BL) and the Free Layer (FL) or a top Pinned (TopPinned) structure formed by sequentially stacking the Free Layer (FL), the Barrier Layer (BL) and the Reference Layer (RL), and the Bottom Pinned structure is popular.
In order to be able to record information in such magnetoresistive elements, it is proposed to use a writing method based on spin momentum transfer or spin transfer torque (Spin Transfer Torque, STT) switching technology, such MRAM being called STT-MRAM, which is in turn divided into in-plane STT-MRAM and perpendicular STT-MRAM, depending on the direction of the magnetic polarization, the latter having better properties, in a Magnetic Tunnel Junction (MTJ) with perpendicular anisotropy (PMA) as free layer for storing information, having two magnetization directions in perpendicular direction, namely: up and down, in practical applications, the direction of the free layer magnetization vector remains unchanged when reading information or being empty; during writing, if a signal is input from a state different from the existing state, the direction of the magnetization vector of the free layer will be turned 180 degrees in the vertical direction, and the ability of the free layer of the magnetic Memory to keep the magnetization vector unchanged in the empty state is called Data Retention (Data Retention) or thermal stability (Thermal Stability), which are different in different application scenarios, and the thermal stability requirement for a typical nonvolatile Memory (NVM) is that the Data can be stored for 10 years at 125 ℃.
Further, the Data Retention (Data Retention) can be calculated using the following formula:
wherein τ is the time when the magnetization vector is unchanged under the thermal disturbance condition 0 For the time of attempt, E is the energy barrier of the free layer, k B Is the boltzmann constant, and T is the operating temperature.
The thermal stability factor (Thermal Stability Factor) can then be expressed as follows:
wherein K is eff Is the effective energy density of the free layer in each direction, V is the volume of the free layer, K V Is the bulk anisotropy constant, M s Is the saturation magnetic susceptibility of the free layer, N z Demagnetizing constant in vertical direction, t is thickness of free layer, K i CD is the critical dimension (Critical Dimension, CD) of a Magnetic Random Access Memory (MRAM) and As is the stiffness integral exchange constant.
Further, λ is the critical dimension of the transition of the magnetization vector switching mode of the free layer from the domain switching mode to the reverse domain nucleation/expansion mode, and experiments show that the free layer exhibits in-plane anisotropy when the free layer is thicker and perpendicular anisotropy when the free layer is thinner, K V Is generally negligible, whereas the contribution of the demagnetizing energy to the perpendicular anisotropy is negative, so that the perpendicular anisotropy comes entirely from the interface effect (K i )。
Further, empirical data for Magnetic Tunnel Junctions (MTJs) with perpendicular anisotropy (Perpendicular Magnetic Anisotropy, PMA) indicate that the critical dimensions of domain inversion (I) and reverse domain nucleation/expansion (II) are 40nm to 70nm.
In addition, as the volume of the magnetic free layer is reduced, the spin-polarized current to be injected in the writing or switching operation is also smaller, and the critical current I of the writing operation is in the conventional PSTT-MRAM c0 And the relationship with the thermal stability is strong, and can be expressed as the following formula:
wherein alpha is a damping coefficient,is about the Planck constant, η is spin polarizability.
As mentioned above, STT-based spin transfer torque is the dominant writing method of current MRAM, however, it also has a difficult speed and barrier reliability bottleneck, the magnitude of spin transfer torque is positively correlated with the magnetization vectors of the Free Layer (FL) and the Reference Layer (RL), before writing, the magnetization directions of the two ferromagnetic layers are almost collinear (parallel or antiparallel), a small included angle is mainly induced by thermal fluctuation, so at the initial stage of writing, the spin transfer torque is relatively weak, the included angle of the two magnetization vectors is gradually increased as the magnetization inversion process proceeds, the spin transfer torque is enhanced, at the initial stage, the weak spin transfer torque causes an initial Delay (intubation Delay), the writing speed is limited, the initial Delay can be reduced by increasing the write current, but the probability of barrier breakdown is also increased, and the existence of the initial Delay makes the STT-MRAM still difficult to meet the performance requirements of the cache (such as: SRAM).
In addition, MTJ, which is the core memory cell of a magnetic memory (MRAM), must also be compatible with CMOS processes and must be able to withstand long-term anneals at 400 ℃.
Disclosure of Invention
The present invention addresses the problems and deficiencies of the prior art by providing a structure for optimizing the write performance of a Magnetic Random Access Memory (MRAM) and a method of making the same.
The invention solves the technical problems by the following technical proposal:
the invention provides a structure for optimizing writing performance of a magnetic random access memory, which comprises a writing accelerator, wherein the writing accelerator is positioned at the lower side of a bottom electrode of the magnetic random access memory and the upper side of a bottom electrode through hole, and the writing accelerator is directly connected with the bottom electrode and the bottom electrode through hole.
The invention also provides a preparation method of the structure for optimizing the writing performance of the magnetic random access memory, which comprises the following steps:
step one: providing a surface polished CMOS substrate with a metal connecting line Mx, wherein x is more than or equal to 1;
step two: manufacturing a bottom electrode through hole on the CMOS substrate after planarization treatment and grinding the bottom electrode through hole;
step three: patterning, defining and etching a write accelerator metal on the bottom electrode through hole, filling a write accelerator dielectric medium, and flattening the write accelerator dielectric medium by adopting chemical mechanical planarization;
step four: and sequentially depositing a bottom electrode, a magnetic tunnel junction multilayer film and a top electrode on the write accelerator, manufacturing a magnetic tunnel junction memory cell, and finally manufacturing bit line connection on the top electrode.
On the basis of conforming to the common knowledge in the field, the above preferred conditions can be arbitrarily combined to obtain the preferred examples of the invention.
The invention has the positive progress effects that:
in MRAM circuits, when performing a write operation, the Free Layer (FL) region directly above the Write Accelerator (WA) preferentially forms inverted domains that facilitate magnetization switching, which rapidly nucleate, expand, and complete magnetization switching. The magnetization vector is greatly improved from parallel to antiparallel or antiparallel to parallel switching speed due to the introduction of the Write Accelerator (WA), namely: the task of writing a '0' or a '1' can be realized in the MRAM memory cell more quickly, and the requirement of a cache (such as SRAM) can be met. Meanwhile, since the time taken to write data is shorter, the power consumption of the device is also lower.
The structure for optimizing the writing performance of the Magnetic Random Access Memory (MRAM) and the preparation method thereof are particularly suitable for a Magnetic Tunnel Junction (MTJ) process (corresponding to a CMOS process node of 20nm or more) with the size of more than 40nm, reduce the power consumption, improve the reading and writing speed and can be used as a substitute scheme of a high-speed cache.
Drawings
Fig. 1: the invention provides a structure for optimizing the writing performance of a magnetic random access memory, which is characterized in that a magnetization vector overturning schematic diagram in the writing process.
Fig. 2: the invention provides a preparation method of a structure for optimizing writing performance of a magnetic random access memory, and provides a schematic diagram of a substrate with a metal connecting line Mx (x is more than or equal to 1) with a polished surface.
Fig. 3: the invention provides a preparation method of a structure for optimizing the writing performance of a magnetic random access memory, which is used for manufacturing a schematic diagram after a bottom electrode through hole (BEV).
Fig. 4: in the method for preparing the structure for optimizing the write performance of the magnetic random access memory, in a preferred embodiment, a schematic diagram after a Write Accelerator (WA) is manufactured.
Fig. 5: in the method for preparing the structure for optimizing the write performance of the magnetic random access memory, in other preferred embodiments, a Write Accelerator (WA) is schematically shown.
Fig. 6: in the preparation method of the structure for optimizing the write performance of the magnetic random access memory, in a preferred embodiment, the Bottom Electrode (BE), the Magnetic Tunnel Junction (MTJ), the Top Electrode (TE) and the bit line connection (BL) are schematic diagrams after the preparation is completed.
The figure shows: 31-Write Accelerator (WA), 42 a-reference layer, 42 b-barrier layer, 42 c-free layer, 100-surface polished substrate with CMOS metal interconnect Mx (x.gtoreq.1), 110-metal interconnect Mx (x.gtoreq.1) interlayer dielectric, 120-metal interconnect Mx (x.gtoreq.1), 210-Bottom Electrode Via (BEV) etch barrier layer, 220-Bottom Electrode Via (BEV) interlayer dielectric, 230-Bottom Electrode Via (BEV), 310-Write Accelerator (WA) metal, 320-Write Accelerator (WA) dielectric, 410-Bottom Electrode (BE), 420-Magnetic Tunnel Junction (MTJ), 430-Top Electrode (TE), 440-insulating cap layer, 450-Magnetic Tunnel Junction (MTJ) interlayer dielectric, 510-bit line connection (BL) interlayer dielectric and 520-bit line connection.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
A structure for optimizing Magnetic Random Access Memory (MRAM) write performance, comprising: -a write accelerator (Write Accelerator, WA) located on the underside of the Bottom Electrode (BE) of the Magnetic Random Access Memory (MRAM), on the upper side of the Bottom Electrode via (Bottom Electrode Via, BEV), i.e. between and directly connected to the Bottom Electrode (BE) and the Bottom Electrode Via (BEV).
Further, the Write Accelerator (WA) is generally much smaller in size than the Bottom Electrode (BE) and the Bottom Electrode Via (BEV), and may BE of any shape, while its position relative to the Bottom Electrode (BE) and the Bottom Electrode Via (BEV) is adjustable.
In MRAM circuits, when performing a write operation, the Free Layer (FL) region directly above the Write Accelerator (WA) preferentially forms inverted domains that facilitate magnetization switching, which rapidly nucleate, expand, and complete magnetization switching.
The magnetization vector is greatly improved from parallel to antiparallel or antiparallel to parallel switching speed due to the introduction of the Write Accelerator (WA), namely: the task of writing a '0' or a '1' can be realized in the MRAM memory cell more quickly, and the requirement of a cache (such as SRAM) can be met.
Meanwhile, since the time taken to write data is shorter, the power consumption of the device is also lower.
Further, due to the relatively small size of the Write Accelerator (WA), better local surface Roughness (RMS) can be obtained in the planarization process, in which case a better quality barrier layer (Tunnel Barrier Layer) can be obtained, facilitating the improvement of Tunneling Magnetic Resistivity (TMR) and the enhancement of read performance.
In summary, the structure for optimizing the writing performance of the Magnetic Random Access Memory (MRAM) and the preparation method thereof provided by the invention are particularly suitable for a Magnetic Tunnel Junction (MTJ) process (corresponding to a CMOS process node of 20nm or more) of more than 40nm, reduce power consumption, improve the reading and writing speed, and can be used as an alternative scheme of a cache.
FIG. 1 is a schematic diagram of a structure for optimizing the write performance of a Magnetic Random Access Memory (MRAM) according to the present invention, in which a reverse magnetic domain is introduced into a Free Layer (FL) by a Write Accelerator (WA) 31 during writing, and the magnetization vector in the Free Layer (FL) 42c is accelerated.
More specifically, as shown at I in FIG. 1, when the MTJ is in a high resistance state (i.e., logic "1"), the magnetization vector of the Free Layer (FL) 42c and the magnetization vector of the Reference Layer (RL) 42a are antiparallel.
As shown in II in fig. 1, in order to achieve inversion of the magnetization vector of the Free Layer (FL) 42c, a current greater than the critical current density may BE passed from the upper end of the Free Layer (FL) 42c (i.e., a non-spin-excited electron flow is passed from the lower end of the Reference Layer (RL) 42 a), and in order to accelerate the inversion of the magnetization vector of the Free Layer (FL) 42c, a Write Accelerator (WA) 31 is provided below the Bottom Electrode (BE) and at a position a below the reference layer 42 a.
Further, the Write Accelerator (WA) 31 is much smaller in size than the Magnetic Tunnel Junction (MTJ), and the Write Accelerator (WA) may BE disposed at any position below the Bottom Electrode (BE).
In this case, the electron flow passes through the Write Accelerator (WA) 31, and first the reverse magnetic domains 1, 2 are produced in the Free Layer (FL) located directly above the Write Accelerator (WA) 31, and then the reverse domains nucleate, expand and complete magnetization vector switching.
As shown in fig. 1 at II, after the magnetization vectors are completely flipped, the magnetization vectors of the Free Layer (FL) 42c and the Reference Layer (RL) 42c are parallel to each other, and the MTJ at this time assumes a low resistance state (i.e., logic "0").
Through the process i→iii, writing from "1" to "0" is completed.
More specifically, as shown in IV, when the MTJ is in a low resistance state (i.e., logic "0"), the magnetization vector of the Free Layer (FL) 42c and the magnetization vector of the Reference Layer (RL) 42a are parallel to each other.
As shown in V, in order to achieve inversion of the magnetization vector of the Free Layer (FL) 42c, a current greater than the critical current density may BE passed from the lower end of the Reference Layer (RL) 42a (i.e., a non-spin-excited electron flow is passed from the upper end of the Free Layer (FL) 42 c), and in order to accelerate the inversion of the magnetization vector of the Free Layer (FL) 42c, a Write Accelerator (WA) 31 is provided at a position a below the Bottom Electrode (BE) and below the Reference Layer (RL) 42 a.
Further, the Write Accelerator (WA) 31 is much smaller in size than the Magnetic Tunnel Junction (MTJ), and the Write Accelerator (WA) may BE disposed at any position below the Bottom Electrode (BE).
Under such conditions, a current is passed through the Write Accelerator (WA) 31 and reverse magnetic domains 3, 4 are first produced in the Free Layer (FL) directly above the Write Accelerator (WA) 31, followed by nucleation of the reverse domains, expansion and complete magnetization vector switching.
After the magnetization vectors are fully flipped, the magnetization vectors of the Free Layer (FL) 42c and the Reference Layer (RL) 42a are antiparallel, as shown at IV, with the MTJ exhibiting a high resistance state (i.e., a logic "1").
Through the process iv→vi, writing from "0" to "1" is completed.
By fabricating a Write Accelerator (WA) 31 much smaller than the Magnetic Tunnel Junction (MTJ) below the MTJ, the production of reverse magnetic domains in the Free Layer (FL) 42c is facilitated, which will accelerate the inversion of the magnetization vector of the Free Layer (FL) 42c, reduce the write time and power consumption, be well suited for MRAM circuits with MTJ sizes above 40nm, and be well suited for use in cache memory.
A preparation method of a structure for optimizing writing performance of a Magnetic Random Access Memory (MRAM) comprises the following specific steps:
step one: a surface polished CMOS substrate 100 with metal lines Mx (x.gtoreq.1) is provided, in FIG. 2, the metal lines Mx (x.gtoreq.1) 120 material is Cu.
Step two: in fig. 3, a Bottom Electrode Via (BEV) 230 is fabricated on the substrate 100 after the planarization process, and is planarized.
Wherein the Bottom Electrode Via (BEV) etch stop layer 210 is SiON, siN, siN, siC or SiCN and the Bottom Electrode Via (BEV) interlayer dielectric 220 is SiO 2 SiON or Low-K dielectric.
Further, the Low-k dielectric means a material having a dielectric constant (k) lower than that of silicon dioxide (k=3.9), and in practice, the Low-k material may be a hydrogen Silicate (HydrogenSilsequioxane, HSQ, k=2.8 to 3.0), a methyl Silicate (MSQ, k=2.5 to 2.7) containing si—ch3 functional groups, a hybrid organosiloxane polymer (Hybrid Organic Siloxane Polymer, HOSP) film (k=2.5) synthesized by combining a hydrogen Silicate HSQ and a methyl Silicate MSQ, a Porous SiOCH film (k=2.3 to 2.7), or even a Porous Silicate (Porous Silicate) organic polymer compound having an ultralow dielectric constant (k < 2.0) and a Porous SiOCH film having a dielectric constant (k) of 1.9.
The Bottom Electrode Via (BEV) 230 is formed by W, typically by chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), atomic layer deposition (Atomic Layer Deposition, ALD) or ion beam deposition (Ion Beam Deposition, IBD). A layer of Ti/TiN is typically deposited as a diffusion barrier prior to deposition.
After the deposition of the BEV metal 230, the BEV metal is polished down to the BEV via interlayer dielectric 220 using a chemical mechanical polishing (Chemical Mechanical Planarization, CMP) method.
Step three: in fig. 4, a Write Accelerator (WA) metal 310 is patterned and etched over a Bottom Electrode Via (BEV) 230, then a Write Accelerator (WA) dielectric 320 is filled and planarized using Chemical Mechanical Planarization (CMP).
Wherein, in order to have a sufficient height of the Write Accelerator (WA) metal 310, the depth of the selectively etched W Bottom Electrode Via (BEV) 230 may be selected to be 5nm to 40nm.
In fig. 4 (b) and 5, the Write Accelerator (WA) 31 is generally much smaller in size than the top opening of the Bottom Electrode Via (BEV) 230, and the pattern may be near the center of the Bottom Electrode Via (BEV) 230 or off-center, and may be any shape that can be machined, such as: "∈", "very good", "" X "," "l", "" | "," ≡ "," -or "(").
Since the Write Accelerator (WA) metal 310 is fabricated directly by etching the Bottom Electrode Via (BEV) 230, the material of the Write Accelerator (WA) metal 310 is also W.
The material of the Write Accelerator (WA) dielectric 320 is SiC, siN or SiCN, typically by means of CVD deposition.
Furthermore, due to the smaller size of the Write Accelerator (WA), better local surface Roughness (RMS) can be obtained in the CMP process, and under this condition, a higher quality barrier layer can be obtained, which is beneficial to the improvement of Tunneling Magnetic Resistivity (TMR) and the improvement of reading performance.
Step four: in fig. 6, a Bottom Electrode (BE) 410, a Magnetic Tunnel Junction (MTJ) 420 multilayer film, a Top Electrode (TE) 430 are deposited, and a Magnetic Tunnel Junction (MTJ) 420 memory cell is fabricated, and finally a Bit Line (BL) 520 connection is fabricated over the Top Electrode (TE) 430.
The bottom electrode 410 is made of Ti, tiN, ta, taN, W, WN or a combination thereof, and is typically formed by physical vapor deposition (Physical Vapor Deposition, PVD), and is typically planarized after deposition to achieve surface flatness for fabricating the magnetic tunnel junction.
The total thickness of the Magnetic Tunnel Junction (MTJ) 420 multilayer film is typically 3nm to 30nm, and typically includes a buffer Layer, a seed Layer, a synthetic antiferromagnetic Layer (SyAF), a lattice isolating Layer, a Reference Layer (RL), a Barrier Layer (BL), a Free Layer (FL), and a Capping Layer (CL) stacked sequentially upward.
(1) The Reference Layer (RL) has a thickness of 0.7nm to 1.5nm, typically Co, fe, ni, coFe, coB, feB, coFeB, or a combination thereof.
(2) Further, under the Reference Layer (RL), a superlattice synthetic anti-iron layer (SyAF) is formed, the structure of which is typically [ Co/(Pt, pd or Ni)] n Co/(Ru, ir or Rh)/Co [ (Pt, pd or Ni)/Co] m (wherein m.gtoreq.0, the thickness of the single layers of Co, (Pt, pd or Ni) and (Ru, ir or Rh) is less than 1nm, further, the thickness of the single layers of Co and (Pt, pd or Ni) may be below 0.5nm, such as 0.10nm,0.15nm,0.20nm,0.25nm,0.30nm,0.35nm,0.40nm,0.45nm or 0.50nm, and pass through a single layerThe layer lattice isolating layer achieves a magnetic coupling between the Reference Layer (RL) and the synthetic antiferroelectric layer (SyAF), which is typically composed of a material of Ta, W, mo, hf, fe, co (Ta, W, mo or Hf), fe (Ta, W, mo or Hf), feCo (Ta, W, mo or Hf) or FeCoB (Ta, W, mo or Hf).
(3) The Barrier Layer (BL) is a non-magnetic metal oxide having a total thickness of 0.6nm to 1.5nm, preferably MgO, al 2 O 3 ZnO, mgZnO, mgBO or MgAlO, mgO may be further selected.
(4) The Free Layer (FL) has a variable magnetic polarization and a total thickness of 1.1nm to 3nm, and is typically composed of CoB, feB, coFeB, coFe/CoFeB, fe/CoFeB, coFeB/(Ta, W, mo, hf)/CoFeB, fe/CoFeB/(W, mo, hf)/CoFeB, or CoFe/CoFeB/(W, mo, hf)/CoFeB, and further may be selected from CoFeB/(W, mo, hf)/CoFeB, fe/CoFeB/(W, mo, hf)/CoFeB.
(5) Typically, after the Free Layer (FL) deposition, a Capping Layer (CL), typically (Mg, al 2 O 3 A double layer structure of either ZnO, mgZnO, mgBO or MgAlO)/(W, mo, mg, nb, ru, hf, V, cr or Pt, or a combination thereof), more preferably, a MgO/(W, mo, hf)/Ru or MgO/Pt/(W, mo, hf)/Ru structure may be selected. The preferred effect of selecting MgO provides an additional source of interfacial anisotropy for the Free Layer (FL) and thus increases thermal stability.
(6) The material of the insulating cover (Encapsulation Layer, EL) 440 is typically SiC, siON, siCN or SiN, typically by CVD or ALD.
(7) The Top Electrode (TE) 430 has a thickness of 20nm to 100nm, and Ta, taN, ti, tiN, W, W, or any combination thereof, is selected to achieve a better profile in the halogen plasma.
The material of the Magnetic Tunnel Junction (MTJ) interlayer dielectric 450 is typically SiO 2 SiON or Low-k dielectric; the bit line connection (BL) 520 is Cu and is typically deposited with a TaN/Ta diffusion barrier layer prior to deposition.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that these are by way of example only, and the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the principles and spirit of the invention, but such changes and modifications fall within the scope of the invention.
Claims (7)
1. The structure for optimizing the writing performance of the magnetic random access memory is characterized by comprising a writing accelerator, wherein the writing accelerator is positioned at the lower side of a bottom electrode of the magnetic random access memory and the upper side of a bottom electrode through hole, and the writing accelerator is directly connected with the bottom electrode and the bottom electrode through hole; the write accelerator has a smaller size than the bottom electrode and the bottom electrode through hole, the write accelerator has an upper surface smaller in size than the bottom electrode, and a lower surface smaller in size than the bottom electrode through hole, and the write accelerator can be of any shape, and at the same time, the positions thereof relative to the bottom electrode and the bottom electrode through hole can be adjusted;
in the writing process of the magnetic random access memory, when the magnetic tunnel junction is in a high-resistance state, the magnetization vector of the free layer of the magnetic tunnel junction is antiparallel to the magnetization vector of the reference layer, current with the density larger than the critical current is adopted to be introduced from the upper end of the free layer so as to realize the overturning of the magnetization vector of the free layer, and after the magnetization vector is completely overturned, the magnetization vectors of the free layer and the reference layer are parallel to each other, and at the moment, the magnetic tunnel junction is in a low-resistance state; in the process of writing, when the magnetic tunnel junction is in a low resistance state, the magnetization vector of the free layer of the magnetic tunnel junction and the magnetization vector of the reference layer are parallel to each other, a current larger than the critical current density is adopted to be introduced from the lower end of the reference layer so as to realize the inversion of the magnetization vector of the free layer, and after the magnetization vector is completely inverted, the magnetization vectors of the free layer and the reference layer are antiparallel, and at the moment, the magnetic tunnel junction is in a high resistance state.
2. The structure for optimizing write performance of magnetic random access memory of claim 1, wherein a top-down cross-section of the write accelerator has a shape of: "∈", "very good", "" X "," "l", "" | "," ≡ "," -or "(").
3. The method of fabricating a structure for optimizing write performance of a magnetic random access memory of claim 1, comprising the steps of:
step one: providing a surface polished CMOS substrate with a metal connecting line Mx, wherein x is more than or equal to 1;
step two: manufacturing a bottom electrode through hole on the CMOS substrate after planarization treatment and grinding the bottom electrode through hole;
step three: patterning, defining and etching a write accelerator metal on the bottom electrode through hole, filling a write accelerator dielectric medium, and flattening the write accelerator dielectric medium by adopting chemical mechanical planarization;
step four: and sequentially depositing a bottom electrode, a magnetic tunnel junction multilayer film and a top electrode on the write accelerator, manufacturing a magnetic tunnel junction memory cell, and finally manufacturing bit line connection on the top electrode.
4. The method for fabricating a structure for optimizing write performance of a mram as recited in claim 3, wherein in step two, the bottom electrode via is formed from W by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or ion beam deposition, and a Ti/TiN layer is deposited as a diffusion barrier layer prior to deposition; after depositing the bottom electrode via metal, the bottom electrode via metal is polished down to the bottom electrode via interlayer dielectric using a chemical mechanical polishing process.
5. The method for fabricating a structure for optimizing write performance of a magnetic random access memory according to claim 3, wherein in the third step, the material of the etching write accelerator metal is W, and the etching depth is 5nm to 40nm; the material of the write accelerator dielectric is SiC, siN or SiCN by means of chemical vapor deposition.
6. The method of claim 3, wherein in the fourth step, the bottom electrode is made of Ti, tiN, ta, taN, W, WN or a combination thereof, and physical vapor deposition is adopted.
7. The method of claim 3, wherein in step four, a chemical mechanical planarization process is selected to planarize the structure after bottom electrode deposition.
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