CN109545957A - A kind of manufacturing method of magnetic RAM cell array and peripheral circuit line - Google Patents
A kind of manufacturing method of magnetic RAM cell array and peripheral circuit line Download PDFInfo
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- CN109545957A CN109545957A CN201710858159.0A CN201710858159A CN109545957A CN 109545957 A CN109545957 A CN 109545957A CN 201710858159 A CN201710858159 A CN 201710858159A CN 109545957 A CN109545957 A CN 109545957A
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Abstract
The present invention provides a kind of magnetic RAM cell array and the manufacturing methods of peripheral circuit line, include the following steps: that (1) provides the CMOS substrate with metal connecting line of surface polishing, and hearth electrode through-hole is made in substrate, metal is then filled in hearth electrode through-hole and by its surface rubbing；(2) contact of storage region hearth electrode and magnetic tunnel junction array are made on the hearth electrode through-hole of storage region, and the contact of logic region hearth electrode is made on the hearth electrode through-hole of logic region；(3) metal connecting line that production top electrode through-hole is connected with realization logic unit/storage unit.Hearth electrode contact metal film and magnetic tunnel junction multilayer film can be conducive to the raising of magnetic RAM magnetism/electric property with primary depositing in this way, and the complexity and cost of manufacture for simplifying technique reduce.
Description
Technical field
The present invention relates to a kind of magnetic RAM (MRAM) cell array and the manufacturing methods of peripheral circuit line, belong to
In magnetic RAM (MRAM, Magnetic Radom Access Memory) manufacturing technology field.
Background technique
In recent years, using the MRAM of magnetic tunnel junction (MTJ, Magnetic Tunnel Junction) by it is believed that being
Following solid state non-volatile memory body, it has the characteristics that high-speed read-write, large capacity and low energy consumption.Ferromagnetism MTJ is usual
For sandwich structure, layer is remembered wherein being magnetic, it can change the direction of magnetization to record different data；It is located in the middle absolutely
The tunnel barrier layer of edge；Magnetic reference layer, positioned at the other side of tunnel barrier layer, its direction of magnetization is constant.
For information can be recorded in this magnetoresistive element, it is proposed that using based on spin momentum transfer or spin-transfer torque
The write method of (STT, Spin Transfer Torque) switch technology, such MRAM are known as STT-MRAM.According to magnetic polarization
The difference in direction, STT-MRAM is divided into STT-MRAM and vertical STT-MRAM (i.e. pSTT-MRAM), the latter in face again to be had preferably
Performance.Method according to this, can be by providing spin polarized current to magnetoresistive element come the intensity of magnetization of inverting magnetization memory layer
Direction.In addition, the reduction of the volume with Magnetic memory layer, writes or spin polarized current that conversion operation need to be injected is also smaller.
Therefore, this write method can be achieved at the same time device miniaturization and reduce electric current.
Meanwhile can also reduce in view of switching electric current required when reducing MTJ element size, so the pSTT- in terms of scale
MRAM can be very good mutually to agree with state-of-the-art technology node.Therefore, it is desirable to be that pSTT-MRAM element is made into minimum ruler
It is very little, and there is extraordinary uniformity, and the influence to MTJ magnetism is minimized, used preparation method can also be real
Existing high good and the bad rate, pinpoint accuracy, high reliability, low energy consumption, and remain adapted to the temperature coefficient that data well save.Meanwhile
Write operation is changed based on resistance state in nonvolatile memory, thus to mtj memory device lifetime caused by needing to control thus
Destruction and shortening.However, one small-sized MTJ element of preparation may will increase the fluctuation of MTJ resistance, so that pSTT-MRAM
Biggish fluctuation can also be had therewith by writing voltage or electric current, can damage the performance of MRAM in this way.
In present MRAM manufacturing process, when making MTJ cell, it will usually which selection and CMOS Via are misaligned
Mode, it may be assumed that so-called off-axis structure, the mode that this and cmos circuit integrates are highly detrimental to the contracting of MRAM circuit
Macro requirement is highly detrimental to production microminiature magnetic storage requirement.
Recently, in order to realize the requirement of MRAM circuit micromation, usually in the CMOS through-hole (VIA of surface polishingx(x >=
1) MTJ cell is directly made on), it may be assumed that so-called on-axis structure.In the cmos circuit using copper wiring, all through-holes
(VIA) and material used by line (M, Metal) is all metallic copper.However, due to the size ratio VIA of mtj structure unitx
(x >=1) top opening size is small, when etching magnetic tunnel junction and its hearth electrode, in order to make between MTJ cell completely
Partition, it is necessary to over etching is carried out, in over etching, not by magnetic tunnel junction and its copper VIA of hearth electrode coveringx(x >=1)
Region will be partially etched, while can also damage its diffusion barrier layer (Ta/TaN), copper VIA will be will form in this wayx(x >=
1) the dielectric diffusion admittance of low-k outside it is arrived, Cu atom will be diffused into low-k dielectric, this will certainly be to magnetic
The electric property of property random access memory, such as: time correlation dielectric breakdown (TDDB, Time Dependent Dielectric
Breakdown) and electron mobility (EM, Electron Mobility) etc., cause to damage.
In addition, during magnetic tunnel junction and its hearth electrode over etching, due to ion bombardment (Ion
Bombardment), it will copper atom and its formation compound are splashed to the side wall of magnetic tunnel junction and the low-k being etched
The surface of material, to be polluted to entire MRAM device.
Summary of the invention
The manufacture craft and alignment of a kind of magnetic tunnel junction of the invention and its surrounding logic circuit.In memory block
Domain, using in metal connecting line (Mx, Metalx(x >=1)) on successively make hearth electrode through-hole (BEV, Bottom Electrode
Via), hearth electrode contact (BEC, Bottom Electrode Contact), magnetic tunnel junction structure unit (MTJ) and top electrode
Through-hole (TEV, Top Electrode Via)；BEV, BEC, MTJ and TEV are successively aligned；In logic region, then using top
The mode that electrode through-hole (TEV) and hearth electrode contact (BEC) are connected directly realizes that BEV, BEC and TEV are successively aligned；Finally,
One layer of metal connecting line (M is made on top electrode through-hole (TEV)x+1, x >=1) with realize magnetic RAM logic region and
Connection between storage region.
The present invention includes but is not limited solely to prepare magnetic RAM (MRAM), is also not necessarily limited to any process sequence or stream
Journey, as long as the same or similar method that the product or device that are prepared and following selection process sequence or process are prepared,
Its specific technical solution is as follows:
The manufacturing method of a kind of magnetic RAM cell array and peripheral circuit line, includes the following steps:
Step 1: the CMOS substrate with metal connecting line of surface polishing being provided, and makes hearth electrode through-hole in substrate, so
Metal is filled in hearth electrode through-hole afterwards；
Step 2: the contact of storage region hearth electrode and magnetic tunnel junction array are made on the hearth electrode through-hole of storage region,
The contact of logic region hearth electrode is made on the hearth electrode through-hole of logic region；
Step 3: the metal connecting line that production top electrode through-hole is connected with realization logic unit/storage unit.
Further, step 2 includes following subdivided step:
Step 2.1: the hearth electrode through-hole of storage region and logic region being polished, then on the hearth electrode through-hole polished
It is sequentially depositing hearth electrode contact metal, magnetic tunnel junction multilayer film and hard mask layer；
Step 2.2: graphic definition magnetic tunnel junction pattern, and hard mask layer and magnetic tunnel junction multilayer film are carved
It loses and keeps certain over etching, one layer of first magnetic is deposited around hard mask layer and magnetic tunnel junction multilayer film then after etching
Property tunnel knot dielectric capping layers；
Step 2.3: in storage region, using the magnetic tunnel junction pattern formed, with the first magnetic tunnel junction electricity Jie
Matter coating is hard mask, and the pattern of storage region hearth electrode contact is defined by autoregistration；In logic region, by using one
Cover the pattern that new photoresist defines the contact of logic region hearth electrode；Then using etching technics make storage region hearth electrode contact with
Logic region hearth electrode contact all partitions, finally remove remaining impurity；
Step 2.4: the covering of the second magnetic tunnel junction dielectric is deposited on completing the product after all techniques of step 2.3
Layer.
Further, step 2.2 includes following technical detail:
In step 2.2, completed using reactive ion etching and/or the method for ion beam etching to magnetic tunnel junction multilayer film
Etching and maintain certain over etching, finally storage region formed magnetic tunnel junction array.Reactive ion etching uses
CH3OH、CH4/Ar、C2H5OH、CH3OH/Ar or CO/NH3As main etching gas；Ion beam etching mainly uses Ar, Kr
Or Xe is as ion source.
In step 2.2, the material of the first magnetic tunnel junction dielectric capping layers is SiC, SiN or SiCN, the first magnetic tunnel
The forming method of road knot dielectric capping layers is using one among chemical vapor deposition, atomic layer deposition or ion beam depositing
Kind.
Further, step 2.3 includes following technical detail:
In step 2.3, in storage region, using the first magnetic tunnel junction dielectric capping layers as hard mask, memory block is realized
The definition of domain hearth electrode contact.In logic region, using photoresist as mask, logic region hearth electrode is defined using photoetching process
The pattern of contact.
In step 2.3, the contact of storage region hearth electrode and logic area are made using reactive ion etching/or ion beam etching
The contact partition of domain hearth electrode；Reactive ion etching uses CF4、SF6、CH3OH、CH4/Ar、C2H5OH、CH3OH/Ar or CO/NH3
As main etching gas；Ion beam etching mainly uses Ar, Kr or Xe as ion source.
Further, step 2.4 includes following technical detail:
In step 2.4, the material of the second magnetic tunnel junction dielectric capping layers is selected from SiC, SiN or SiCN, the second magnetic
Property tunnel knot dielectric capping layers forming method using among chemical vapor deposition, atomic layer deposition or ion beam depositing
It is a kind of.
Further, in step 3, using singly inlay twice or single dual-damascene technics realize metal connecting line system
Make.
Beneficial effects of the present invention: when making MTJ cell and hearth electrode and contacting, using first making MTJ cell,
Then the technique that is made is contacted to hearth electrode again, when making hearth electrode contact, in logic region, using photoetching/
Etching technics makes hearth electrode contact, in storage region, using hearth electrode contact autoregistration magnetic tunneling junction cell
Form is made, and such hearth electrode contact metal and magnetic tunnel junction multilayer film can be conducive to magnetic random with primary depositing
The raising of memory magnetism/electric property, the complexity and cost of manufacture of technique reduce.Due in magnetic tunneling junction cell battle array
Column contact (BEC) in the following, increasing one layer of hearth electrode, have effectively separated CMOS back segment copper and magnetic tunnel junction array, favorably
In the promotion of device electric property and yield.
Detailed description of the invention
In conjunction with attached drawing, and by reference to following detailed description, it will more easily to the present invention by more complete understanding
And its adjoint advantage and feature is more easily to understand, in which:
Fig. 1 (a) to Fig. 1 (c) is the step schematic diagram for making the filling of hearth electrode through-hole；
Fig. 2 (a) to Fig. 2 (d) is the step schematic diagram for making hearth electrode contact and magnetic tunnel junction array；
Fig. 3 (a) to Fig. 3 (d) is the step schematic diagram of the metal connecting line of single mosaic technology production twice；
Fig. 4 is the step schematic diagram of a dual-damascene technics production metal connecting line.
Wherein, two imaginary curves illustrate that left and right two parts are actually separated by very far in Fig. 3 (d) and Fig. 4, are intended merely to conveniently
It shows, just handle or so two parts are drawn in together in figure；In other each figures, left and right two parts are actually also to be separated by, in order to make
Figure is succinct, and two imaginary curves do not mark.
Description of symbols: the band metal connecting line (M of 100- surface polishingx(x >=1)) CMOS substrate, 201- hearth electrode
Through-hole (BEV) diffusion barrier layer, 202- hearth electrode through-hole (BEV) dielectric, 2031- hearth electrode through-hole (BEV) (storage region),
2032- hearth electrode through-hole (BEV) (logic region), 2041- hearth electrode through-hole (BEV) fill diffusion barrier layer (storage region),
2042- hearth electrode through-hole (BEV) fills diffusion barrier layer (logic region), and 2051- hearth electrode through-hole (BEV) fills (memory block
Domain), 2052- hearth electrode through-hole (BEV) fills (logic region), and 301- hearth electrode contacts (BEC) metal layer, and 302- includes seed
Magnetic tunnel junction (MTJ) multilayer film of layer, 303- push up hard mask layer, 304- magnetic tunnel junction dielectric capping layers (I), 305- light
Resistance, 401- magnetic tunnel junction dielectric capping layers (II), 402- top electrode through-hole (TEV) dielectric, 4031- top electrode through-hole
(TEV) (storage region), 4032- top electrode through-hole (TEV) (logic region), 4041- top electrode through-hole (TEV) filling diffusion resistance
Barrier (storage region), 4042- top electrode through-hole (TEV) fill diffusion barrier layer (logic region), 4051- top electrode through-hole
(TEV) (storage region) is filled, 4052- top electrode through-hole (TEV) fills (logic region), 501- metal connecting line (Mx+1(x >=
1) etching barrier layer, 502- metal connecting line (Mx+1(x >=1)) dielectric, 5031- metal connecting line (Mx+1(x >=1)) diffusion barrier
Layer (storage region), 5032- metal connecting line (Mx+1(x >=1) diffusion barrier layer (logic region), 5041- metal connecting line (Mx+1(x
>=1)) (storage region), 5042- metal connecting line (Mx+1(x >=1)) (logic region).
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.It should be noted that attached drawing of the present invention is all made of simplified form and uses non-essence
Quasi- ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
The manufacturing process of a kind of magnetic RAM cell array of the invention and peripheral circuit line, is provided at two layers
Between metal, the manufacture craft and alignment of magnetic RAM part and its surrounding logic circuit are carried out.In storage region,
Using in metal connecting line (Mx, Metalx(x >=1)) on successively make hearth electrode through-hole (BEV, Bottom Electrode
Via), hearth electrode contact (BEC, Bottom Electrode Contact), magnetic tunnel junction structure unit (MTJ) and top electrode
Through-hole (TEV, Top Electrode Via)；BEV, BEC, MTJ and TEV are successively aligned；In logic region, then using top
The mode that electrode through-hole (TEV) and hearth electrode contact (BEC) are connected directly realizes that BEV, BEC and TEV are successively aligned；Finally,
One layer of metal connecting line (M is made on top electrode through-hole (TEV)x+1, (x >=1)) to realize magnetic RAM logic region
Connection between storage region.Due in magnetic tunnel junction in the following, increase one layer of hearth electrode contact (BEC), effectively every
Broken CMOS back segment copper and magnetic tunnel junction array, is conducive to the promotion of device electric property and yield.Due in production MTJ
When unit and hearth electrode contact, using MTJ cell is first made, the technique made then is contacted to hearth electrode again,
When making hearth electrode contact, in logic region, hearth electrode contact is made of photoetching/etching technics, is being deposited
Storage area domain is made in the form of hearth electrode contacts autoregistration magnetic tunneling junction cell, and such hearth electrode contacts metal film
It can be conducive to the raising of magnetic RAM magnetism/electric property with magnetic tunnel junction multilayer film with primary depositing, technique
Complexity and cost of manufacture reduce.The present invention includes but is not limited solely to prepare magnetic RAM (MRAM), is also not necessarily limited to
Any process sequence or process, if what the product or device that are prepared and following selection process sequence or process were prepared
Same or similar method, the specific steps of which are as follows:
Step 1: the band metal connecting line (M of surface polishing is providedx(x >=1)) CMOS substrate 100, and make bottom on it
Then electrode through-hole (BEV, Bottom Electrode Via) 2031 and hearth electrode through-hole 2032 use singly inlaying for standard
The filling of (SD, Single Damascene) technique progress metallic copper.
Further, step 1 can be divided into following forming step:
Step 1.1: deposit diffusion barriers 201 and hearth electrode via dielectric 202, as shown in Fig. 1 (a), wherein diffusion
Barrier layer 201 both can be used as barrier metal line (Mx) in copper to the diffusion barrier of hearth electrode via dielectric 202, and can
With the etching barrier layer etched as BEV, with a thickness of 10nm~50nm, forming material can be SiN, SiC or SiCN etc.；Bottom
Electrode via dielectric 202 with a thickness of 60nm~150nm, forming material can be SiO2, SiON or low-k etc..
Wherein, low-k (low-k) dielectric medium refers to that dielectric constant (k) is lower than the material of silica (k=3.9)
Material, in the specific implementation, low-k material can be hydrogeneous silicate (Hydrogen Silsequioxane, HSQ, k=2.8~
3.0), containing Si-CH3The salt containing methane-siliconic acid (Methylsilsesquioxane, MSQ, k=2.5~2.7) of functional group,
Hybrid organic siloxane polymer (Hybrid synthesized by the comprehensive hydrogeneous silicates HSQ and MSQ of salt containing methane-siliconic acid
Organic Siloxane Polymer, HOSP) film (k=2.5), porous SiOCH film (k=2.3~2.7), or even can
Using organics high-molecular compounds such as the porosity silicates (Porous Silicate) of ultralow dielectric (k < 2.0)
And the porous SiOCH film that dielectric constant (k) is 1.9.
Step 1.2: in storage region and logic region while 2031 pattern of graphic definition hearth electrode through-hole (BEV), bottom
2032 pattern of electrode through-hole, etching forms hearth electrode through-hole (BEV) 2031, hearth electrode through-hole 2032, as shown in Fig. 1 (b).It is carving
After erosion, remaining polymer is generally removed using dry process and/or wet clean process.
Step 1.3: filling metallic copper to hearth electrode through-hole (BEV) 2031,2032 the inside of hearth electrode through-hole, and using chemistry
Mechanical polishing (CMP, Chemical Mechanical Planarization) polishes, and forms hearth electrode through-hole and fills 2051, bottom
Electrode through-hole filling 2052, as shown in Fig. 1 (c)；Wherein, usually before electro-coppering, all can previously deposited one layer of Ti/TiN or
Ta/TaN diffusion barrier layer 2041, diffusion barrier layer 2042 and copper seed layer.
Step 2: in storage region, making magnetic tunnel junction (MTJ) cell array and hearth electrode contact below
(BEC), in logic region, hearth electrode contact (BEC) is made.
Further, step 2 can be divided into following forming step:
Step 2.1: on the hearth electrode through-hole (BEV) polished, being sequentially depositing hearth electrode contact (BEC) metal layer 301, magnetic
Property tunnel knot multilayer film 302 and top hard mask layer 303, as shown in Fig. 2 (a).
Wherein, hearth electrode contact (BEC) metal layer 301 is Ta, TaN, Ti, TiN, W or WN etc., thickness range 20nm
~80nm, can using chemical vapor deposition (CVD, Chemical Vapor Deposition), physical vapour deposition (PVD) (PVD,
Physical Vapor Deposition), atomic layer deposition (ALD, Atomic Layer Deposition) or ion beam it is heavy
The modes such as product (IBD, Ion Beam Deposition) are realized.
The overall thickness of magnetic tunnel junction (MTJ) multilayer film 302 be 15nm~40nm, can be by reference layer, barrier layer and
Remember layer the Bottom Pinned structure being superimposed upwards in turn either from memory layer, barrier layer and reference layer successively to
The Top Pinned structure of upper superposition.
Further, reference layer has magnetic polarization invariance, is face inner mold (iSTT-MRAM) or vertical (pSTT- according to it
MRAM) structure is different.The reference layer of face inner mold (iSTT-MRAM) generally has (IrMn or PtMn)/CoFe/Ru/CoFe/
CoFeB structure, preferred overall thickness are 10~30nm；The reference layer of vertical-type (pSTT-MRAM) generally have TbCoFe or
[Co/Pt]/Co/Ru/ [CoPt]/CoFeBm superlattice multilayer film structure usually needs one layer of seed layer, such as Ta/Pt below,
Its preferred reference layer overall thickness is 8~20nm.
Further, barrier layer is nonmagnetic metal oxide, preferably MgO or Al2O3, with a thickness of 0.5nm~3nm.
Further, the structure of bilayer MgO can be used.
Further, memory layer polarizes with variable magnetic, is face inner mold (iSTT-MRAM) or vertical (pSTT- according to it
MRAM) institute is different again for structure.The memory layer of face inner mold iSTT-MRAM is generally CoFe/CoFeB or CoFe/NiFe, preferred thick
Degree be 2nm~6nm, vertical-type pSTT-MRAM memory layer be generally CoFeB, CoFe/CoFeB, Fe/CoFeB, CoFeB (Ta, W,
Mo)/CoFeB, preferred thickness are 0.8nm~2nm.
Push up hard mask layer 303 with a thickness of 20nm~100nm, select Ta, TaN, W or WN etc. to obtain in halogen plasma-based
It obtains and more preferably carves profile.
Step 2.2: graphic definition magnetic tunnel junction pattern, and to top hard mask layer 303 and magnetic tunnel junction multilayer film
302 perform etching, and keep certain over etching, then, one layer of magnetic tunnel junction dielectric capping layers (I) 304 are deposited, such as Fig. 2
(b) shown in；
In the process, (LE, lithography-etching) or Twi-lithography two are once etched using a photoetching
The method of secondary etching (LELE, lithography-etching-lithography-etching) is completed to magnetic tunnel junction
Reactive ion (RIE) etching of definition and top hard mask layer 303, and remaining polymerization is removed using RIE or wet processing simultaneously
Object, so that pattern is transferred to the top of magnetic tunnel junction.
Using reactive ion etching (RIE, Reactive Ion Etching) and/or ion beam etching (IBE, Ion
Beam Etching) method complete to magnetic tunnel junction (MTJ) etch and maintain certain over etching；Finally, in storage region
Form magnetic tunnel junction (MTJ) array element.
Wherein, IBE mainly uses Ar, Kr or Xe etc. as ion source；RIE mainly uses CH3OH、CH4/ Ar,
C2H5OH、CH3OH/Ar or CO/NH3Deng as main etching gas.
Wherein, 304 material of magnetic tunnel junction dielectric capping layers (I) is SiC, SiN or SiCN etc., and forming method can
To use chemical vapor deposition (CVD, Chemical Vapor Deposition), atomic layer deposition (ALD, Atomic Layer
Deposition) or the modes such as ion beam depositing (IBD, Ion Beam Deposition) are realized.
Step 2.3: in storage region, using the magnetic tunnel junction dielectric capping layers (I) 304 of deposition for hard mask, adopt
With self aligned mode, the definition of hearth electrode contact (BEC) is realized；In logic region, using photoresist (PR, Photo Resist)
305 are used as mask, as shown in Fig. 2 (c).(BEC) pattern is contacted using the hearth electrode that photoetching process defines logic region；Then,
The hearth electrode of different units is set to contact (BEC) cell partition using etching technics, finally, remaining poly- using dry process removal
Object is closed, as shown in Fig. 2 (d).
Wherein, etching technics can realize that IBE mainly uses the conducts such as Ar, Kr or Xe using modes such as IBE or RIE
Ion source；RIE mainly uses CF4、SF6、CH3OH、CH4/Ar、C2H5OH、CH3OH/Ar or CO/NH3Deng as main etching
Gas.
Step 2.4: deposited magnetic tunnel knot dielectric capping layers (II) 401 again, wherein magnetic tunnel junction dielectric covers
401 material of cap rock (II) is SiC, SiN or SiCN etc., and forming method can use chemical vapor deposition (CVD), atomic layer
Deposit (ALD) or ion beam depositing (IBD) etc..
Step 3: production top electrode through-hole (TEV, Top Electrode Via) and realization logic unit/storage unit phase
Metal connecting line (the M of connectionx+1).It in this step, can be (SD, Single Damascene) or single using singly inlaying twice
Secondary dual damascene (DD, Dual Damascene) technique is realized.
Case study on implementation one: (SD, Single Damascene) technique is singly inlayed twice, its step are as follows:
Step 3.1.1: on magnetic tunnel junction dielectric capping layers (II) 401, depositing top electrode via dielectric 402,
Finally, top electrode through-hole (TEV) dielectric 402 is polished using flatening process, as shown in Fig. 3 (a)；Top electrode through-hole (TEV)
Dielectric 402 is SiO2, the materials such as SiON or low-k, with a thickness of 120nm~400nm.
Step 3.1.2: graphic definition simultaneously forms top electrode through-hole (TEV) 4031, top electrode through-hole using etching technics
4032；In logic region, it is allowed to be connected to hearth electrode contact metal layer 301；In storage region, it is allowed to be connected to top hard mask layer
303, in general, polymer is removed using cleaning process after the etch, as shown in Fig. 3 (b).
Step 3.1.3: filling metal forms top electrode through-hole filling 4051, top electrode through-hole filling 4052, and useization
It learns mechanical polishing (CMP) to be polished, as shown in Fig. 3 (c).Wherein, usually in plating (ECP, Electro Chemical
It Plating, all can previously deposited one layer of Ti/TiN or Ta/TaN diffusion barrier layer 4041,4042 and of diffusion barrier layer) before copper
Copper seed layer.
Step 3.1.4: deposited metal line (Mx+1) dielectric 502, graphic definition simultaneously etches to form connection logic region
With the metal connecting line slot of storage region, electro-coppering is polished to Wire connection slot the inside, and using chemically mechanical polishing, is patrolled with forming connection
Collect the metal connecting line (M in region and storage regionx+1) 5041, metal connecting line 5042, as shown in Fig. 3 (d)；Wherein, metal connecting line
(Mx+1) dielectric 502 with a thickness of 50nm~300nm, material SiO2, SiON or low-k etc., usually before the deposition,
The etching barrier layer 501 that a layer thickness is tens nanometers, material SiN, SiC or SiCN etc. will be deposited；Electro-coppering it
Before, it all can previously deposited one layer of Ti/TiN or Ta/TaN diffusion barrier layer 5031, diffusion barrier layer 5032 and copper seed layer.
Two: dual damascenes of case study on implementation (DD, Dual Damascene) technique, as shown in Figure 4；Its step are as follows:
Step 3.2.1: on magnetic tunnel junction dielectric capping layers (II) 401, depositing top electrode via dielectric 402,
Then, top electrode through-hole (TEV) dielectric 402 is polished using flatening process；Top electrode through-hole (TEV) dielectric 402 is
SiO2, the materials such as SiON or low-k, with a thickness of 120nm~400nm；Finally, deposited metal line (Mx+1) dielectric 502
With a thickness of 50nm~300nm, material SiO2, SiON or low-k etc., usually before the deposition, can all deposit a layer thickness
For tens nanometers of etching barrier layer 501, material SiN, SiC or SiCN etc..
Step 3.2.2: graphic definition and using etching technics formed top electrode through-hole (TEV) and connection logic region with
The metal connecting line slot of storage region makes top electrode through-hole 4032 be connected to hearth electrode contact metal layer 301 in logic region,
Storage region makes top electrode through-hole 4031 be connected to top hard mask layer 303, in general, being removed after the etch using cleaning process
Polymer.
Step 3.2.3: filling metal forms top electrode through-hole filling 4051, top electrode through-hole filling 4052 and metal connecting line
(Mx+1) 5041, metal connecting line 5042, and polished using chemically mechanical polishing；It wherein, all can be prior usually before electro-coppering
Deposit one layer of Ti/TiN or Ta/TaN diffusion barrier layer 4041, diffusion barrier layer 4042, diffusion barrier layer 5031, diffusion barrier layer
5032 and copper seed layer.
The preferred embodiment of the present invention has been described in detail above.It should be appreciated that those skilled in the art without
It needs creative work according to the present invention can conceive and makes many modifications and variations.Therefore, all technologies in the art
Personnel are available by logical analysis, reasoning, or a limited experiment on the basis of existing technology under this invention's idea
Technical solution, all should be within the scope of protection determined by the claims.
Claims (10)
1. the manufacturing method of a kind of magnetic RAM cell array and peripheral circuit line, which is characterized in that including as follows
Step:
Step 1: the CMOS substrate with metal connecting line of surface polishing being provided, and makes hearth electrode through-hole on the substrate, so
Metal is filled in the hearth electrode through-hole afterwards；
Step 2: the contact of storage region hearth electrode and magnetic tunnel junction array are made on the hearth electrode through-hole of storage region,
The contact of logic region hearth electrode is made on the hearth electrode through-hole of logic region；
Step 3: the metal connecting line that production top electrode through-hole is connected with realization logic unit/storage unit.
2. the manufacturing method of a kind of magnetic RAM cell array according to claim 1 and peripheral circuit line,
It is characterized in that, the step 2 includes following subdivided step:
Step 2.1: the hearth electrode through-hole of the storage region and the logic region being polished, then described in polish
Hearth electrode contact metal, magnetic tunnel junction multilayer film and hard mask layer are sequentially depositing on hearth electrode through-hole；
Step 2.2: graphic definition magnetic tunnel junction pattern, and to the hard mask layer and the magnetic tunnel junction multilayer film into
Row etches and keeps certain over etching, sinks around the hard mask layer and the magnetic tunnel junction multilayer film then after etching
One layer of first magnetic tunnel junction dielectric capping layers of product；
Step 2.3: in the storage region, using the magnetic tunnel junction pattern formed, with the described first magnetic tunnel
Road knot dielectric capping layers are hard mask, and the pattern of the storage region hearth electrode contact is defined by autoregistration；It is patrolled described
Region is collected, the pattern of the logic region hearth electrode contact is defined by using a set of new photoresist；Then etching technics is used
So that the storage region hearth electrode contact is contacted all partitions with the logic region hearth electrode, finally removes remaining impurity；
Step 2.4: depositing the second magnetic tunnel junction dielectric capping layers on completing the product after all techniques of step 2.3.
3. the manufacturing method of a kind of magnetic RAM cell array according to claim 2 and peripheral circuit line,
It is characterized in that, being completed using reactive ion etching and/or the method for ion beam etching to the magnetic tunnel in step 2.2
It ties the etching of multilayer film and maintains certain over etching, finally form the magnetic tunnel junction array in storage region.
4. the manufacturing method of a kind of magnetic RAM cell array according to claim 3 and peripheral circuit line,
It is characterized in that, the reactive ion etching uses CH in step 2.23OH、CH4/Ar、C2H5OH、CH3OH/Ar or CO/NH3
As main etching gas；The ion beam etching mainly uses Ar, Kr or Xe as ion source.
5. the manufacturing method of a kind of magnetic RAM cell array according to claim 2 and peripheral circuit line,
It is characterized in that, in step 2.2, the material of the first magnetic tunnel junction dielectric capping layers is SiC, SiN or SiCN, described
The forming method of first magnetic tunnel junction dielectric capping layers uses chemical vapor deposition, atomic layer deposition or ion beam depositing
One of.
6. the manufacturing method of a kind of magnetic RAM cell array according to claim 2 and peripheral circuit line,
It is characterized in that, in step 2.3, in the logic region, using the photoresist as mask, using photoetching process define described in patrol
Collect the pattern of region hearth electrode contact.
7. the manufacturing method of a kind of magnetic RAM cell array according to claim 2 and peripheral circuit line,
It is characterized in that, contacting the storage region hearth electrode using reactive ion etching/or ion beam etching in step 2.3
All partitions are contacted with the logic region hearth electrode.
8. the manufacturing method of a kind of magnetic RAM cell array according to claim 7 and peripheral circuit line,
It is characterized in that, the reactive ion etching uses CF in step 2.34、SF6、CH3OH、CH4/Ar、C2H5OH、CH3OH/Ar or
Person CO/NH3As main etching gas；The ion beam etching mainly uses Ar, Kr or Xe as ion source.
9. the manufacturing method of a kind of magnetic RAM cell array according to claim 2 and peripheral circuit line,
It is characterized in that, the material of the second magnetic tunnel junction dielectric capping layers is selected from SiC, SiN or SiCN in step 2.4,
The forming method of the second magnetic tunnel junction dielectric capping layers uses chemical vapor deposition, atomic layer deposition or ion beam
One of deposition.
10. the manufacturing method of a kind of magnetic RAM cell array according to claim 1 and peripheral circuit line,
It is characterized in that, in step 3, using singly inlaying twice or single dual-damascene technics realizes the production of the metal connecting line.
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| WO2021238573A1 (en) * | 2020-05-28 | 2021-12-02 | International Business Machines Corporation | Dual damascene crossbar array for disabling a defective resistive switching device in the array |
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