CN109713121B - Method for manufacturing magnetic random access memory cell array and peripheral circuit thereof - Google Patents
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Abstract
The invention provides a method for manufacturing a magnetic random access memory cell array and a peripheral circuit thereof, which comprises the following steps: (1) Providing a CMOS substrate with a polished surface and a metal connecting wire, manufacturing a bottom electrode through hole on the CMOS substrate, and filling metal copper in the bottom electrode through hole; (2) making a bottom electrode contact on the bottom electrode through hole; (3) Manufacturing a magnetic tunnel junction structure unit in a storage area, wherein the magnetic tunnel junction structure unit consists of a bottom seed layer, a magnetic tunnel junction multilayer film and a top hard mask layer; (4) And manufacturing a top electrode through hole in the logic area and a metal copper connecting wire for realizing the connection of the logic unit/the storage unit. Because a layer of bottom electrode contact is added below the magnetic tunnel junction, the situation that a CMOS rear-section copper through hole is directly connected with an etching process in the manufacture of the magnetic tunnel junction array is effectively avoided, the improvement of the electrical performance and the yield of a device is facilitated, and meanwhile, the process complexity and the manufacturing cost are greatly reduced.
Description
Technical Field
The invention relates to a method for manufacturing a Magnetic random Access Memory unit array and peripheral circuits thereof, belonging to the technical field of Magnetic Random Access Memory (MRAM) manufacturing.
Background
In recent years, MRAM using Magnetic Tunnel Junction (MTJ) is considered as a future solid-state nonvolatile memory, which has features of high speed read and write, large capacity, and low power consumption. Ferromagnetic MTJs are typically sandwich structures with a magnetic memory layer that can change the magnetization direction to record different data; an insulating tunnel barrier layer in between; and the magnetic reference layer is positioned on the other side of the tunnel barrier layer, and the magnetization direction of the magnetic reference layer is unchanged.
In order to be able to record information in such a magnetoresistive element, a writing method based on Spin momentum Transfer (STT) switching technology has been proposed, and such an MRAM is called STT-MRAM. STT-MRAM is further classified into in-plane STT-MRAM and perpendicular STT-MRAM (i.e., pSTT-MRAM), which have better performance depending on the direction of magnetic polarization. In this way, the magnetization direction of the magnetic memory layer can be reversed by supplying a spin-polarized current to the magnetoresistive element. In addition, as the volume of the magnetic memory layer is reduced, the smaller the spin-polarized current to be injected for writing or switching operation. Therefore, this writing method can achieve both device miniaturization and current reduction.
Meanwhile, the pSTT-MRAM can be well matched with the most advanced technology node in terms of scale, because the required switching current is reduced when the size of the MTJ element is reduced. Therefore, it is desirable to make the pSTT-MRAM device extremely small in size, with excellent uniformity, and with minimal impact on the MTJ magnetic properties, by a fabrication method that also achieves Gao Liangyou rate, high accuracy, high reliability, low power consumption, and maintains a temperature coefficient suitable for good data storage. Meanwhile, the write operation in the nonvolatile memory is based on the resistance state change, so that it is necessary to control the damage and shortening of the life of the MTJ memory device caused thereby. However, the fabrication of a small MTJ device may increase the fluctuation of MTJ resistance, so that the write voltage or current of pSTT-MRAM may fluctuate greatly, which may impair the performance of MRAM.
In the present MRAM fabrication process, CMOS VIAs (VIA) are typically polished on the surface to meet the scaling requirements of MRAM circuits x (x>= 1)) directly on the MTJ cell, i.e.: the so-called on-axis structure. In a CMOS circuit using copper process, all the material used for the VIAs (VIA) and the interconnects (M, metal) is copper Metal. However, the size of the unit cell is larger than that of VIA due to the MTJ structure x (x>= 1) top opening size is small, when etching magnetic tunnel junction and its bottom electrode, in order to completely separate MTJ cell, over etching must be performed, in over etching, copper VIA not covered by magnetic tunnel junction and its bottom electrode x (x>Area of = 1) will be partially etched while also damaging its diffusion barrier (Ta/TaN), which will form copper VIA x (x>= 1) diffusion path to the low-k dielectric outside it, cu atoms will diffuse into the low-k dielectric, which will tend to contribute to the electrical properties of the magnetic random access memory, such as: time Dependent Dielectric Breakdown (TDDB), electron Mobility (EM), etc., causing damage.
In addition, during the over-etching of the magnetic tunnel junction and its bottom electrode, copper atoms and their forming compounds will be sputtered to the sidewalls of the magnetic tunnel junction and the surface of the etched low-k material due to Ion Bombardment (Ion Bombardment), thereby contaminating the entire MRAM device.
Disclosure of Invention
The invention provides a method for manufacturing a magnetic random access memory cell array and a peripheral circuit thereof, which provides a manufacturing process and an alignment mode for a magnetic random access memory device and a peripheral logic circuit thereof between two layers of metal. In the storage region, metal connection (M) is adopted x (x>= 1)) sequentially manufacturing a Bottom Electrode through hole (BEV), a Bottom Electrode Contact (BEC), and a magnetic tunnel junction structure unit (MTJ); the BEV, BEC and MTJ are aligned in sequence; in the logic circuit area, the top electrode through hole (TEV) and the Bottom Electrode Contact (BEC) are directly connected, and the BEV, the BEC and the TEV are sequentially aligned; finally, a metal line (M) is formed directly on the Top Electrode Via (TEV) and on top of the MTJ x+1 (x>= 1)) to enable the connection between the logical area and the storage area of the magnetic random access memory.
The invention includes, but is not limited to, the preparation of Magnetic Random Access Memory (MRAM), and is not limited to any process sequence or flow, as long as the prepared product or device is the same or similar to the following method prepared by the preferred process sequence or flow, and the specific technical scheme is as follows:
a method of fabricating an array of magnetic random access memory cells and surrounding circuitry, comprising the steps of:
step 1: providing a CMOS substrate with a polished surface and a metal connecting wire, manufacturing a bottom electrode through hole on the substrate, and then filling metal copper in the bottom electrode through hole;
step 2: making a bottom electrode contact on the bottom electrode through hole;
and step 3: manufacturing a magnetic tunnel junction structure unit in a storage area, wherein the magnetic tunnel junction structure unit consists of a bottom seed layer, a magnetic tunnel junction multilayer film and a top hard mask layer;
and 4, step 4: and manufacturing a top electrode through hole in the logic area and a metal copper connecting wire for realizing the connection of the logic unit/the storage unit.
Further, in step 1, a single damascene process is adopted to fill the copper metal.
Further, the material of the bottom electrode contact in step 2 is selected from one of Ta, taN, ti, tiN, W or WN.
Further, step 3 comprises the following subdivision steps:
step 3.1: sequentially forming a bottom seed layer, a magnetic tunnel junction multilayer film and a top hard mask layer on the ground bottom electrode contact;
step 3.2: the magnetic tunnel junction pattern is defined in a graphical mode, and the top hard mask layer, the magnetic tunnel junction multilayer film and the bottom seed layer are etched;
step 3.3: depositing a dielectric covering layer around the etched bottom seed layer, the magnetic tunnel junction multilayer film and the top hard mask layer and covering the whole etched area and the top of the top hard mask layer;
step 3.4: depositing a magnetic tunnel junction dielectric around the dielectric capping layer, and grinding down the magnetic tunnel junction dielectric and a portion of the dielectric capping layer until a top of the top mask layer is exposed;
further, the dielectric cap material is selected from one of SiC, siN, or SiCN.
Further, the magnetic tunnel junction dielectric is selected from SiO 2 SiON or a low dielectric constant dielectric, i.e., a dielectric constant less than SiO 2 The material of (1).
Further, the total thickness of the magnetic tunnel junction multilayer film is 15 nm-40 nm.
Further, the thickness of the top hard mask layer is 20nm to 100nm.
Further, the material of the top hard mask layer is selected from one of Ta, taN, W or WN.
Further, step 4 is implemented by using a double single damascene or a double damascene process.
The invention has the beneficial effects that: because a layer of Bottom Electrode Contact (BEC) is added below the magnetic tunnel junction, the situation that a CMOS rear-section copper through hole is directly connected with an etching process in the magnetic tunnel junction array manufacturing process is effectively avoided, the improvement of the electrical performance and the yield of a device is facilitated, meanwhile, because the Top Electrode through hole (TEV, top Electrode Via) is not formed above the magnetic tunnel junction, the process complexity and the manufacturing cost are greatly reduced.
Drawings
The accompanying drawings are schematic diagrams of various steps of a method for fabricating a magnetic random access memory array and its surrounding circuitry in accordance with a preferred embodiment of the present invention, wherein:
FIGS. 1 (a) to 1 (c) are schematic views illustrating steps for forming a bottom electrode via fill;
FIGS. 2 (a) to 2 (b) are schematic views illustrating steps for forming a bottom electrode contact;
FIGS. 3 (a) to 3 (d) are schematic diagrams illustrating steps of fabricating a magnetic tunnel junction structure unit;
FIGS. 4 (a) to 4 (b) are schematic views illustrating steps of forming metal lines by two single damascene processes;
FIG. 5 is a schematic diagram of a step of forming metal interconnects by a dual damascene process;
description of reference numerals: 100-surface polished metal wiring (M) x (x>= 1)) CMOS substrate, 201-Bottom Electrode Via (BEV) diffusion barrier layer, 202-Bottom Electrode Via (BEV) dielectric, 203-Bottom Electrode Via (BEV), 204-Bottom Electrode Via (BEV) filled diffusion barrier layer, 205-Bottom Electrode Via (BEV) filled, 301-Bottom Electrode Contact (BEC) metal, 302-Bottom Electrode Contact (BEC), 303-Bottom Electrode Contact (BEC) dielectric, 401-Magnetic Tunnel Junction (MTJ) multilayer film, 402-top hard mask layer, 403-dielectric capping layer, 404-magnetic tunnel junction dielectric, 405-Top Electrode Via (TEV) filled diffusion barrier layer (logic region), 406-Top Electrode Via (TEV) (logic region), 501-metal wire (M) wire x+1 (x>= 1)), diffusion barrier layer, 502-metallic copper wiring (M) x+1 (x>＝1))。
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. It is to be noted that the drawings are in simplified form and are not to precise scale, which is provided for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The invention provides a method for manufacturing a magnetic random access memory cell array and a peripheral circuit thereof, which provides a manufacturing process and an alignment mode for a magnetic random access memory and a peripheral logic circuit thereof between two layers of metal. In the storage region, metal connection (M) is adopted x ，Metal x (x>= 1) sequentially manufacturing a Bottom Electrode through hole (BEV), a Bottom Electrode Contact (BEC), and a magnetic tunnel junction structure unit (MTJ); the BEV, BEC and MTJ are aligned sequentially. In the logic circuit area, the top electrode through hole (TEV) and the Bottom Electrode Contact (BEC) are directly connected, and the BEV, the BEC and the TEV are sequentially aligned; finally, a metal line (M) is formed directly on the Top Electrode Via (TEV) and on top of the MTJ x+1 ，x>= 1) to enable the connection between the logical area and the storage area of the magnetic random access memory. Because a layer of Bottom Electrode Contact (BEC) is added below the magnetic tunnel junction, the situation that a CMOS rear-section copper through hole is directly connected with an etching process in the magnetic tunnel junction array manufacturing process is effectively avoided, the improvement of the electrical performance and the yield of a device is facilitated, meanwhile, because the Top Electrode through hole (TEV, top Electrode Via) is not formed above the magnetic tunnel junction, the process complexity and the manufacturing cost are greatly reduced.
The present invention includes, but is not limited to, the fabrication of Magnetic Random Access Memory (MRAM) and is not limited to any process sequence or flow, as long as the resulting product or device is prepared by the same or similar method as that prepared by the following preferred process sequence or flow, and the specific steps are as follows:
step 1: metal-coated wiring (M) providing surface finish x (x>= 1) and a Bottom Electrode Via (BEV) 203 is fabricated thereon, and then, a filling of metal copper is performed using a standard Single Damascene (SD) process.
Further, the following formation steps can be divided:
step 1.1: deposited bottom electrode via diffusion barrierBarrier layer 201 and bottom electrode via dielectric 202, as shown in fig. 1 (a), wherein bottom electrode via diffusion barrier layer 201 can serve as both barrier metal line (M) x ) The diffusion barrier layer of the medium copper to the bottom electrode through hole dielectric 202 can also be used as an etching barrier layer for BEV etching, the thickness of the diffusion barrier layer is 10 nm-50 nm, and the forming material can be SiN, siC or SiCN and the like; the bottom electrode via dielectric 202 has a thickness of 60nm to 150nm, and the material for forming the bottom electrode via dielectric may be SiO 2 SiON, low-k, or the like;
the low dielectric constant (low-k) dielectric refers to a material having a dielectric constant (k) lower than that of silicon dioxide (k = 3.9), and in the specific implementation, the low-k material may be Hydrogen Silicate (HSQ, k =2.8 to 3.0), methylsilicate-containing (MSQ, k =2.5 to 2.7) containing Si-CH3 functional groups, hybrid organosiloxane Polymer (HOSP) synthesized by combining HSQ and MSQ containing methylsilicate (Hybrid Organic Siloxane Polymer, k = 2.5), porous SiOCH film (k =2.3 to 2.7), or even an Organic Polymer compound such as Porous Silicate having an ultra-low dielectric constant (k < 2.0) and a Porous SiOCH film having a dielectric constant (k) of 1.9.
Step 1.2: patterning and defining a Bottom Electrode Via (BEV) 203 pattern in the memory region and the logic region simultaneously, etching to form the Bottom Electrode Via (BEV) 203, as shown in fig. 1 (b), and removing residual polymer by using a dry process and/or a wet cleaning process after etching;
step 1.3: the bottom electrode via fill 205 is formed by filling copper metal into the Bottom Electrode Via (BEV) 203 and planarizing it using Chemical Mechanical Planarization (CMP), as shown in fig. 1 (c), wherein a Ti/TiN or Ta/TaN diffusion barrier layer 204 and a copper seed layer are typically deposited in advance before electroplating the copper.
Step 2: bottom Electrode Contacts (BEC) 302 are fabricated. Wherein, the Bottom Electrode Contact (BEC) 302 can be Ta, taN, ti, tiN, W or WN, etc.;
further, the following formation steps can be divided:
step 2.1: depositing a Bottom Electrode Contact (BEC) metal 301, as shown in fig. 2 (a), wherein the deposited Bottom Electrode Contact (BEC) metal 301 is 20nm to 80nm, and may be implemented by Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or Ion Beam Deposition (IBD);
step 2.2: the method comprises the steps of defining a Bottom Electrode Contact (BEC) 302 pattern in a graphical mode to be aligned with a bottom electrode through hole (BEV) 203, forming the bottom electrode contact 302 by adopting an Etching process, wherein the Etching process can be realized by adopting Reactive Ion Etching (RIE) or Ion Beam Etching (IBE, ion Beam Etching) and other processes, and removing residual polymers and the like by adopting a cleaning process after Etching;
wherein, IBE mainly adopts Ar, kr or Xe and the like as an ion source; mainly using Cl for RIE 2 Or CF 4 Etc. as the main etching gas.
Step 2.3: the Bottom Electrode Contact (BEC) dielectric 303 is filled and planarized using a planarization process down to the top of the Bottom Electrode Contact (BEC) 302. Wherein the Bottom Electrode Contact (BEC) dielectric 303 is SiO 2 SiON, low-k, or the like.
And step 3: manufacturing a magnetic tunnel junction structure unit (MTJ) comprising a seed layer at the bottom and a top hard mask layer in a storage area;
further, the following formation steps can be divided:
step 3.1: on the planarized Bottom Electrode Contact (BEC) 302, a seed layer, a magnetic tunnel junction multilayer film 401, and a top hard mask layer 402 are sequentially formed as shown in fig. 3 (a).
The total thickness of the Magnetic Tunnel Junction (MTJ) multilayer film is 15 nm-40 nm, and the MTJ multilayer film can be a Bottom Pin structure formed by sequentially and upwardly superposing a reference layer, a barrier layer and a memory layer or a Top Pin structure formed by sequentially and upwardly superposing a memory layer, a barrier layer and a reference layer.
Further, the reference layer has a magnetic polarization invariance that differs depending on whether it is an in-plane (iST-MRAM) or perpendicular (pSTT-MRAM) structure. The reference layer of the in-plane (iSTT-MRAM) typically has a (IrMn or PtMn)/CoFe/Ru/CoFe/CoFeB structure with a preferred total thickness of 10-30 nm; the reference layer of the vertical type (pSTT-MRAM) typically has a TbCoFe or [ Co/Pt ]/Co/Ru/[ CoPt ]/CoFeBm superlattice multilayer film structure, and typically requires a seed layer below, such as Ta/Pt, with a preferred total reference layer thickness of 8-20 nm.
Further, the barrier layer is a non-magnetic metal oxide, preferably MgO or Al 2 O 3 The thickness of the film is 0.5 nm-3 nm.
Further, a double-layered MgO structure may be employed.
Further, the memory layer has a variable magnetic polarization, which differs depending on whether it is an in-plane (iST-MRAM) or perpendicular (pSTT-MRAM) structure. The memory layer of the in-plane iSTT-MRAM is generally CoFe/CoFeB or CoFe/NiFe, and the thickness is preferably 2nm to 6nm, and the memory layer of the vertical pSTT-MRAM is generally CoFeB, coFe/CoFeB, fe/CoFeB, coFeB (Ta, W, mo)/CoFeB, and the thickness is preferably 0.8nm to 2nm.
The top hard mask layer 402 has a thickness of 20nm to 100nm, and Ta, taN, W, WN, etc. are selected to obtain a better profile in halogen plasma.
Step 3.2: defining a magnetic tunnel junction pattern in a graphical manner, and etching the top hard mask layer 402, the magnetic tunnel junction multilayer film 401 and the bottom electrode, as shown in fig. 3 (b);
in this process, the definition of the magnetic tunnel junction and the Reactive Ion (RIE) etching of the top hard mask layer 402 are accomplished using one lithography-etching (LE) or two lithography-etching (LELE) and simultaneously RIE or wet process is used to remove the residual polymer to transfer the pattern to the top of the magnetic tunnel junction.
Finishing the Etching of the magnetic tunnel junction by adopting a Reactive Ion Etching (RIE) method and/or an Ion Beam Etching (IBE) method;
wherein, IBE mainly adopts Ar, kr or Xe and the like as an ion source; RIE mainly employs CH 3 OH、CH 4 /Ar、C 2 H 5 OH、CH 3 OH/Ar or CO/NH 3 Etc. as the main etching gas；
Step 3.3: depositing a dielectric capping layer 403 around the magnetic tunnel junction multilayer film 401 and the top hard mask layer 402 and covering the entire etched area, including the top hard mask layer; as shown in FIG. 3 (c); the dielectric cap layer 403 is made of SiC, siN, or SiCN, and the forming method thereof can be implemented by Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), or Ion Beam Deposition (IBD).
Step 3.4: depositing a magnetic tunnel junction dielectric 404 around the dielectric cap layer 403 and planarizing the magnetic tunnel junction dielectric 404 with Chemical Mechanical Polishing (CMP) to the top hard mask layer 402;
wherein the magnetic tunnel junction dielectric 404 may be SiO 2 SiON, low-k, etc.
And 4, step 4: in the logic area, a Top Electrode Via (TEV) 406 and a metal copper connecting wire (M) for realizing the connection of the logic unit/the memory unit are manufactured x+1 ) 502. In this step, a double Single Damascene (SD) or a Double Damascene (DD) process may be used.
The first embodiment is as follows: the double Single Damascene (SD) process includes the following steps:
step 4.1.1: in the logic area, a top electrode through hole (TEV) is defined in a graphic mode and is formed by an etching process to be connected with a bottom electrode through hole (BEV) filling 205, and in the storage area, a metal copper connecting wire (M) is formed x+1 ) 502 are directly connected to the top hard mask layer 402; typically, a cleaning process is used to remove the polymer after etching;
step 4.1.2: fill metal to top electrode via 406 and polish flat using Chemical Mechanical Polishing (CMP); wherein a Ti/TiN or Ta/TaN diffusion barrier layer 405 and a copper seed layer are typically deposited in advance before Electroplating (ECP) copper, as shown in FIG. 4 (a).
Step 4.1.3: depositing metal connecting line (M) x+1 ) Dielectric, defining and etching to form metal wiring groove for connecting logic region and storage region, electroplating copper into the wiring groove, and polishing by chemical mechanical polishingFlat to form a metal copper line (M) connecting the logic region and the memory region x+1 ) 502, as shown in fig. 4 (b); wherein, the metal connecting line (M) x+1 ) The thickness of the dielectric medium is 50 nm-300 nm, and the material is SiO 2 SiON or low-k, etc., usually before deposition, an etching barrier layer with a thickness of tens of nanometers is deposited, and the material of the etching barrier layer is SiN, siC or SiCN, etc.; a Ti/TiN or Ta/TaN diffusion barrier layer 501 and a copper seed layer are deposited in advance prior to electroplating copper.
The second embodiment: a Dual Damascene (DD) process, as shown in fig. 5; the method comprises the following steps:
step 4.2.1: depositing a metal line (M) on the surface of the surface-polished MTJ dielectric 404 x+1 ) A dielectric; metal connecting wire (M) x+1 ) The dielectric 602 has a thickness of 50 nm-300 nm and is made of SiO 2 SiON or low-k, etc., usually before deposition, an etching barrier layer with a thickness of tens of nanometers is deposited, and the material of the etching barrier layer is SiN, siC or SiCN, etc.;
step 4.2.2: in the logic area, a Top Electrode Via (TEV) and a metal wiring trench connecting the logic area and the memory area are defined graphically and formed using an etching process such that the top electrode via 406 is connected to the Bottom Electrode Via (BEV) fill 205. Simultaneously, the storage area and the logic area are defined in a graphical mode and a metal copper connecting line (M) is formed by adopting an etching process x+1 ) 502, directly connected to the top hard mask layer 402 of the memory region and the Top Electrode Via (TEV) of the logic region; typically, a cleaning process is used to remove the polymer after etching;
step 4.2.3: fill copper metal to top electrode via 406 and metal copper interconnect (M) x+1 ) 502, and adopting chemical mechanical polishing to grind flat; wherein a Ti/TiN or Ta/TaN diffusion barrier layer 501 and a copper seed layer are typically deposited in advance prior to electroplating copper.
The foregoing detailed description of the preferred embodiments of the invention has been presented. It should be understood that numerous modifications and variations could be devised by those skilled in the art in light of the present teachings without departing from the inventive concepts. Therefore, the technical solutions available to those skilled in the art through logic analysis, reasoning and limited experiments based on the prior art according to the concept of the present invention should be within the scope of protection defined by the claims.
Claims (9)
1. A method of fabricating an array of magnetic random access memory cells and the circuitry surrounding the array, comprising the steps of:
step 1: providing a CMOS substrate with a polished surface and a metal connecting wire, manufacturing a bottom electrode through hole on the substrate, and then filling metal copper in the bottom electrode through hole;
the step 1 comprises the following steps:
step 1.1: depositing a bottom electrode via diffusion barrier layer and a bottom electrode via dielectric;
step 1.2: simultaneously defining a bottom electrode through hole pattern in a graphical manner in the storage area and the logic area;
step 1.3: filling metal copper into the bottom electrode through hole, and depositing a Ti/TiN or Ta/TaN diffusion barrier layer and a copper seed layer in advance before electroplating copper;
step 2: making a bottom electrode contact on the bottom electrode through hole;
the step 2 comprises the following steps:
step 2.1: depositing a bottom electrode contact metal;
step 2.2: graphically defining a bottom electrode contact pattern to be aligned with the bottom electrode via;
step 2.3: filling the bottom electrode contact dielectric and flattening by adopting a flattening process until the bottom electrode contacts the top;
and step 3: manufacturing a magnetic tunnel junction structure unit in a storage area, wherein the magnetic tunnel junction structure unit is composed of a bottom seed layer, a magnetic tunnel junction multilayer film and a top hard mask layer;
the step 3 comprises the following steps:
step 3.1: sequentially forming the bottom seed layer, the magnetic tunnel junction multilayer film and the top hard mask layer on the ground bottom electrode contact;
step 3.2: graphically defining a magnetic tunnel junction pattern, and etching the top hard mask layer, the magnetic tunnel junction multilayer film and the bottom seed layer;
step 3.3: depositing a dielectric covering layer around the etched bottom seed layer, the magnetic tunnel junction multilayer film and the top hard mask layer and covering the whole etched area and the top of the top hard mask layer;
step 3.4: depositing a magnetic tunnel junction dielectric around the dielectric covering layer, and grinding the magnetic tunnel junction dielectric and part of the dielectric covering layer until the top of the top hard mask layer is exposed;
and 4, step 4: and manufacturing a top electrode through hole in the logic area and a metal copper connecting wire for realizing the connection of the logic unit/the storage unit.
2. The method of claim 1, wherein the copper metal is filled in step 1 by a single damascene process.
3. The method of claim 1, wherein the bottom electrode contact in step 2 is made of a material selected from Ta, taN, ti, tiN, W and WN.
4. The method of claim 1, wherein the dielectric cap material is selected from the group consisting of SiC, siN, and SiCN.
5. The method of claim 1, wherein the magnetic tunnel junction dielectric is selected from the group consisting of SiO 2 SiON or a low dielectric constant dielectric, i.e. a dielectric constant lower than SiO 2 The material of (1).
6. The method of claim 1, wherein the total thickness of the magnetic tunnel junction multilayer film is 15nm to 40nm.
7. The method of claim 1, wherein the top hard mask layer has a thickness of 20nm to 100nm.
8. The method of claim 1, wherein the top hard mask layer is made of a material selected from Ta, taN, W and WN.
9. The method of claim 1 wherein step 4 is performed by a dual damascene process or a dual damascene process.
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