CN109545744B - Method for manufacturing magnetic random access memory unit array and peripheral circuit connecting line - Google Patents
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- H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
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Abstract
The invention provides a method for manufacturing a magnetic random access memory cell array and a peripheral circuit connecting line, and provides a manufacturing process and an alignment mode for a magnetic random access memory device and a peripheral logic circuit thereof between two layers of metal. In the storage area, a bottom electrode through hole, a bottom electrode contact, a magnetic tunnel junction structure unit and a top electrode through hole are sequentially manufactured on the metal connecting line and are sequentially aligned; in the logic circuit area, the top electrode through hole and the bottom electrode contact are directly connected, and the top electrode through hole, the bottom electrode contact and the bottom electrode through hole are sequentially aligned; and finally, manufacturing a layer of metal connecting wire on the top electrode through hole to realize the connection between the logic area and the storage area of the magnetic random access memory. Because a layer of bottom electrode contact is added below the magnetic tunnel junction unit array, the direct connection between the copper at the back section of the CMOS and the bottom of the magnetic tunnel junction array is effectively isolated, and the improvement of the electrical performance and the yield of the device is facilitated.
Description
Technical Field
The invention relates to a method for manufacturing a Magnetic Random Access Memory (MRAM) unit array and a peripheral circuit connecting line, belonging to the technical field of manufacturing of MRAM.
Background
In recent years, MRAM using Magnetic Tunnel Junction (MTJ) is considered as a future solid-state nonvolatile memory, which has features of high speed read and write, large capacity, and low power consumption. Ferromagnetic MTJs are typically sandwich structures, among which are: a magnetic memory layer which can change a magnetization direction to record different data; an insulating tunnel barrier layer in between; and the magnetic reference layer is positioned on the other side of the tunnel barrier layer, and the magnetization direction of the magnetic reference layer is unchanged.
In order to be able to record information in such a magnetoresistive element, a writing method based on Spin momentum Transfer (STT) switching technology has been proposed, and such an MRAM is called STT-MRAM. STT-MRAM is further classified into in-plane STT-MRAM and perpendicular STT-MRAM (i.e., pSTT-MRAM), which have better performance depending on the direction of magnetic polarization. In this way, the magnetization direction of the magnetic memory layer can be reversed by supplying a spin-polarized current to the magnetoresistive element. In addition, as the volume of the magnetic memory layer is reduced, the smaller the spin-polarized current to be injected for writing or switching operation. Therefore, this writing method can achieve both device miniaturization and current reduction.
Meanwhile, the pSTT-MRAM can be well matched with the most advanced technology node in terms of scale, because the required switching current is reduced when the size of the MTJ element is reduced. It is therefore desirable to make the pSTT-MRAM device extremely small in size, with very good uniformity, and with minimal impact on the MTJ magnetic properties, by a fabrication method that also achieves high yield, high accuracy, high reliability, low power consumption, and maintains a temperature coefficient suitable for good data storage. Meanwhile, the write operation in the nonvolatile memory is based on the resistance state change, so that it is necessary to control the damage and shortening of the life of the MTJ memory device caused thereby. However, the fabrication of a small MTJ device may increase the fluctuation of MTJ resistance, so that the write voltage or current of pSTT-MRAM may fluctuate greatly, which may impair the performance of MRAM.
In the current MRAM fabrication process, to meet the requirements for scaling MRAM circuits, surface-polished CMOS VIAs (VIA) are typically usedx(x>1)) directly on the MTJ cell, namely: the so-called on-axis structure. In a CMOS circuit using copper process, all the VIA (VIA) and the connecting line (M, Metal) are made of copper. However, the size of the unit cell is larger than that of VIA due to the MTJ structurex(x>1) small size of top opening, when etching the magnetic tunnel junction and its bottom electrode, over-etching must be performed in order to completely separate the MTJ cells, in which over-etching, the copper VIA not covered by the magnetic tunnel junction and its bottom electrodex(x>1) will be partially etched while also damaging its diffusion barrier (Ta/TaN), which will form a copper VIAx(x>1) diffusion path to the low-k dielectric outside it, Cu atoms will diffuse into the low-k dielectric, which will tend to contribute to the electrical properties of the mram, such as: time Dependent Dielectric Breakdown (TDDB), Electron Mobility (EM), etc., causing damage.
In addition, during the over-etching of the magnetic tunnel junction and its bottom electrode, copper atoms and their forming compounds will be sputtered onto the sidewalls of the magnetic tunnel junction and the surface of the etched low-k material due to ion bombardment (IonBombardment), thereby causing contamination and electrical shorting of the entire MRAM device.
Disclosure of Invention
The invention provides a method for manufacturing a magnetic random access memory cell array and a peripheral circuit connecting line, and provides a manufacturing process and an alignment mode for a magnetic random access memory device and a peripheral logic circuit thereof between two layers of metal. In the storage region, metal connection (M) is adoptedx(x>1), sequentially manufacturing a Bottom Electrode Via (BEV), a Bottom Electrode Contact (BEC), a Magnetic Tunnel Junction (MTJ), and a Top Electrode Via (TEV); the BEV, BEC, MTJ and TEV are aligned in sequence; in the logic circuit area, the top electrode through hole (TEV) and the Bottom Electrode Contact (BEC) are directly connected, and the BEV, the BEC and the TEV are sequentially aligned; finally, a metal line (M) is formed on the Top Electrode Via (TEV)x+1(x>1) to enable a connection between the logic and memory regions of the magnetic random access memory.
The invention includes but is not limited to the preparation of Magnetic Random Access Memory (MRAM), and is not limited to any process sequence or flow, as long as the prepared product or device is the same or similar to the method prepared by the following preferred process sequence or flow, and the specific technical scheme is as follows:
a method for manufacturing a magnetic random access memory cell array and a peripheral circuit connecting line comprises the following steps:
step 1: providing a CMOS substrate with a polished surface and a metal connecting wire, manufacturing a bottom electrode through hole on the substrate, and then filling metal in the bottom electrode through hole;
step 2: making a bottom electrode contact on the bottom electrode through hole;
and step 3: manufacturing a magnetic tunnel junction structure unit on the bottom electrode contact;
and 4, step 4: and manufacturing a top electrode through hole and a metal connecting wire for realizing the connection of the logic unit/the storage unit on the magnetic tunnel junction structure unit.
Further, step 2 comprises the following subdivision steps:
step 2.1: depositing a bottom electrode contact metal; the bottom electrode contact metal is selected from one of Ta, TaN, Ti, TiN, W or WN; the thickness of the bottom electrode contact metal deposition is 20 nm-80 nm; depositing the bottom electrode contact metal by adopting one mode of chemical vapor deposition, physical vapor deposition, atomic layer deposition or ion beam deposition;
step 2.2: defining a bottom electrode contact pattern in a graphical mode to enable the bottom electrode contact pattern to be aligned with the bottom electrode through hole, etching bottom electrode contact metal to form bottom electrode contact, and removing residual impurities after etching; the etching is realized by adopting a reactive ion etching or ion beam etching process;
step 2.3: filling a bottom electrode contact dielectric in the etched gap, and flattening the top of the bottom electrode contact dielectric until the top of the bottom electrode contact dielectric is flush with the top of the bottom electrode contact; the bottom electrode contact dielectric is SiO2SiON or a low dielectric constant dielectric, low dielectric constant dielectric being understood to mean a dielectric constant which is lower than SiO2The material of (1).
Further, the magnetic tunnel junction structure unit in the step 3 comprises a magnetic tunnel junction multilayer film and a hard mask. Preferably, a seed layer or etch stop layer is deposited under the magnetic tunnel junction multilayer film.
Furthermore, in step 4, a double-damascene process or a double-damascene process is adopted to realize the manufacture of the metal connecting wire.
The invention has the beneficial effects that: because a layer of Bottom Electrode Contact (BEC) is added below the magnetic tunnel junction unit array, the direct connection between the copper at the back section of the CMOS and the bottom of the magnetic tunnel junction array is effectively isolated, and the improvement of the electrical performance and the yield of the device is facilitated.
Drawings
The accompanying drawings are schematic diagrams of steps in a method of fabricating an array of magnetic random access memory cells and peripheral circuit traces according to a preferred embodiment of the present invention. Wherein:
FIGS. 1(a) to 1(c) are schematic views illustrating steps for forming a bottom electrode via fill;
FIGS. 2(a) to 2(b) are schematic views illustrating steps for forming a bottom electrode contact;
FIGS. 3(a) to 3(c) are schematic views illustrating steps of fabricating a magnetic tunnel junction structure unit;
FIGS. 4(a) to 4(d) are schematic views illustrating steps of forming metal lines by two single damascene processes;
FIG. 5 is a schematic diagram of a step of forming metal interconnects by a dual damascene process;
wherein, the two dotted curves in fig. 4(d) and fig. 5 illustrate that the left and right parts are actually far apart, and the left and right parts are drawn together only for convenience of illustration; in the other figures, the left and right portions are also physically separated, and the two dashed curves are not shown for simplicity.
Description of reference numerals: 100-surface polished metal wiring (M)x(x>1) CMOS substrate; 201-Bottom Electrode Via (BEV) diffusion barrier layer; 202-Bottom Electrode Via (BEV) dielectric; 203-Bottom Electrode Via (BEV); 204-Bottom Electrode Via (BEV) fill diffusion barrier; 205-Bottom Electrode Via (BEV) fill; 301-Bottom Electrode Contact (BEC) metal layer; 302-Bottom Electrode Contact (BEC); 303-Bottom Electrode Contact (BEC) dielectric; 401 — Magnetic Tunnel Junction (MTJ) multilayer film including a seed layer; 402-top hard mask; 403-dielectric capping layer; 501-Top Electrode Via (TEV) dielectric; 502-Top Electrode Via (TEV); 503-Top Electrode Via (TEV) fill diffusion barrier; 504-Top Electrode Via (TEV) fill; 601-Metal line (M)x+1(x>1) etching the barrier layer; 602-Metal line (M)x+1(x>1)) a dielectric; 603-Metal line (M)x+1(x>1) a diffusion barrier layer; 604-Metal lines (M)x+1(x>＝1))。
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. It is to be noted that the drawings are in simplified form and are not to precise scale, which is provided for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The invention provides a method for manufacturing a magnetic random access memory unit array and a peripheral circuit connecting line, which comprises the steps of carrying out manufacturing process and alignment mode of a magnetic random access memory and a peripheral logic circuit thereof between two layers of metal; in the storage region, metal connection (M) is adoptedx) Sequentially manufacturing a bottom electrode through hole (BEV), a Bottom Electrode Contact (BEC), a magnetic tunnel junction structure unit (MTJ) and a top electrode through hole (TEV); in the logic circuit area, the top electrode through hole (TEV) and the Bottom Electrode Contact (BEC) are directly connected, and finally, a layer of metal connecting wire (M) is manufactured on the top electrode through hole (TEV)x+1) To enable connection between the magnetic random access memory logic area and the storage area. Thus, BEV, BEC, MTJ and TEV are aligned in sequence in the memory region, and BEV, BEC and TEV are aligned in sequence in the memory region. The present invention includes, but is not limited to, the fabrication of Magnetic Random Access Memories (MRAMs), and is not limited to any process sequence or flow, as long as the resulting product or device is prepared by the same or similar method as that prepared by the following preferred process sequence or flow, with the following specific steps:
step 1: metal-coated wiring (M) providing surface finishx(x>1) and Bottom Electrode Via (BEV)203 is fabricated thereon, followed by filling of metallic copper using a standard Single Damascene (SD) process.
Further, the above step 1 may be divided into the following forming steps:
step 1.1: a diffusion barrier layer 201 and a bottom electrode via dielectric 202 are deposited on the CMOS substrate 100 as shown in fig. 1(a), wherein the diffusion barrier layer 201 can be used as a barrier metal line (M)x) The diffusion protection layer of the middle copper towards the bottom electrode through hole dielectric 202 can also be used as an etching barrier layer for etching the bottom electrode through hole 203, the thickness of the diffusion barrier layer 201 is 10 nm-50 nm, and the forming material can be SiN, SiC or SiCN and the like; the bottom electrode via dielectric 202 has a thickness of 60nm to 200 nmnm, the forming material can be SiO2SiON, low-k, etc.
The low dielectric constant (low-k) dielectric refers to a material having a dielectric constant (k) lower than that of silicon dioxide (k is 3.9), and in the specific implementation, the low-k material may be a hydrosilicate (HSQ, k is 2.8-3.0) containing Si — CH3Functional group-containing methylsiliconate (MSQ, k is 2.5-2.7), Hybrid organosiloxane Polymer (HOSP) film (k is 2.5) synthesized by combining Hydrosiliconate (HSQ) and Methylsiliconate (MSQ), porous SiOCH film (k is 2.3-2.7), and ultra-low dielectric constant (k is 2.5) can be used<2.0) Porous Silicate, and a Porous SiOCH film having a dielectric constant (k) of 1.9.
Step 1.2: the memory region and the logic region are patterned to define a Bottom Electrode Via (BEV)203 pattern, and the Bottom Electrode Via (BEV)203 pattern is etched to form, as shown in fig. 1(b), and after etching, a dry process and/or a wet cleaning process is generally used to remove the residual polymer.
Step 1.3: the bottom electrode via fill 205 is formed by filling copper metal into the Bottom Electrode Via (BEV)203 by electroplating and planarizing by Chemical Mechanical Polishing (CMP), as shown in fig. 1(c), wherein a Ti/TiN or Ta/TaN diffusion barrier layer 204 and a copper seed layer are typically deposited in advance before electroplating copper.
Step 2: making a Bottom Electrode Contact (BEC) 302; the Bottom Electrode Contact (BEC)302 may be Ta, TaN, Ti, TiN, W, WN, or the like, and a Ta or TaN etching hard mask layer (not shown) is typically grown thereon.
Further, the step 2 may be divided into the following forming steps:
step 2.1: as shown in fig. 2(a), the Bottom Electrode Contact (BEC) metal layer 301 is deposited, wherein the Bottom Electrode Contact (BEC) metal layer 301 is 20nm to 80nm, and may be deposited by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or Ion Beam Deposition (IBD).
Step 2.2: the Bottom Electrode Contact (BEC)302 is patterned to be aligned with the Bottom Electrode Via (BEV)203, and the bottom electrode contact 302 is formed by an Etching process, which may be implemented by Reactive Ion Etching (RIE) or Ion Beam Etching (IBE), and after Etching, a cleaning process is used to remove residual polymer, etc.
Wherein, IBE mainly adopts Ar, Kr or Xe and the like as an ion source; mainly using Cl for RIE2Or CF4Etc. as the main etching gas.
Step 2.3: the Bottom Electrode Contact (BEC) dielectric 303 is filled and planarized using a planarization process down to the top of the Bottom Electrode Contact (BEC)302 as shown in fig. 2 (b). Wherein the Bottom Electrode Contact (BEC) dielectric 303 is SiO2SiON, low-k, or the like.
And step 3: in the storage region, a magnetic tunnel junction structure cell (MTJ) is fabricated that includes a seed layer on the bottom and a hard mask layer on the top.
Further, the step 3 may be divided into the following forming steps:
step 3.1: on the planarized Bottom Electrode Contact (BEC)302, a seed layer, a magnetic tunnel junction multilayer film 401, and a top hard mask 402 are sequentially formed as shown in fig. 3 (a).
The total thickness of the Magnetic Tunnel Junction (MTJ) multilayer film is 15 nm-40 nm, and the MTJ multilayer film can be a Bottom Pin structure formed by sequentially and upwardly superposing a reference layer, a barrier layer and a memory layer or a Top Pin structure formed by sequentially and upwardly superposing a memory layer, a barrier layer and a reference layer.
Further, the reference layer has a magnetic polarization invariance that differs depending on whether it is an in-plane (iST-MRAM) or perpendicular (pSTT-MRAM) structure. The reference layer of in-plane (iSTT-MRAM) typically has a (IrMn or PtMn)/CoFe/Ru/CoFe/CoFeB structure with a preferred total thickness of 10-30 nm; the reference layer of the vertical type (pSTT-MRAM) generally has a TbCoFe or [ Co/Pt ]/Co/Ru/[ CoPt ]/CoFeB superlattice multilayer film structure, and a seed layer, such as Ta/Pt, is generally required below, and the total thickness of the reference layer is preferably 8-20 nm.
Further, the barrier layer is a non-magnetic metal oxide, preferably MgO, MgZnO or Al2O3The thickness is 0.5 nm-3 nm.
Further, a double-layered MgO structure may be employed.
Further, the memory layer has a variable magnetic polarization that differs depending on whether it is an in-plane (iST-MRAM) or perpendicular (pSTT-MRAM) structure. The memory layer of the in-plane iSTT-MRAM is generally CoFe/CoFeB or CoFe/NiFe, and the thickness is preferably 2nm to 6nm, and the memory layer of the vertical pSTT-MRAM is generally CoFeB, CoFe/CoFeB, Fe/CoFeB, CoFeB/(Ta, W, Mo)/CoFeB, and the thickness is preferably 0.8nm to 2 nm.
The top hard mask 402 has a thickness of 20nm to 100nm, and Ta, TaN, W, WN, etc. are selected to achieve better profile in a halogen plasma.
Step 3.2: defining a magnetic tunnel junction pattern in a graphical manner, and etching the top electrode, the magnetic tunnel junction multilayer film 401 and the bottom electrode, as shown in fig. 3 (b);
in this process, the definition of the magnetic tunnel junction and the Reactive Ion (RIE) etching of the top hard mask 402 are accomplished using one lithography-etching (LE) or two lithography-etching (LELE), and simultaneously the RIE process is used to remove the residual polymer to transfer the pattern to the top of the magnetic tunnel junction.
Finishing the Etching of the magnetic tunnel junction and the bottom electrode by adopting a Reactive Ion Etching (RIE) method and/or an Ion Beam Etching (IBE) method;
wherein, IBE mainly adopts Ar, Kr or Xe and the like as an ion source; for RIE, CF is mainly used4、CF3H、Cl2Etc. as the main etching gas of the hard mask, mainly CH is used3OH、CH4/Ar、C2H5OH、CH3OH/Ar or CO/NH3Etc. as the main etching gas of the magnetic tunnel junction multilayer film.
Step 3.3: depositing a dielectric capping layer 403 around the magnetic tunnel junction multilayer film 401 and the top hard mask 402 and covering the entire etched area, including the top hard mask layer; as shown in FIG. 3 (c); the dielectric cap Layer 403 is made of SiC, SiN, or SiCN, and the forming method thereof can be implemented by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or Ion Beam Deposition (IBD).
And 4, step 4: manufacturing a Top Electrode through hole (TEV, Top Electrode Via) and a metal connecting line (M) for realizing the connection of a logic unit/a storage unitx+1)604. In this step, a double Single Damascene (SD) or a Double Damascene (DD) process may be used.
The first embodiment is as follows: the double Single Damascene (SD) process includes the following steps:
step 4.1.1: on the dielectric cap 403, a top electrode via dielectric 501 is deposited and a planarization process is used to polish the Top Electrode Via (TEV) dielectric 501, as shown in FIG. 4 (a); the Top Electrode Via (TEV) dielectric 501 is SiO2SiON or low-k, the thickness of which is 120nm to 400 nm;
step 4.1.2: a Top Electrode Via (TEV)502 is defined graphically and formed using an etching process to connect to the bottom electrode via fill 205 in the logic region and to the top hard mask 402 in the memory region, typically using a cleaning process to remove the polymer after etching, as shown in fig. 4 (b);
step 4.1.3: the fill metal forms a top electrode via fill 504 and is planarized using Chemical Mechanical Polishing (CMP), as shown in fig. 4 (c); wherein a Ti/TiN or Ta/TaN diffusion barrier layer 503 and a copper seed layer are typically deposited in advance before Electroplating (ECP) copper.
Step 4.1.4: depositing metal connecting line (M)x+1) A dielectric 602, patterned to define and etch metal wiring trenches connecting the logic and memory regions, electroplated copper into the wiring trenches, and planarized using chemical mechanical polishing to form metal lines (M) connecting the logic and memory regionsx+1)604, as shown in FIG. 4 (d); wherein, the metal connecting line (M)x+1) The dielectric 602 has a thickness of 50 nm-300 nm and is made of SiO2SiON or low-k, etc., typically before deposition, an etch stop layer 601 of several tens of nanometers thick is deposited, which is made of SiN, SiC or SiCN, etc.; a Ta/TaN diffusion barrier layer 603 and a copper seed layer are deposited in advance before electroplating copper.
The second embodiment: a disposable Dual Damascene (DD) process, as shown in fig. 5; the method comprises the following steps:
step 4.2.1: on the dielectric cap 403, a top electrode via dielectric 501 is deposited, and a planarization process is used to polish the Top Electrode Via (TEV) dielectric 501 and deposit a metal line (M)x+1) A dielectric 602; the Top Electrode Via (TEV) dielectric 501 is SiO2SiON or low-k, the thickness of which is 120nm to 400 nm; metal connecting wire (M)x+1) The dielectric 602 has a thickness of 50 nm-300 nm and is made of SiO2SiON or low-k, etc., typically before deposition, an etch stop layer 601 of several tens of nanometers thick is deposited, which is made of SiN, SiC or SiCN, etc.;
step 4.2.2: a Top Electrode Via (TEV)502 and a metal wiring trench connecting the logic area and the memory area are defined graphically and formed using an etching process, the top electrode via 502 is connected to the bottom electrode contact 302 in the logic area, the top electrode via 502 is connected to the top hard mask 402 in the memory area, and typically, the polymer is removed using a cleaning process after etching;
step 4.2.3: electroplating fill metal to form top electrode via fill 504 and metal line (M)x+1)604, and polishing by chemical mechanical polishing; wherein a Ta/TaN diffusion barrier layer 503 and a copper seed layer are typically deposited in advance prior to electroplating copper.
The foregoing detailed description of the preferred embodiments of the invention has been presented. It should be understood that numerous modifications and variations could be devised by those skilled in the art in light of the present teachings without departing from the inventive concepts. Therefore, the technical solutions available to those skilled in the art through logic analysis, reasoning and limited experiments based on the prior art according to the concept of the present invention should be within the scope of protection defined by the claims.
Claims (10)
1. A method for manufacturing a magnetic random access memory cell array and a peripheral circuit connecting line is characterized by comprising the following steps:
step 1: providing a CMOS substrate with a polished surface and a metal connecting wire, manufacturing a bottom electrode through hole on the substrate, and then filling metal in the bottom electrode through hole;
step 2: making a bottom electrode contact on the bottom electrode through hole;
and step 3: manufacturing a magnetic tunnel junction structure unit on the bottom electrode contact;
and 4, step 4: manufacturing a top electrode through hole and a metal connecting line for realizing the connection of a logic unit/a storage unit on the magnetic tunnel junction structure unit;
wherein the step 1 comprises the following steps:
step 1.1: depositing a diffusion barrier layer and a bottom electrode through hole dielectric on the CMOS substrate, wherein the diffusion barrier layer can be used as a diffusion protection layer for blocking copper in a metal connecting line from being towards the bottom electrode through hole dielectric, and can also be used as an etching barrier layer for etching the bottom electrode through hole;
step 1.2: simultaneously defining a bottom electrode through hole pattern in a graphical manner in the storage area and the logic area, and etching to form a bottom electrode through hole;
step 1.3: and filling metal copper into the bottom electrode through hole by adopting an electroplating method, and polishing and grinding by adopting chemical machinery to form bottom electrode through hole filling.
2. The method of claim 1, wherein the step 2 comprises the following steps:
step 2.1: depositing a bottom electrode contact metal;
step 2.2: defining a bottom electrode contact pattern in a graphical mode to enable the bottom electrode contact pattern to be aligned with the bottom electrode through hole, etching the bottom electrode contact metal to form a bottom electrode contact, and removing residual impurities after etching;
step 2.3: and filling a bottom electrode contact dielectric in the etched gap, and flattening the top of the bottom electrode contact dielectric until the top of the bottom electrode contact dielectric is flush with the top of the bottom electrode contact.
3. The method as claimed in claim 2, wherein the bottom electrode contact metal is selected from Ta, TaN, Ti, TiN, W or WN.
4. The method as claimed in claim 2, wherein the bottom electrode contact metal is deposited to a thickness of 20nm to 80 nm.
5. The method of claim 2, wherein the bottom electrode contact metal is deposited by one of chemical vapor deposition, physical vapor deposition, atomic layer deposition, or ion beam deposition.
6. The method of claim 2, wherein the etching is performed by ion beam etching.
7. The method of claim 2, wherein the bottom electrode contact dielectric is SiO2SiON or a low dielectric constant dielectric, which means a dielectric constant lower than SiO2The material of (1).
8. The method as claimed in claim 1, wherein the step 3 of forming the MTJ structure unit comprises forming a MTJ multilayer film and a hard mask.
9. The method as claimed in claim 8, wherein a seed layer or an etch stop layer is deposited under the MTJ multilayer film.
10. The method of claim 1, wherein step 4 comprises performing two single damascene or one dual damascene processes to form the metal interconnects.
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