CN102376651A - Method for improving capacity of filling dielectric medium between magnetic tunnel junction (MTJ) metals in magnetic random access memory (MRAM) - Google Patents

Method for improving capacity of filling dielectric medium between magnetic tunnel junction (MTJ) metals in magnetic random access memory (MRAM) Download PDF

Info

Publication number
CN102376651A
CN102376651A CN2010102615178A CN201010261517A CN102376651A CN 102376651 A CN102376651 A CN 102376651A CN 2010102615178 A CN2010102615178 A CN 2010102615178A CN 201010261517 A CN201010261517 A CN 201010261517A CN 102376651 A CN102376651 A CN 102376651A
Authority
CN
China
Prior art keywords
mtj
mram
layer
inter
magnetic memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2010102615178A
Other languages
Chinese (zh)
Other versions
CN102376651B (en
Inventor
吴金刚
倪景华
于书坤
李锦�
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201010261517.8A priority Critical patent/CN102376651B/en
Publication of CN102376651A publication Critical patent/CN102376651A/en
Application granted granted Critical
Publication of CN102376651B publication Critical patent/CN102376651B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)

Abstract

The invention discloses a method for improving capacity of filling a dielectric medium between magnetic tunnel junction (MTJ) metals in a magnetic random access memory (MRAM). In the method, by etching an MTJ unit film into a wedge and depositing an MTJ protective etching barrier layer on the wedge, and by further removing a convex suspended structure from the MTJ protective etching barrier layer by using a re-etching method, IMD can be uniformly filled during sequent deposition of the IMD, so that the generation of a cavity is avoided; the method is not required to be carried out under a high-temperature condition, so that the attenuation of the MTJ caused by high temperature is avoided and the performance of the MRAM is improved.

Description

Improve the method for the filling capacity of the MTJ inter-metal dielectric among the MRAM
Technical field
The present invention relates to magnetic random reference to storage (MRAM) technical field, relate in particular to the method for the filling capacity of the MTJ inter-metal dielectric among a kind of MRAM of raising.
Background technology
Magnetic random reference to storage (MRAM, Magnetic Random Access Memory) is a kind of nonvolatile memory, and so-called " non-volatile " still can keep remembering complete after being meant and turning off power supply.At aspect of performance, the high speed that MRAM has static random access memory (SRAM) reads write capability, and the high integration of dynamic random access memory (DRAM), and can repeat to write basically unlimitedly, is the solid-state memory of a kind of " global function ".Thereby its application prospect is considerable, is expected to leading storage market of future generation.
MRAM generally comprises peripheral drive circuit and a plurality of magnetic memory cell, and said magnetic memory cell is made up of a break-through transistor and a magnetoresistive tunnel junction (MTJ, Magnetic Tunnel Junction).And; For compatible mutually with CMOS integrated circuit preparation technology, as a rule, said MTJ is inserted between the two metal layers of CMOS integrated circuit; For example be inserted between ground floor metal level and the second layer metal layer, link to each other through metal throuth hole (via) between the said two metal layers.
Yet because MRAM is writing the bigger drive current of fashionable needs, this point has all produced adverse effect to reducing cell size, isolate peripheral circuit and reducing power consumption.A method that reduces drive current is the size that reduces MTJ.But when the size of MTJ is also littler than the size of last layer via; Can make when etching last layer via; Should when etching into MTJ, stop etching; But exceed the part continuation etching of MTJ, cause the metal level short circuit of last layer via and following one deck, thereby have a strong impact on the performance of MRAM along last layer via.
In order to solve the metal level problem of short-circuit of last layer via and following one deck; Proposition covers the layer of protecting etching barrier layer on MTJ; Thereby avoid the over etching short circuit problem; This protection etching barrier layer is the silicon carbide layer (NDC, Nitrogen Dopped Silicon Carbite) that silicon nitride layer (SiN) or nitrogen mix.Yet; Because the MTJ among the MRAM has high pattern density (pattern density) and high aspect ratio (aspectratio); Make SiN or NDC in overwrite procedure, have serious protruding outstanding (overhang) phenomenon; Thereby make when deposit MTJ intermetallic dielectric layer (IMD, Inter-Metal Dielectric) next, to be easy to generate cavity (void) problem, cause short circuit.Please refer to Fig. 1 about protruding outstanding phenomenon, Fig. 1 is the sketch map of the protruding outstanding phenomenon that the covering protection etching barrier layer exists on MTJ, and is as shown in Figure 1; When deposition protection etching barrier layer 106 on MTJ103, because the pattern density of MTJ103 is big, promptly the interval between two MTJ103 is little; Simultaneously because the figure of MTJ103 has high aspect ratio, and protection etching barrier layer 106 in the deposition rate at MTJ top greater than deposition rate at sidewall, cause protection etching barrier layer 106 at the thickness at the top of MTJ103 much larger than its thickness at sidewall; Thereby outstanding to the side, form protruding outstanding phenomenon, make at dielectric layer (IMD between depositing metal next; Inter-Metal Dielectric) time; Part IMD between two MTJ103 fills not enter, and produces cavity (void), possibly cause short circuit.Wherein, this MTJ103 is prepared on the ground floor metal level 101, isolates through insulating medium layer 102 between the ground floor metal level 101, and said insulating medium layer 102 is the silica of carbon dope; And also deposited one deck cap layer (capping layer) 105 on the top of said MTJ103; Also deposited one deck inculating crystal layer (seed layer) 104 in the bottom of said MTJ103, said MTJ protection etching barrier layer 106 is deposited on the said cap layer (cappinglayer) 105.Said cap layer (capping layer) 105 is an electric conducting material with said inculating crystal layer (seed layer) 104, and MTJ103 is protected in acting as of said cap layer (capping layer) 105, and MTJ103 is contacted better with last layer via; Said inculating crystal layer (seed layer) 104 helps the MTJ103 film evenly grows, and MTJ103 is contacted better with said ground floor metal level 101.
Therefore, how to improve the filling capacity of the IMD among the MTJ, make it not produce the cavity, become a very crucial problem.
In order to address this problem, existing a kind of method is to improve the depositing temperature of IMD, yet the preparation temperature of MRAM must not surpass 350 ℃, and this is because after temperature surpassed 350 ℃, the magnetic of MTJ can decay, thereby has a strong impact on the performance of MRAM.
Existing another kind of method is to adopt high-density plasma (HDP, High Density Plasma) chemical vapor deposition (CVD) technology to deposit IMD, and the IMD that this method forms has higher filling capacity, can avoid IMD cavity problem effectively.But there is following problem in HDP CVD:
(1) in HDP CVD, the IMD dielectric layer of high filling capacity needs at high temperature to form usually, and temperature is general above 400 ℃, and the preparation temperature of MRAM must not be above 350 ℃;
(2) concerning 12 inches semiconductor plants; Its last part technology adopts damascene structure (damascene) usually; There is not the IMD filling step in this technology, thereby does not have the HDP instrument, therefore if in the preparation process of MRAM, introduce HDP CVD; Some technological process control problems will be caused, and the preparation cost of MRAM can be increased greatly.
Therefore, how be lower than under 350 ℃ the temperature, improving the filling capacity of the IMD among the MTJ, making it not produce the cavity, becoming the technical problem that present industry is needed solution badly.
Summary of the invention
The object of the present invention is to provide the method for the filling capacity of the MTJ inter-metal dielectric among a kind of MRAM of raising; Method with the filling capacity that solves the MTJ inter-metal dielectric among the existing raising MRAM needs hot conditions usually; And after temperature surpasses 350 ℃; The magnetic of MTJ can decay, thereby has a strong impact on the problem of the performance of MRAM.
For addressing the above problem; The present invention proposes the method for the filling capacity of the MTJ inter-metal dielectric among a kind of MRAM of raising; Wherein said MRAM comprises the MTJ magnetic memory cell; Said MTJ magnetic memory cell is deposited between the first metal layer and second metal level of integrated circuit, and said the first metal layer comprises a plurality of first metals and isolate the dielectric layer of said a plurality of first metals that this method comprises the steps:
(100) deposition MTJ unit membrane on said the first metal layer;
(200) said MTJ unit membrane is carried out photoetching and etching, form a plurality of wedge shape MTJ magnetic memory cells;
(300) deposition MTJ protection etching barrier layer, post-depositional said MTJ protection etching barrier layer has protruding outstanding structure;
(400) said MTJ protection etching barrier layer is eat-back, remove said protruding outstanding structure, and the side wall thicknesses of said MTJ protection etching barrier layer is first thickness after eat-backing;
(500) deposition IMD; And
(600) said IMD is carried out photoetching and etching, form the through hole and second metal level.
Optional, the side of each the wedge shape MTJ magnetic memory cell in said a plurality of wedge shape MTJ magnetic memory cells and the angle of bottom surface are 68 °~85 °.
Optional, the side of said each wedge shape MTJ magnetic memory cell and the angle of bottom surface are 75 °~80 °.
Optional, the process conditions of said step (400) are:
Gas flow: CHF 3, 10~50sccm; O 2, 5~50sccm; Ar, 0~1000sccm;
Power: 0~400W;
Pressure: 5~60mTorr.
Optional, said first thickness exceeds the peak excursion value d of said wedge shape MTJ magnetic memory cell greater than said through hole Max
Optional, said d Max=d 1+ d 2+ d 3+ d 4, wherein, d 1For the domain critical size of through hole exceeds the size of the domain critical size of wedge shape MTJ magnetic memory cell, d 2Poor for the domain standard critical size of the upper limit of the actual process critical size of through hole and through hole, d 3Poor for the actual process critical size lower limit of the domain standard critical size of wedge shape MTJ magnetic memory cell and wedge shape MTJ magnetic memory cell, d 4The poorest alignment precision during for exposure between through hole and the wedge shape MTJ magnetic memory cell.
Optional, the temperature of said deposition IMD is less than 350 ℃.
Optional, the material of said IMD is the silica of carbon dope or cryogenic oxidation silicon or the low temperature TEOS for preparing based on SiH4.
Optional, said MTJ magnetic memory cell comprises inculating crystal layer, is positioned at the MTJ main body on the said inculating crystal layer and is positioned at the cap layer on the said MTJ main body.
Optional, the material of said cap layer is an electric conducting material.
Optional, the material of said cap layer is one or more among Ta or Pt or Co or Fe or Ru or Al or W or Ti or TiN or TaN or Ni or the NiFe.
Optional, the material of said inculating crystal layer is an electric conducting material.
Optional, the material of said inculating crystal layer is one or more among Ta or Pt or Co or Fe or Ru or Al or W or Ti or TiN or TaN or Ni or the NiFe.
Optional, said MTJ protection etching barrier layer is the silicon carbide layer that silicon nitride layer or nitrogen mix.
The present invention makes it compared with prior art owing to adopt above technical scheme, has following advantage and good effect:
(1) the present invention makes that through the MTJ unit membrane is etched into wedge shape the said MTJ protection of deposition etching barrier layer becomes relatively easy on the sidewall of said wedge shape MTJ magnetic memory cell; And further through the method for eat-backing, the protruding outstanding structure of said MTJ protection etching barrier layer is removed, thereby made IMD be easy to even filling, avoided empty generation;
(2) adopt method provided by the invention to prepare MRAM, do not need hot conditions, thereby help improving the performance of MRAM;
(3) adopt method provided by the invention to prepare MRAM, the feasible through hole that contacts with said wedge shape MTJ magnetic memory cell and the through hole of peripheral drive circuit can carry out etching simultaneously, thereby have saved a mask, have reduced cost.
Description of drawings
Fig. 1 is the sketch map of the protruding outstanding phenomenon that the covering protection etching barrier layer exists on MTJ;
The flow chart of steps of the method for the filling capacity of the MTJ inter-metal dielectric among the raising MRAM that Fig. 2 provides for the embodiment of the invention;
The structural representation that on said the first metal layer, deposits the MTJ unit membrane that Fig. 3 provides for the embodiment of the invention;
Fig. 4 carries out the structural representation after the etching for what the embodiment of the invention provided to said MTJ unit membrane;
Structural representation behind the deposition MTJ protection etching barrier layer that Fig. 5 embodiment of the invention provides;
Fig. 6 protects the structural representation after etching barrier layer eat-backs for what the embodiment of the invention provided to said MTJ;
Structural representation behind the deposition IMD that Fig. 7 provides for the embodiment of the invention;
Formation through hole that Fig. 8 provides for the embodiment of the invention and the structural representation behind second metal level.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the method for the filling capacity of the MTJ inter-metal dielectric among the raising MRAM of the present invention's proposition is done further explain.According to following explanation and claims, advantage of the present invention and characteristic will be clearer.What need explanation is, accompanying drawing all adopts the form of simplifying very much and all uses non-ratio accurately, only is used for conveniently, the purpose of the aid illustration embodiment of the invention lucidly.
Core concept of the present invention is; The method of the filling capacity of the MTJ inter-metal dielectric among a kind of MRAM of raising is provided, and this method deposits MTJ protection etching barrier layer above that again after the MTJ unit membrane being etched into wedge shape, and further through the method for eat-backing the protruding outstanding structure of said MTJ protection etching barrier layer is removed; Thereby when making subsequent deposition IMD; IMD can fill equably, thereby has avoided empty generation, and owing to this method need not carried out under hot conditions; Thereby avoided high temperature to the decline that MTJ causes, improved the performance of MRAM.
Please refer to Fig. 2; The flow chart of steps of the method for the filling capacity of the MTJ inter-metal dielectric among the raising MRAM that Fig. 2 provides for the embodiment of the invention; As shown in Figure 2, the method for the filling capacity of the MTJ inter-metal dielectric among the raising MRAM that the embodiment of the invention provides comprises the steps:
(100) deposition MTJ unit membrane on said the first metal layer; Please refer to Fig. 3 about this step; The structural representation that on said the first metal layer, deposits the MTJ unit membrane that Fig. 3 provides for the embodiment of the invention; As shown in Figure 3, said MTJ unit membrane comprises inculating crystal layer 203, is positioned at the MTJ main body 204 on the said inculating crystal layer 203 and is positioned at the cap layer 205 on the said MTJ main body 204; And said MTJ unit membrane is deposited on the first metal layer, and said the first metal layer comprises a plurality of first metals 201 and isolates the dielectric layer 202 of said a plurality of first metals 201;
(200) said MTJ unit membrane is carried out photoetching and etching, form a plurality of wedge shape MTJ magnetic memory cells; Please refer to Fig. 4 about this step; Wherein Fig. 4 carries out the structural representation after the etching for what the embodiment of the invention provided to said MTJ unit membrane; As shown in Figure 4; After said MTJ unit membrane carries out photoetching and etching, form a plurality of wedge shape MTJ magnetic memory cells (only having illustrated two among this figure), the side of said each wedge shape MTJ magnetic memory cell and the angle of bottom surface are θ;
(300) deposition MTJ protection etching barrier layer, post-depositional said MTJ protection etching barrier layer has protruding outstanding structure; About this step, please refer to Fig. 5, the structural representation behind the deposition MTJ protection etching barrier layer that Fig. 5 embodiment of the invention provides, as shown in Figure 5, post-depositional said MTJ protection etching barrier layer 206 has protruding outstanding structure;
(400) said MTJ protection etching barrier layer is eat-back, remove said protruding outstanding structure, and the side wall thicknesses of said MTJ protection etching barrier layer is first thickness after eat-backing; Please refer to Fig. 6 about this step; Fig. 6 protects the structural representation after etching barrier layer eat-backs for what the embodiment of the invention provided to said MTJ; As shown in Figure 6; After eat-backing, the protruding outstanding structure of said MTJ protection etching barrier layer 206 is removed, and the side wall thicknesses of said MTJ protection etching barrier layer 206 is first thickness d after eat-backing;
(500) deposition IMD; Please refer to Fig. 7 about this step, the structural representation behind the deposition IMD that Fig. 7 provides for the embodiment of the invention, as shown in Figure 7, through after eat-backing, IMD207 can be deposited on the said MTJ protection etching barrier layer 206 equably, does not have cavitation; And
(600) said IMD is carried out photoetching and etching, form the through hole and second metal level; Please refer to Fig. 8 about this step; Formation through hole that Fig. 8 provides for the embodiment of the invention and the structural representation behind second metal level; As shown in Figure 8; Between first metal 201 and second metal 209 in second metal level of said wedge shape MTJ magnetic memory cell in said the first metal layer; Owing on said wedge shape MTJ magnetic memory cell, deposited MTJ protection etching barrier layer 206, thereby 208 of said through holes etch into till the said wedge shape MTJ magnetic memory cell, have prevented that said through hole 208 from directly touching MTJ main body 204 with 201 short circuits of said first metal or through hole 208 and causing short circuit and pollution.
Further; The side of each the wedge shape MTJ magnetic memory cell in said a plurality of wedge shape MTJ magnetic memory cell and the angle theta of bottom surface are 68 °~85 °; Preferably; The side of said each wedge shape MTJ magnetic memory cell and the angle theta of bottom surface are 75 °~80 °, thereby make said MTJ protection etching barrier layer 206 can be deposited on the sidewall of said wedge shape MTJ magnetic memory cell preferably.
Further, the process conditions of said step (400) are:
Gas flow: CHF 3, 10~50sccm; O 2, 5~50sccm; Ar, 0~1000sccm;
Power: 0~400W;
Pressure: 5~60mTorr.
Further, said first thickness d exceeds the peak excursion value d of said wedge shape MTJ magnetic memory cell greater than said through hole 208 MaxThereby prevent to cause damage to said wedge shape MTJ magnetic memory cell in the etch back process; And avoid in the etching process of ensuing through hole 208, causing through hole 208 over etchings, cause that said through hole 208 directly touches MTJ main body 204 with 201 short circuits of said first metal or through hole 208 and causes short circuit and pollution.
Further, said d Max=d 1+ d 2+ d 3+ d 4, wherein, d 1For the domain critical size of through hole 208 exceeds the size of the domain critical size of wedge shape MTJ magnetic memory cell, d 2Poor for the domain standard critical size of the upper limit of the actual process critical size of through hole 208 and through hole 208, d 3Poor for the actual process critical size lower limit of the domain standard critical size of wedge shape MTJ magnetic memory cell and wedge shape MTJ magnetic memory cell, d 4For when exposure through hole 208 and wedge shape MTJ magnetic memory cell between the poorest alignment precision, thereby comprised the full-size of all predictable process deviations.
Further, the temperature of said deposition IMD207 is less than 350 ℃, thereby can not cause the magnetic decline to MTJ main body 204.
Further, the material of said IMD207 is the silica of carbon dope or cryogenic oxidation silicon or the low temperature TEOS for preparing based on SiH4, thereby can under relatively low temperature, form, and avoids in its forming process, MTJ main body 204 being caused the magnetic decline.
Further, the material of said cap layer 205 is an electric conducting material, thereby it is contacted better with said through hole 208.
Further, the material of said cap layer 205 is one or more among Ta or Pt or Co or Fe or Ru or Al or W or Ti or TiN or TaN or Ni or the NiFe.
Can be further, the material of said inculating crystal layer 203 is an electric conducting material, thereby it is contacted better with said first metal 201.
Further, the material of said inculating crystal layer 203 is one or more among Ta or Pt or Co or Fe or Ru or Al or W or Ti or TiN or TaN or Ni or the NiFe.
Further, said MTJ protection etching barrier layer 206 is the silicon carbide layer that silicon nitride layer or nitrogen mix.
In a specific embodiment of the present invention; Said MTJ magnetic memory cell is formed between said the first metal layer and said second metal level; Yet should be realized that; According to actual conditions, said MTJ magnetic memory cell can also be formed between other the two-layer adjacent metal in the integrated circuit, between three-layer metal layer and the 4th layer of metal level.
In a specific embodiment of the present invention, the reacting gas that adopts in the said step (400) is CHF 3And O 2Yet, should be realized that, according to actual conditions, said CHF 3Can adopt CF 4Or CH 2F 2Substitute said O 2Can adopt CO 2Or CO substitutes.
In sum; The invention provides the method for the filling capacity of the MTJ inter-metal dielectric among a kind of MRAM of raising, this method deposits MTJ protection etching barrier layer above that again after the MTJ unit membrane being etched into wedge shape, and further through the method for eat-backing the protruding outstanding structure of said MTJ protection etching barrier layer is removed; Thereby when making subsequent deposition IMD; IMD can fill equably, thereby has avoided empty generation, and owing to this method need not carried out under hot conditions; Thereby avoided high temperature to the decline that MTJ causes, improved the performance of MRAM.
Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.

Claims (14)

1. method that improves the filling capacity of the MTJ inter-metal dielectric among the MRAM; Wherein, Said MRAM comprises the MTJ magnetic memory cell, and said MTJ magnetic memory cell is deposited between the first metal layer and second metal level of integrated circuit, and said the first metal layer comprises a plurality of first metals and isolates the dielectric layer of said a plurality of first metals; It is characterized in that this method comprises the steps:
(100) deposition MTJ unit membrane on said the first metal layer;
(200) said MTJ unit membrane is carried out photoetching and etching, form a plurality of wedge shape MTJ magnetic memory cells;
(300) deposition MTJ protection etching barrier layer, post-depositional said MTJ protection etching barrier layer has protruding outstanding structure;
(400) said MTJ protection etching barrier layer is eat-back, remove said protruding outstanding structure, and the side wall thicknesses of said MTJ protection etching barrier layer is first thickness after eat-backing;
(500) deposition IMD; And
(600) said IMD is carried out photoetching and etching, form the through hole and second metal level.
2. the method for the filling capacity of the MTJ inter-metal dielectric among the raising MRAM as claimed in claim 1; It is characterized in that the side of each the wedge shape MTJ magnetic memory cell in said a plurality of wedge shape MTJ magnetic memory cells and the angle of bottom surface are 68 °~85 °.
3. the method for the filling capacity of the MTJ inter-metal dielectric among the raising MRAM as claimed in claim 2 is characterized in that the side of said each wedge shape MTJ magnetic memory cell and the angle of bottom surface are 75 °~80 °.
4. the method for the filling capacity of the MTJ inter-metal dielectric among the raising MRAM as claimed in claim 1 is characterized in that the process conditions of said step (400) are:
Gas flow: CHF 3, 10~50sccm; O 2, 5~50sccm; Ar, 0~1000sccm;
Power: 0~400W;
Pressure: 5~60mTorr.
5. the method for the filling capacity of the MTJ inter-metal dielectric among the raising MRAM as claimed in claim 1 is characterized in that said first thickness exceeds the peak excursion value d of said wedge shape MTJ magnetic memory cell greater than said through hole Max
6. the method for the filling capacity of the MTJ inter-metal dielectric among the raising MRAM as claimed in claim 5 is characterized in that said d Max=d 1+ d 2+ d 3+ d 4, wherein, d 1For the domain critical size of through hole exceeds the size of the domain critical size of wedge shape MTJ magnetic memory cell, d 2Poor for the domain standard critical size of the upper limit of the actual process critical size of through hole and through hole, d 3Poor for the actual process critical size lower limit of the domain standard critical size of wedge shape MTJ magnetic memory cell and wedge shape MTJ magnetic memory cell, d 4The poorest alignment precision during for exposure between through hole and the wedge shape MTJ magnetic memory cell.
7. the method for the filling capacity of the MTJ inter-metal dielectric among the raising MRAM as claimed in claim 1 is characterized in that the temperature of said deposition IMD is less than 350 ℃.
8. the method for the filling capacity of the MTJ inter-metal dielectric among the raising as claimed in claim 7 MRAM is characterized in that, the material of said IMD is the silica of carbon dope or based on SiH 4The cryogenic oxidation silicon or the low temperature TEOS of preparation.
9. the method for the filling capacity of the MTJ inter-metal dielectric among the raising MRAM as claimed in claim 1; It is characterized in that said MTJ magnetic memory cell comprises inculating crystal layer, is positioned at the MTJ main body on the said inculating crystal layer and is positioned at the cap layer on the said MTJ main body.
10. the method for the filling capacity of the MTJ inter-metal dielectric among the raising MRAM as claimed in claim 9 is characterized in that the material of said cap layer is an electric conducting material.
11. the method for the filling capacity of the MTJ inter-metal dielectric among the raising MRAM as claimed in claim 10 is characterized in that the material of said cap layer is one or more among Ta or Pt or Co or Fe or Ru or Al or W or Ti or TiN or TaN or Ni or the NiFe.
12. the method for the filling capacity of the MTJ inter-metal dielectric among the raising MRAM as claimed in claim 9 is characterized in that the material of said inculating crystal layer is an electric conducting material.
13. the method for the filling capacity of the MTJ inter-metal dielectric among the raising MRAM as claimed in claim 12 is characterized in that the material of said inculating crystal layer is one or more among Pt or Pt or Co or Fe or Ru or Al or W or Ti or TiN or TaN or Ni or the NiFe.
14. the method for the filling capacity of the MTJ inter-metal dielectric among the raising MRAM as claimed in claim 1 is characterized in that, said MTJ protection etching barrier layer is the silicon carbide layer that silicon nitride layer or nitrogen mix.
CN201010261517.8A 2010-08-24 2010-08-24 Method for improving capacity of filling dielectric medium between magnetic tunnel junction (MTJ) metals in magnetic random access memory (MRAM) Active CN102376651B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201010261517.8A CN102376651B (en) 2010-08-24 2010-08-24 Method for improving capacity of filling dielectric medium between magnetic tunnel junction (MTJ) metals in magnetic random access memory (MRAM)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201010261517.8A CN102376651B (en) 2010-08-24 2010-08-24 Method for improving capacity of filling dielectric medium between magnetic tunnel junction (MTJ) metals in magnetic random access memory (MRAM)

Publications (2)

Publication Number Publication Date
CN102376651A true CN102376651A (en) 2012-03-14
CN102376651B CN102376651B (en) 2014-04-16

Family

ID=45795035

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201010261517.8A Active CN102376651B (en) 2010-08-24 2010-08-24 Method for improving capacity of filling dielectric medium between magnetic tunnel junction (MTJ) metals in magnetic random access memory (MRAM)

Country Status (1)

Country Link
CN (1) CN102376651B (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105336756A (en) * 2014-07-09 2016-02-17 中芯国际集成电路制造(上海)有限公司 Magnetic random access memory and manufacturing method thereof
CN107004763A (en) * 2014-12-02 2017-08-01 高通股份有限公司 Magnetic etching stopping layer for spin-transfer torque magnetic random access memory magnetic funnel node device
CN109087996A (en) * 2017-06-14 2018-12-25 上海磁宇信息科技有限公司 A method of making magnetic RAM top electrode groove
CN109087993A (en) * 2017-06-13 2018-12-25 上海磁宇信息科技有限公司 A method of making magnetic RAM top electrode hole
CN109256405A (en) * 2017-07-14 2019-01-22 中电海康集团有限公司 The production method of MRAM array and its
CN109545744A (en) * 2017-09-21 2019-03-29 上海磁宇信息科技有限公司 A kind of manufacturing method of magnetic RAM cell array and peripheral circuit line
WO2019061826A1 (en) * 2017-09-28 2019-04-04 中电海康集团有限公司 Mtj device and manufacturing method therefor, and mram
CN109994476A (en) * 2017-12-29 2019-07-09 上海磁宇信息科技有限公司 A method of preparing magnetic RAM array element
CN110739326A (en) * 2018-07-19 2020-01-31 联华电子股份有限公司 Magnetic random access memory structure
CN111816764A (en) * 2019-04-11 2020-10-23 上海磁宇信息科技有限公司 Method for preparing magnetic tunnel junction unit array

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003174215A (en) * 2001-12-07 2003-06-20 Yamaha Corp Magnetic tunnel junction element and its manufacturing method
CN1481014A (en) * 2002-09-04 2004-03-10 旺宏电子股份有限公司 Method for filling in shallow groove isolation structure with high depth-width ratio
CN101523503A (en) * 2005-09-20 2009-09-02 格兰迪斯股份有限公司 Magnetic devices having stabilized free ferromagnetic layer or multilayered free ferromagnetic layer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003174215A (en) * 2001-12-07 2003-06-20 Yamaha Corp Magnetic tunnel junction element and its manufacturing method
CN1481014A (en) * 2002-09-04 2004-03-10 旺宏电子股份有限公司 Method for filling in shallow groove isolation structure with high depth-width ratio
CN101523503A (en) * 2005-09-20 2009-09-02 格兰迪斯股份有限公司 Magnetic devices having stabilized free ferromagnetic layer or multilayered free ferromagnetic layer

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105336756B (en) * 2014-07-09 2019-11-15 中芯国际集成电路制造(上海)有限公司 Magnetic random access memory and its manufacturing method
CN105336756A (en) * 2014-07-09 2016-02-17 中芯国际集成电路制造(上海)有限公司 Magnetic random access memory and manufacturing method thereof
CN107004763A (en) * 2014-12-02 2017-08-01 高通股份有限公司 Magnetic etching stopping layer for spin-transfer torque magnetic random access memory magnetic funnel node device
CN107004763B (en) * 2014-12-02 2019-11-26 高通股份有限公司 Magnetic etching stopping layer for spin-transfer torque magnetic random access memory magnetic funnel node device
CN109087993A (en) * 2017-06-13 2018-12-25 上海磁宇信息科技有限公司 A method of making magnetic RAM top electrode hole
CN109087996A (en) * 2017-06-14 2018-12-25 上海磁宇信息科技有限公司 A method of making magnetic RAM top electrode groove
CN109256405A (en) * 2017-07-14 2019-01-22 中电海康集团有限公司 The production method of MRAM array and its
CN109545744A (en) * 2017-09-21 2019-03-29 上海磁宇信息科技有限公司 A kind of manufacturing method of magnetic RAM cell array and peripheral circuit line
CN109545744B (en) * 2017-09-21 2020-08-21 上海磁宇信息科技有限公司 Method for manufacturing magnetic random access memory unit array and peripheral circuit connecting line
WO2019061826A1 (en) * 2017-09-28 2019-04-04 中电海康集团有限公司 Mtj device and manufacturing method therefor, and mram
CN109994476A (en) * 2017-12-29 2019-07-09 上海磁宇信息科技有限公司 A method of preparing magnetic RAM array element
CN109994476B (en) * 2017-12-29 2021-03-16 上海磁宇信息科技有限公司 Method for preparing magnetic random access memory array unit
CN110739326A (en) * 2018-07-19 2020-01-31 联华电子股份有限公司 Magnetic random access memory structure
CN110739326B (en) * 2018-07-19 2022-05-24 联华电子股份有限公司 Magnetic random access memory structure
CN111816764A (en) * 2019-04-11 2020-10-23 上海磁宇信息科技有限公司 Method for preparing magnetic tunnel junction unit array
CN111816764B (en) * 2019-04-11 2024-05-28 上海磁宇信息科技有限公司 Method for preparing magnetic tunnel junction cell array

Also Published As

Publication number Publication date
CN102376651B (en) 2014-04-16

Similar Documents

Publication Publication Date Title
CN102376651B (en) Method for improving capacity of filling dielectric medium between magnetic tunnel junction (MTJ) metals in magnetic random access memory (MRAM)
CN101515566B (en) Method for forming integrated circuit
US8970213B2 (en) Method for manufacturing magnetoresistance effect element
US8907435B2 (en) Semiconductor memory and manufacturing method thereof
EP3127174A1 (en) Replacement conductive hard mask for multi-step magnetic tunnel junction (mtj) etch
US7144744B2 (en) Magnetoresistive random access memory device structures and methods for fabricating the same
US20100055804A1 (en) Method for patterning semiconductor device having magnetic tunneling junction structure
JP5107128B2 (en) Manufacturing method of semiconductor device
CN109994602A (en) A method of preparing magnetic RAM memory unit and logic unit
CN110224059A (en) Semiconductor device and forming method thereof
CN107527994B (en) Magnetic tunnel junction double-layer side wall and forming method thereof
US20200035906A1 (en) Mtj bottom metal via in a memory cell and method for producing the same
US9698342B2 (en) Contact layer for magnetic tunnel junction element and manufacturing method thereof
US6680500B1 (en) Insulating cap layer and conductive cap layer for semiconductor devices with magnetic material layers
CN103295967B (en) Manufacturing method for separated grid type flash memory embedded into logical circuit
US20090004839A1 (en) Method for fabricating an interlayer dielectric in a semiconductor device
CN107785483A (en) A kind of preparation method of magnetic RAM
CN107331769B (en) Method for selectively etching double-layer hard mask of magnetic tunnel junction by reactive ion beam
CN111668368B (en) Preparation method of pseudo-magnetic tunnel junction unit structure
CN107527993B (en) Magnetic tunnel junction contact electrode and forming method thereof
CN111952440A (en) Method of manufacturing MRAM device
CN111816764B (en) Method for preparing magnetic tunnel junction cell array
TWI839856B (en) Semiconductor device and method of forming the same
CN107546321B (en) Top electrode of magnetic random access memory and forming method thereof
CN111816224B (en) Preparation method of magnetic tunnel junction memory array unit and peripheral circuit thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHA

Effective date: 20130614

Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING

Free format text: FORMER OWNER: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION

Effective date: 20130614

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: 201203 PUDONG NEW AREA, SHANGHAI TO: 100176 DAXING, BEIJING

TA01 Transfer of patent application right

Effective date of registration: 20130614

Address after: 100176 No. 18 Wenchang Avenue, Beijing economic and Technological Development Zone

Applicant after: Semiconductor Manufacturing International (Beijing) Corporation

Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation

Address before: 201203 No. 18 Zhangjiang Road, Shanghai

Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation

C14 Grant of patent or utility model
GR01 Patent grant