CN109994476A - A method of preparing magnetic RAM array element - Google Patents
A method of preparing magnetic RAM array element Download PDFInfo
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- CN109994476A CN109994476A CN201711474396.3A CN201711474396A CN109994476A CN 109994476 A CN109994476 A CN 109994476A CN 201711474396 A CN201711474396 A CN 201711474396A CN 109994476 A CN109994476 A CN 109994476A
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
- G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
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Abstract
The present invention provides a kind of methods for preparing magnetic RAM array element, by interting one layer of bit line vias etching barrier layer among magnetic tunnel junction dielectric, enable the main etching being blocked in subsequent bit line vias etching technics, and main etching terminal optical emitting spectrum is provided and judges signal；Then selection etch rate is lower, selects to perform etching remaining dielectric and coating than higher over etching technique.Present invention effectively avoids bit line vias to etch final stage in the over etching of hard mask and magnetic tunnel junction periphery dielectric cap layer, and then avoids the short circuit of entire magnetic RAM array element circuit.
Description
Technical field
Magnetic RAM (MRAM, Magnetic Radom Access Memory) battle array is prepared the present invention relates to a kind of
The method of column unit belongs to magnetic RAM manufacturing technology field.
Background technique
In recent years, using the MRAM of magnetic tunnel junction (MTJ, Magnetic Tunnel Junction) by it is believed that being
Following solid state non-volatile memory body, it has the characteristics that high-speed read-write, large capacity and low energy consumption.Ferromagnetism MTJ is usual
For sandwich structure, layer is remembered wherein being magnetic, it can change the direction of magnetization to record different data；It is located in the middle absolutely
The tunnel barrier layer of edge；Magnetic reference layer, positioned at the other side of tunnel barrier layer, its direction of magnetization is constant.
For information can be recorded in this magnetoresistive element, it is proposed that using based on spin momentum transfer or spin-transfer torque
The write method of (STT, Spin Transfer Torque) switch technology, such MRAM are known as STT-MRAM.According to magnetic polarization
The difference in direction, STT-MRAM is divided into STT-MRAM and vertical STT-MRAM (i.e. pSTT-MRAM), the latter in face again to be had preferably
Performance.Method according to this, can be by providing spin polarized current to magnetoresistive element come the intensity of magnetization of inverting magnetization memory layer
Direction.In addition, the reduction of the volume with Magnetic memory layer, writes or spin polarized current that conversion operation need to be injected is also smaller.
Therefore, this write method can be achieved at the same time device miniaturization and reduce electric current.
Meanwhile can also reduce in view of switching electric current required when reducing MTJ element size, so the pSTT- in terms of scale
MRAM can be very good mutually to agree with state-of-the-art technology node.Therefore, it is desirable to be that pSTT-MRAM element is made into minimum ruler
It is very little, and there is extraordinary uniformity, and the influence to MTJ magnetism is minimized, used preparation method can also be real
Existing high good and the bad rate, pinpoint accuracy, high reliability, low energy consumption, and remain adapted to the temperature coefficient that data well save.Meanwhile
Write operation is changed based on resistance state in nonvolatile memory, thus to mtj memory device lifetime caused by needing to control thus
Destruction and shortening.However, one small-sized MTJ element of preparation may will increase the fluctuation of MTJ resistance, so that pSTT-MRAM
Biggish fluctuation can also be had therewith by writing voltage or electric current, can damage the performance of MRAM in this way.
In present MRAM manufacturing process, connection between magnetic tunnel junction (MTJ) and bit line (Bit line), usually
Using bit line vias (BLV, Bit Line Via) and with magnetic tunnel junction one-time formed top electrode (TE, Top
Electrode the mode) being connected directly is realized；However, when etching makes BLV, it is general using in magnetic tunnel junction
(MTJ) coating deposited immediately after etching is the etching barrier layer of BLV；In this configuration, this coating is not often
It is enough to stop the ion bombardment in the main etch step of BLV, this will will cause magnetic tunnel junction hearth electrode (BE, Bottom
Electrode) and the direct connection of top electrode (TE, Top Electrode), as shown in Figure 1, to make entire component failure.
If this phenomenon can be more obvious when the alignment of BLV and magnetic tunnel junction pattern does not make very accurate situation.
Summary of the invention
In order to solve the above-mentioned technical problems, the present invention provides a kind of sides for preparing magnetic RAM array element
Method.By interting one layer of bit line vias (BLV) etching barrier layer among magnetic tunnel junction dielectric, enable after being blocked in
Main etching in continuous bit line vias etching technics, and main etching terminal optical emitting spectrum (OES, Optical are provided
Emission Spectroscopy) judge signal；Then selection etch rate is lower, selects than higher over etching technique pair
Remaining dielectric and coating perform etching.Specific technical solution is as follows:
Scheme one, includes the following steps:
Step 1: provide surface polishing the CMOS substrate with metal throuth hole, and in substrate depositions of bottom electrode metal layer,
Magnetic tunnel junction multilayer film and top electrode film layer；
Step 2: patterned magnetic tunnel knot pattern, etching magnetic tunnel junction multilayer film forms magnetic tunnel junction, etches bottom
Electrode metal layer forms hearth electrode, and covers magnetic tunnel junction and hearth electrode with the first coating；
It is situated between Step 3: being sequentially depositing the first dielectric layer, bit line vias etching barrier layer, the second electricity on the first coating
Then matter layer planarizes the second dielectric layer, the second coating is then deposited on the second dielectric layer；
Step 4: etching forms bit line vias, and metallic copper filling is carried out in bit line vias.
Further, the material of the first coating is SiC, SiN or SiCN, using chemical vapor deposition, atomic layer deposition
Long-pending or ion beam depositing mode forms the first coating.
Further, the first dielectric layer, bit line vias etching barrier layer, the second dielectric layer and the second coating this
Four layers of overall thickness is 120nm~400nm.
Further, the first dielectric layer and the second dielectric layer are SiO2, SiON or low-dielectric constant dielectric medium.
Further, the material of bit line vias etching barrier layer is SiC, SiN or SiCN, using chemical vapor deposition or
Person's atomic layer deposition is conformal to be covered on the first dielectric layer, bit line vias etching barrier layer with a thickness of 10nm~50nm.
Further, the second coating is SiO2, the second coating is formed using chemical vapor deposition.
Further, etching is formed in the main etch step of bit line vias, using C4F8Or C4F6As main etching gas.
Using the optical emitting spectrum signal of CN or CO as the etching terminal signal for judging main etch step.After the completion of main etch step, choosing
With the main etching gas of low C/F content, it is sequentially etched bit line vias etching barrier layer, the first dielectric layer and the first coating,
And it stops in top electrode film layer.
Scheme two, includes the following steps:
Step 1: provide surface polishing the CMOS substrate with metal throuth hole, and in substrate depositions of bottom electrode metal layer,
Magnetic tunnel junction multilayer film and top electrode film layer；
Step 2: patterned magnetic tunnel knot pattern, etching magnetic tunnel junction multilayer film forms magnetic tunnel junction, etches bottom
Electrode metal layer forms hearth electrode, and covers magnetic tunnel junction and hearth electrode with the first coating；
Step 3: depositing the first dielectric layer on the first coating, and the first dielectric layer is planarized, then
Bit line vias etching barrier layer, the second dielectric layer, the second coating are sequentially depositing on the first dielectric layer；
Step 4: etching forms bit line vias, and metallic copper filling is carried out in bit line vias.
Beneficial effects of the present invention: present invention effectively avoids bit line vias etching final stage in hard mask and magnetism
The over etching of tunnel knot periphery dielectric cap layer, and then avoid the short of entire magnetic RAM array element circuit
Road.
Detailed description of the invention
In conjunction with attached drawing, and by reference to following detailed description, it will more easily to the present invention by more complete understanding
And its adjoint advantage and feature is more easily to understand, in which:
Under the conditions of Fig. 1 is prior art, schematic diagram that magnetic tunnel junction hearth electrode is directly connected to top electrode；
Fig. 2 (a) is the schematic diagram of substrate in a preferred embodiment of the present invention；
Fig. 2 (b) is the schematic diagram of the depositions of bottom electrode metal layer in substrate in a preferred embodiment of the present invention；
Fig. 3 is the schematic diagram of magnetic tunnel junction and the first coating in a preferred embodiment of the present invention；
Fig. 4 (a) and Fig. 4 (c) is the schematic diagram that etching forms bit line vias in a preferred embodiment of the present invention；
Fig. 5 (a) to Fig. 5 (c) is the schematic diagram that etching forms bit line vias in another preferred embodiment of the invention；
Description of symbols: the band metal throuth hole (V of 100- surface polishingx(x >=1)) CMOS substrate, 101-CMOS electricity
Medium, 102-CMOS dielectric, 103-CMOS via metal diffusion barrier layer, 104-CMOS via metal, 201- hearth electrode gold
Belong to layer, 202- magnetic tunnel junction multilayer film, 203- top electrode film layer (hard mask layer), the first coating of 204-, the first electricity of 205-
Dielectric layer, 206- bit line vias (BLV) etching barrier layer, the second dielectric layer of 207-, the second coating of 208-, 301- bit line are logical
Hole (BLV), 302- bit line vias (BLV) metal diffusion barrier layer, 303- bit line vias (BLV) metal.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.It should be noted that attached drawing of the present invention is all made of simplified form and uses non-essence
Quasi- ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
The present invention includes but is not limited solely to prepare magnetic RAM (MRAM), is also not necessarily limited to any process sequence or stream
Journey, as long as the same or similar method that the product or device that are prepared and following selection process sequence or process are prepared,
The specific steps of which are as follows:
Embodiment 1:
Step 1: the band metal throuth hole (V of surface polishing is providedx(x >=1)) CMOS substrate 100, as shown in Fig. 2 (a)；
And depositions of bottom electrode metal layer 201, magnetic tunnel junction multilayer film 202 and top electrode film layer 203 on it, as shown in Fig. 2 (b)；
Wherein, the material of CMOS through-hole is generally Cu or W etc..Hearth electrode metal layer 201 includes the materials such as Ta, TaN, Ti, TiN, W or WN
Material, thickness range are 20nm~80nm, generally use physical vapor deposition (PVD, Physical Vapor Deposition)
Deng mode realize.Further, surface planarisation processing can be carried out to it to improve its surface smoothness.
Wherein, the overall thickness of magnetic tunnel junction (MTJ) multilayer film 202 is 15nm~40nm, be can be by reference layer, potential barrier
The Bottom Pinned structure of layer and memory layer being superimposed upwards in turn either by memory layer, barrier layer and reference layer according to
The secondary Top Pinned structure being superimposed upwards.
Further, reference layer has magnetic polarization invariance, is face inner mold (iSTT-MRAM) or vertical (pSTT- according to it
MRAM) structure is different.The reference layer of face inner mold (iSTT-MRAM) generally has (IrMn or PtMn)/CoFe/Ru/CoFe/
CoFeB structure, preferred overall thickness are 10~30nm；The reference layer of vertical-type (pSTT-MRAM) generally have TbCoFe or
[Co/Pt]/Co/Ru/[CoPt]/CoFeBmSuperlattice multilayer film structure usually needs one layer of seed layer, such as Ta/Pt below,
Its preferred reference layer overall thickness is 8~20nm.
Further, barrier layer is nonmagnetic metal oxide, preferably MgO or Al2O3, with a thickness of 0.5nm~3nm.More
Further, barrier layer can use the structure of bilayer MgO.
Further, memory layer polarizes with variable magnetic, is face inner mold (iSTT-MRAM) or vertical (pSTT- according to it
MRAM) institute is different again for structure.The memory layer of face inner mold iSTT-MRAM is generally CoFe/CoFeB or CoFe/NiFe, preferred thick
Degree be 2nm~6nm, vertical-type pSTT-MRAM memory layer be generally CoFeB, CoFe/CoFeB, Fe/CoFeB, CoFeB (Ta, W,
Mo)/CoFeB, preferred thickness are 0.8nm~2nm.
In general, one layer of ultra-thin seed layer can be generally deposited before deposited magnetic tunnel knot multilayer film 202, to obtain more
The growth of good magnetic tunnel junction multilayer film 202.
Top electrode film layer (hard mask layer) 203 with a thickness of 20nm~100nm, select Ta, TaN, W or WN etc. in halogen
More preferable quarter profile is obtained in plain plasma-based.
Step 2: patterned magnetic tunnel knot pattern, and it is performed etching, it exists side by side and is covered using the first coating 204
The magnetic tunnel junction that lid etching is formed, as shown in Figure 3.
Above-mentioned steps specifically, graphic definition magnetic tunnel junction pattern, and to top electrode film layer (hard mask layer) 203,
Magnetic tunnel junction multilayer film 202 and hearth electrode metal layer 201 perform etching, and keep certain over etching, so that magnetic tunnel
Effectively separated between road knot, then deposits the first coating 204.
In the process, (LE, lithography-etching) or Twi-lithography two are once etched using a photoetching
The method of secondary etching (LELE, lithography-etching-lithography-etching) is completed to magnetic tunnel junction
The reactive ion etching (RIE) of definition and top electrode film layer 203, and it is residual using reactive ion etching or wet processing removing simultaneously
The polymer stayed, so that magnetic tunnel junction pattern is transferred to the top of magnetic tunnel junction.
Using reactive ion etching (RIE, Reactive Ion Etching) and/or ion beam etching (IBE, Ion
Beam Etching) method complete to the etching of magnetic tunnel junction (MTJ) multilayer film 202 and hearth electrode metal layer 201, and tie up
Hold certain over etching；Finally, magnetic tunnel junction (MTJ) array element is formed in storage region.
Wherein, IBE mainly uses Ar, Kr or Xe etc. as ion source；RIE mainly uses CH3OH、CH4/Ar、
C2H5OH、CH3OH/Ar or CO/NH3Deng as main etching gas；And it can choose fluoro-gas as over etching step
Predominant gas, so as to effectively be separated between the hearth electrode of different magnetic tunnel junction.
Wherein, 204 material of the first coating is SiC, SiN or SiCN etc., and forming method can use chemical gaseous phase
Deposit (CVD, Chemical Vapor Deposition), atomic layer deposition (ALD, Atomic Layer Deposition) or
The modes such as person's ion beam depositing (IBD, Ion Beam Deposition) are realized.
Step 3: the first dielectric layer 205, bit line vias (BLV) etching barrier layer 206, the second dielectric are sequentially depositing
Layer 207, and to being planarized at the top of the second dielectric layer 207, the second coating 208 is then deposited, as shown in Fig. 4 (a).Control
Making above-mentioned four layers of overall thickness is 120nm~400nm.Wherein, the first dielectric layer 205 and the second dielectric layer 207 are SiO2、
The materials such as SiON or low-k (low-k) dielectric.
Low-k (low-k) dielectric refers to that dielectric constant (k) is lower than the material of silica (k=3.9), is having
When body is implemented, low-k material can be hydrogeneous silicate (Hydrogen Silsequioxane, HSQ, k=2.8~3.0), contain
There is Si-CH3The salt containing methane-siliconic acid (Methylsilsesquioxane, MSQ, k=2.5~2.7) of functional group, synthesis are hydrogeneous
Hybrid organic siloxane polymer (Hybrid Organic synthesized by the silicates HSQ and MSQ of salt containing methane-siliconic acid
Siloxane Polymer, HOSP) film (k=2.5), porous SiOCH film (k=2.3~2.7), it might even be possible to using super
The organics high-molecular compounds such as the porosity silicate (Porous Silicate) of low-k (k < 2.0) and dielectric are normal
The porous SiOCH film that number (k) is 1.9.
Bit line vias (BLV) etching barrier layer 206 is generally SiC, SiN or SiCN etc., selects and uses chemical vapor deposition
Product (CVD, Chemical Vapor Deposition) or atomic layer deposition (ALD, Atomic Layer Deposition)
Be covered on to guarantor's type on the first dielectric layer 205, bit line vias (BLV) etching barrier layer 206 with a thickness of 10nm~50nm.The
Two coatings 208 are generally the SiO of high-compactness2, CVD technique is selected to be deposited.Flattening method generally uses chemical machine
Tool planarizes (CMP, Chemical Mechanical Planarization).
Step 4: etching magnetic tunnel junction bit line vias (BLV) go forward side by side row metal copper filling, such as Fig. 4 (b) and Fig. 4 (c) institute
Show；Its step are as follows:
Step 4.1: graphic definition simultaneously forms bit line vias (BLV) 301 using etching technics, in main etch step,
Generally using high C/F content ratio gas (such as: C4F8Or C4F6Deng) it is used as main etching gas；With CN (387nm) or CO
The OES signal of (520nm) etc. is as the etching terminal signal for judging main etch step, then, selects the main etching of low C/F content
Gas is sequentially etched bit line vias etching barrier layer 206, the first dielectric layer 205 and the first coating 204, accurately controls work
Skill parameter and gas componant make etch rate drop in reasonable range and be formed high SiO2/ SiN etching selection ratio, such as Fig. 4
(b) shown in；After etching is completed, remaining polymer etc. is removed using cleaning process.
Step 4.2: filling bit line vias metal 303, and polished using chemically mechanical polishing (CMP), such as Fig. 4 (c)
It is shown；It wherein, all can previously deposited one layer of bit line usually before plating (ECP, Electro Chemical Plating) copper
Via metal diffusion barrier layer 302 (Ti/TiN or Ta/TaN) and copper seed layer.
Embodiment 2:
Step 1: step 2: same respectively to implement in 1 Step 1: step 2；
Step 3: being sequentially depositing the first dielectric layer 205 and alignment polishes, then, depositing bitlines through-hole (BLV) etching resistance
Barrier 206, the second dielectric layer 207 and the second coating 208, as shown in Fig. 5 (a).Wherein, the overall thickness of four layers of control is
120nm~400nm；First dielectric layer 205 and the second dielectric layer 207 are SiO2, materials, the bit line such as SiON or low-k it is logical
Hole (BLV) etching barrier layer 206 is generally SiC, SiN or SiCN etc., selects and uses chemical vapor deposition (CVD, Chemical
Vapor Deposition) or the techniques such as atomic layer deposition (ALD, Atomic Layer Deposition) be covered on
On one dielectric layer 205, with a thickness of 10nm~50nm；Second coating 208 is generally the SiO of high-compactness2, select CVD
Technique is deposited.Flattening method generally uses chemical-mechanical planarization (CMP, Chemical Mechanical
Planarization)。
Step 4: with the 4th step of case study on implementation 1, as shown in Fig. 5 (b) and Fig. 5 (c).
The preferred embodiment of the present invention has been described in detail above.It should be appreciated that those skilled in the art without
It needs creative work according to the present invention can conceive and makes many modifications and variations.Therefore, all technologies in the art
Personnel are available by logical analysis, reasoning, or a limited experiment on the basis of existing technology under this invention's idea
Technical solution, all should be within the scope of protection determined by the claims.
Claims (10)
1. a kind of method for preparing magnetic RAM array element, which comprises the steps of:
Step 1: provide surface polishing the CMOS substrate with metal throuth hole, and on the substrate depositions of bottom electrode metal layer,
Magnetic tunnel junction multilayer film and top electrode film layer；
Step 2: patterned magnetic tunnel knot pattern, etches the magnetic tunnel junction multilayer film and forms magnetic tunnel junction, etch institute
It states hearth electrode metal layer and forms hearth electrode, and cover the magnetic tunnel junction and the hearth electrode with the first coating；
It is situated between Step 3: being sequentially depositing the first dielectric layer, bit line vias etching barrier layer, the second electricity on first coating
Then matter layer planarizes second dielectric layer, then deposit the second coating on second dielectric layer；
Step 4: etching forms bit line vias, and metallic copper filling is carried out in the bit line vias.
2. a kind of method for preparing magnetic RAM array element, which comprises the steps of:
Step 1: provide surface polishing the CMOS substrate with metal throuth hole, and on the substrate depositions of bottom electrode metal layer,
Magnetic tunnel junction multilayer film and top electrode film layer；
Step 2: patterned magnetic tunnel knot pattern, etches the magnetic tunnel junction multilayer film and forms magnetic tunnel junction, etch institute
It states hearth electrode metal layer and forms hearth electrode, and cover the magnetic tunnel junction and the hearth electrode with the first coating；
Step 3: depositing the first dielectric layer on first coating, and first dielectric layer is planarized,
Then bit line vias etching barrier layer, the second dielectric layer, the second coating are sequentially depositing on first dielectric layer；
Step 4: etching forms bit line vias, and metallic copper filling is carried out in the bit line vias.
3. a kind of method for preparing magnetic RAM array element according to claim 1 or 2, which is characterized in that
The material of first coating is that perhaps SiCN is heavy using chemical vapor deposition, atomic layer deposition or ion beam by SiC, SiN
Product mode forms first coating.
4. a kind of method for preparing magnetic RAM array element according to claim 1 or 2, which is characterized in that
In step 3, first dielectric layer, the bit line vias etching barrier layer, second dielectric layer and described second
This four layers overall thickness of coating is 120nm~400nm.
5. a kind of method for preparing magnetic RAM array element according to claim 1 or 2, which is characterized in that
First dielectric layer and second dielectric layer are SiO2, SiON or low-dielectric constant dielectric medium.
6. a kind of method for preparing magnetic RAM array element according to claim 1 or 2, which is characterized in that
The material of the bit line vias etching barrier layer be SiC, SiN perhaps SiCN using chemical vapor deposition or atomic layer deposition
It is conformal to be covered on first dielectric layer, the bit line vias etching barrier layer with a thickness of 10nm~50nm.
7. a kind of method for preparing magnetic RAM array element according to claim 1 or 2, which is characterized in that
Second coating is SiO2, second coating is formed using chemical vapor deposition.
8. a kind of method for preparing magnetic RAM array element according to claim 1 or 2, which is characterized in that
Etching is formed in the main etch step of the bit line vias, using C4F8Or C4F6As main etching gas.
9. a kind of method for preparing magnetic RAM array element according to claim 8, which is characterized in that with CN
Or the optical emitting spectrum signal of CO is as the etching terminal signal for judging the main etch step.
10. a kind of method for preparing magnetic RAM array element according to claim 8, which is characterized in that institute
After the completion of stating main etch step, select the main etching gas of low C/F content, be sequentially etched the bit line vias etching barrier layer,
First dielectric layer and first coating, and stop in the top electrode film layer.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102007614A (en) * | 2008-04-18 | 2011-04-06 | 高通股份有限公司 | Manufacturing method of a magnetic tunnel junction element using two masks |
| CN102376651A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Method for improving capacity of filling dielectric medium between magnetic tunnel junction (MTJ) metals in magnetic random access memory (MRAM) |
| US20150017741A1 (en) * | 2013-07-10 | 2015-01-15 | Hitachi High-Technologies Corporation | Plasma etching method |
| CN107068856A (en) * | 2016-01-29 | 2017-08-18 | 台湾积体电路制造股份有限公司 | Semiconductor structure and the method for manufacturing it |
-
2017
- 2017-12-29 CN CN201711474396.3A patent/CN109994476B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102007614A (en) * | 2008-04-18 | 2011-04-06 | 高通股份有限公司 | Manufacturing method of a magnetic tunnel junction element using two masks |
| CN102376651A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Method for improving capacity of filling dielectric medium between magnetic tunnel junction (MTJ) metals in magnetic random access memory (MRAM) |
| US20150017741A1 (en) * | 2013-07-10 | 2015-01-15 | Hitachi High-Technologies Corporation | Plasma etching method |
| CN107068856A (en) * | 2016-01-29 | 2017-08-18 | 台湾积体电路制造股份有限公司 | Semiconductor structure and the method for manufacturing it |
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