CN110098320B - Method for etching conductive hard mask of magnetic tunnel junction - Google Patents

Method for etching conductive hard mask of magnetic tunnel junction Download PDF

Info

Publication number
CN110098320B
CN110098320B CN201810090020.0A CN201810090020A CN110098320B CN 110098320 B CN110098320 B CN 110098320B CN 201810090020 A CN201810090020 A CN 201810090020A CN 110098320 B CN110098320 B CN 110098320B
Authority
CN
China
Prior art keywords
hard mask
etching
conductive hard
layer
tunnel junction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810090020.0A
Other languages
Chinese (zh)
Other versions
CN110098320A (en
Inventor
张云森
肖荣福
郭一民
陈峻
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Information Technologies Co ltd
Original Assignee
Shanghai Information Technologies Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Information Technologies Co ltd filed Critical Shanghai Information Technologies Co ltd
Priority to CN201810090020.0A priority Critical patent/CN110098320B/en
Publication of CN110098320A publication Critical patent/CN110098320A/en
Application granted granted Critical
Publication of CN110098320B publication Critical patent/CN110098320B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

The invention provides a method for etching a conductive hard mask of a magnetic tunnel junction, which comprises the following steps: (1) Providing a CMOS substrate with a metal through hole, and depositing a bottom electrode, a magnetic tunnel junction multilayer film, an etching barrier layer of a conductive hard mould layer, a conductive hard mask and a mask layer of the conductive hard mask on the substrate; (2) Patterning the conductive hard mask pattern using a bilayer structure of photoresist/bottom anti-reflective layer or a trilayer structure of photoresist/inorganic anti-reflective layer/carbon-containing film layer, and transferring the pattern to the top of the mask layer of the conductive hard mask; (3) etching the conductive hard mask and removing the residue. The invention is beneficial to the control of the critical dimension of the MTJ cell array and the future continuous miniaturization of the whole MRAM, and is beneficial to the improvement of the yield of devices.

Description

Method for etching conductive hard mask of magnetic tunnel junction
Technical Field
The invention relates to a method for etching a conductive hard mask (C-HM, conductive Hard Mask) of a magnetic tunnel junction, belonging to the technical field of manufacturing of magnetic random access memories (MRAM, magnetic Radom Access Memory).
Background
In recent years, MRAM using a magnetic tunnel junction (MTJ, magnetic Tunnel Junction) has been considered as a future solid-state nonvolatile memory, which has characteristics of high-speed reading and writing, large capacity, and low power consumption. Ferromagnetic MTJs are typically sandwich structures, with: a magnetic memory layer which can change a magnetization direction to record different data; an insulating tunnel barrier layer located in the middle; and the magnetic reference layer is positioned on the other side of the tunnel barrier layer, and the magnetization direction of the magnetic reference layer is unchanged.
To be able to record information in such magnetoresistive elements, a writing method based on spin momentum transfer or spin transfer torque (STT, spin Transfer Torque) switching technology is proposed, such MRAM being called STT-MRAM. STT-MRAM is further divided into in-plane STT-MRAM and perpendicular STT-MRAM (i.e., pSTT-MRAM) depending on the direction of magnetic polarization, which have better performance. In this way, the magnetization direction of the magnetic memory layer can be reversed by supplying spin-polarized current to the magnetoresistive element. In addition, as the volume of the magnetic memory layer is reduced, the spin-polarized current to be injected for writing or switching operations is also smaller. Thus, this writing method can achieve both device miniaturization and current reduction.
Meanwhile, the pSTT-MRAM can be well matched with the most advanced technology node in terms of scale, since the switching current required for reducing the size of the MTJ element is also reduced. It is therefore desirable to make pSTT-MRAM elements of very small dimensions, with very good uniformity, and minimizing the impact on MTJ magnetism, using fabrication methods that also achieve Gao Liang rates, high accuracy, high reliability, low power consumption, and maintain a temperature coefficient suitable for good data storage. Meanwhile, the write operation in the nonvolatile memory is based on the resistance state change, so that it is necessary to control the damage and shortening of the life of the MTJ memory device caused thereby. However, the fabrication of a small MTJ element may increase the fluctuation of MTJ resistance, so that the write voltage or current of pSTT-MRAM may also fluctuate greatly, which may impair the performance of MRAM.
In the current MRAM manufacturing process, a primary photomask is generally used to manufacture a Top Electrode (TE), a Magnetic Tunnel Junction (MTJ) cell, and a Bottom Electrode (BE) of a Magnetic Random Access Memory (MRAM); wherein, when etching the magnetic tunnel junction and the bottom electrode unit array, the top electrode is used as a hard mask, and the magnetic tunnel junction and the bottom electrode are self-aligned to the hard mask for etching, so the Top Electrode (TE) is also called a conductive hard mask (C-HM).
Since the magnetic tunnel junction contains Co, fe, ni, pt and other elements, if these elements and Cl and H 2 O, etc., then the Magnetic Tunnel Junction (MTJ) will be chemically damaged (Chemical Corrosion and galvaneiffect), thereby affecting the improvement of its magnetic and electrical properties.
In order to avoid the potential negative effect of Cl element, in the current conductive hard mask etching process, a C/F gas is generally used to perform reactive ion etching (RIE, reactive Ion Etching) on the conductive hard mask; due to SiO 2 The selection ratio of SiON or SiN to the conductive Hard Mask is very low, and when the reactive ion etching process is carried out, photoresist (PR) can only be used as a Soft Mask or a carbon-containing film layer can be used as a Hard Mask (Hard Mask) for etching, and due to the existence of a large amount of C, the Photoresist (PR) or the carbon-containing film layer can be etched after etchingThe electrical hard mask and the side wall of the photoresist/carbon-film-containing layer form a layer of conductive polymer which is difficult to remove, and due to the existence of the irregular conductive polymer, a standard circular MTJ pattern is difficult to obtain in the subsequent MTJ etching, and the control of the MTJ critical dimension (CD, critical Dimension) is not utilized, so that the fluctuation of the read/write current of the MRAM circuit is increased, the improvement of the yield rate of the MRAM circuit is not facilitated, and the continuous miniaturization of the MTJ array unit is not facilitated.
Disclosure of Invention
In order to solve the technical problems, the invention provides a method for etching a conductive hard mask of a magnetic tunnel junction, which selects SiO 2 SiON, siC or SiN is used as etching hard mask of conductive hard mask (such as Ta, taN, ti, tiN, W or WN, etc.), cl is selected 2 Etching the conductive hard mask with the main gas and stopping the etching on the Ru etching barrier layer; finally, in order to prevent the edges of the conductive hard mask (C-HM) from being oxidized, an oxygen-free foaming gas (N 2 /4％H 2 )、N 2 /H 2 Or NH 3 Etc. to remove residues during etching. The specific technical scheme is as follows:
a method of etching a magnetic tunnel junction conductive hard mask comprising the steps of:
providing a CMOS substrate with a metal through hole, wherein the surface of the CMOS substrate is polished, and depositing a bottom electrode, a magnetic tunnel junction multilayer film, an etching barrier layer of a conductive hard mould layer, a conductive hard mask and a mask layer of the conductive hard mask on the substrate;
patterning the conductive hard mask pattern by adopting a double-layer structure of a photoresist/bottom anti-reflection layer or a three-layer structure of a photoresist/inorganic anti-reflection layer/carbon-containing film layer, and transferring the pattern to the top of the mask layer of the conductive hard mask;
and thirdly, etching the conductive hard mask and removing residues.
Further, the material of the etching barrier layer of the conductive hard mask is Ru, and the total thickness of the etching barrier layer of the conductive hard mask is 1 nm-10 nm.
Further, the thickness of the conductive hard mask is 20 nm-100 nm, and the material of the conductive hard mask is Ta, taN, ti, tiN, W or WN.
Further, the thickness of the mask layer of the conductive hard mask is 10 nm-100 nm, and the mask layer of the conductive hard mask is SiO 2 A single layer of SiON, siC, siCN or SiN material, or of SiO 2 A bilayer material of any two of SiON, siC, siCN or SiN.
Further, in the second step, the C/F gas is adopted as the main etching gas to etch the mask layer of the conductive hard mask; after etching, use O 2 、N 2 、O 2 /N 2 Mixture gas or N 2 /H 2 And (3) carrying out reactive ion etching removal on the polymer left after etching by the mixed gas.
Further, the third step comprises the following subdivision steps:
step 3.1: removing the oxide layer of the conductive hard mask by penetration etching;
step 3.2: etching the conductive hard mask, stopping etching on the etching barrier layer of the conductive hard mask, and maintaining partial over-etching;
step 3.3: the residue is removed using a reactive ion etching process without bias.
Further, in step 3.1, the process gas is a C/F gas.
Further, in step 3.2, the main etching gas is Cl 2 、CF 4 、NF 3 Or SF (sulfur hexafluoride) 6 . Can add CH 4 、N 2 、CH 3 F、CH 2 F 2 、CHF 3 Or one or more of Ar, etc. as an auxiliary etching gas.
Further, in step 3.3, the etching gas is N 2 /4％H 2 Foaming gas, N 2 /H 2 Mixture gas or NH 3 。
The invention has the beneficial effects that: the control of the critical dimension of the MTJ cell array and the future continuous miniaturization of the whole MRAM are very facilitated; the adhesion of Cl on the conductive hard mask is further reduced, and the improvement of the device yield is facilitated; the method is very beneficial to the improvement of the yield of the device.
Drawings
The invention will be more fully understood and its attendant advantages and features will be more readily understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, in which:
FIGS. 1 (a) to 1 (b) are schematic diagrams illustrating the deposition of various layers on a CMOS substrate according to a preferred embodiment of the present invention;
FIG. 2 is a schematic diagram of a patterned conductive hard mask pattern in accordance with a preferred embodiment of the present invention;
FIGS. 3 (a) to 3 (b) are schematic views illustrating etching of a conductive hard mask in accordance with a preferred embodiment of the present invention;
FIG. 4 is a schematic illustration of etching to form a bottom electrode and a magnetic tunnel junction in accordance with a preferred embodiment of the present invention.
Reference numerals illustrate: 100-surface polished through-hole with metal (V x (x>=1)), 101-CMOS dielectric, 102-CMOS via metal, 201-bottom electrode and magnetic tunnel junction multilayer film, 202-etch stop layer for conductive hard mask, 203-conductive hard mask, 204-mask layer for conductive hard mask, 205-etch residue, 206-magnetic tunnel junction cap layer, 207-magnetic tunnel junction dielectric.
Detailed Description
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to the appended drawings. It should be noted that the drawings of the present invention are in simplified form and are not to scale precisely, but rather are merely intended to facilitate a clear and concise description of embodiments of the present invention.
The invention discloses a method for etching a conductive hard mask of a magnetic tunnel junction. SiO is selected for use 2 SiON, siC, siN, or the like is used as an etching hard mask for etching the conductive hard mask (such as Ta, taN, ti, tiN, W, WN, or the like), and Cl is selected 2 Etching the conductive hard mask with the main gas and stopping the etching on the Ru etching barrier layer; finally, in order to prevent the edges of the conductive hard mask (C-HM) from being oxidized, an oxygen-free foaming gas (N 2 /4％H 2 )、N 2 /H 2 Or NH 3 And the like to remove the etching processResidues in (a) and (b).
Because the photoresist/carbon-containing film layer is not used as a mask for etching the conductive hard mask in the etching process, an irregular conductive polymer covered on the side wall of the conductive hard mask is not formed in a large amount, which is very beneficial to the control of the critical dimension of the magnetic tunnel junction cell array and the future continuous miniaturization of the whole MRAM; due to the adoption of SiO 2 SiON, siC or SiN is used as a hard mask for etching the conductive hard mask, so that the content of C is very small in the whole etching process, the adhesion of Cl on the conductive hard mask is further reduced, and the improvement of the device yield is facilitated; the dry process of removing the residues after etching is adopted by the gas containing the N/H element, so that the H released in the gas can further neutralize the Cl element in the process, other residues can be effectively removed, and moreover, the gas is free of O, and the Ru etching barrier layer can block the etching of the N/H, so that the improvement of the yield of the device is very facilitated.
The present invention includes, but is not limited to, the fabrication of Magnetic Random Access Memory (MRAM), nor is it limited to any process sequence or flow, provided that the resulting product or device is the same or similar to the following preferred process sequence or flow, comprising the following specific steps:
step one: providing surface polished through holes with metal (V x (x>=1)), as shown in fig. 1 (a); and depositing a bottom electrode and magnetic tunnel junction multilayer film 201, an etch stop layer 202 of a conductive hard mask layer, a conductive hard mask 203 and a mask layer 204 of a conductive hard mask on the substrate 100, as shown in fig. 1 (b); the material of the CMOS via hole is typically Cu, W, or the like.
The Bottom Electrode (BE) comprises Ta, taN, ti, tiN, W or WN and other materials, the thickness of the bottom electrode is 20-80 nm, and the bottom electrode is generally realized by adopting physical vapor deposition (PVD, physical Vapor Deposition) and other modes; further, it may be subjected to a surface planarization treatment in order to improve its surface flatness.
The total thickness of the Magnetic Tunnel Junction (MTJ) multilayer film is 15-40 nm, and the Magnetic Tunnel Junction (MTJ) multilayer film can be a Bottom Pinned structure formed by sequentially and upwardly superposing a reference layer, a barrier layer and a memory layer or a Top Pinned structure formed by sequentially and upwardly superposing the memory layer, the barrier layer and the reference layer.
Further, the reference layer has magnetic polarization invariance, which varies depending on whether it is an in-plane (iSTT-MRAM) or perpendicular (pSTT-MRAM) structure. The reference layer of the in-plane type (iSTT-MRAM) generally has a structure of (IrMn or PtMn)/CoFe/Ru/CoFe/CoFeB, and the total thickness thereof is preferably 10-30 nm; the reference layer of the perpendicular (pSTT-MRAM) typically has TbCoFe or [ Co/Pt ]]/Co/Ru/[CoPt]/CoFeB m The superlattice multilayer film structure generally requires a seed layer, such as Ta/Pt, below, which preferably has a total reference layer thickness of 8-20 nm.
Further, the barrier layer is a non-magnetic metal oxide, preferably MgO or Al 2 O 3 The thickness is 0.5 nm-3 nm. Further, a double-layer MgO structure may be employed.
Further, the memory layer has a variable magnetic polarization, which is different depending on whether it is an in-plane (iSTT-MRAM) or a perpendicular (pSTT-MRAM) structure. The memory layer of the in-plane iSTT-MRAM is typically CoFe/CoFeB or CoFe/NiFe, and preferably has a thickness of 2nm to 6nm, and the memory layer of the perpendicular pSTT-MRAM is typically CoFeB, coFe/CoFeB, fe/CoFeB, coFeB (Ta, W, mo)/CoFeB, and preferably has a thickness of 0.8nm to 2nm.
The etch stop layer 202 of the conductive hard mask, typically Ru, is 1nm to 10nm thick.
The conductive hard mask 203 is also a top electrode film layer with a thickness of 20 nm-100 nm, ta, taN, ti, tiN, W or WN, etc. are selected in order to obtain a better profile in the halogen plasma.
The mask layer 204 of the conductive hard mask has a thickness of 10nm to 100nm and may be formed of SiO 2 A single layer material such as SiON, siC, siCN or SiN, or a double layer material composed of any two of the above.
Step two: patterning a conductive hard mask (C-HM) pattern and transferring the pattern to the top of the mask layer 203 of the patterned conductive hard mask (C-HM), as shown in fig. 2;
in this process, a dual layer structure of photoresist/Bottom Anti-reflective coating (BARC) or a three layer structure of photoresist/inorganic Anti-reflective layer (DARC, dielectricAnti-Reflective Coating)/carbon-containing film layer is used for patterning definition of the conductive hard mask 203.
Then, the mask layer 204 of the conductive hard mask is etched using a C/F gas as a main etching gas, and, after etching, O is used 2 、N 2 、O 2 /N 2 Or N 2 /H 2 The residual polymerization is removed by reactive ion etching.
Step three: etching the conductive hard mask 203 and removing the etching residues 205; the steps can be specifically divided into the following steps:
step 3.1: removing the oxide layer of the conductive hard mask 203 by means of a breakthrough etch (BT); in this step, the reactive ion etching process gas is a C/F gas.
Step 3.2: etching the conductive hard mask 203 and stopping the etching above the etch stop layer 202 of the conductive hard mask, maintaining a small amount of overetching; wherein the main etching gas is Cl 2 、CF 4 、NF 3 Or SF (sulfur hexafluoride) 6 Etc., and may be added with CH 4 、N 2 、CH 3 F、CH 2 F 2 、CHF 3 Or one or more of Ar, etc. as an auxiliary etching gas.
Step 3.3: etching residues 205 are removed by a reactive ion etching process without bias, wherein the etching gas is foaming gas (N2/4% H2), N 2 /H 2 Or NH 3 Etc.
Step four: the bottom electrode and magnetic tunnel junction multilayer film 201 are etched, then covered with a magnetic tunnel junction cap layer 206, then filled with a magnetic tunnel junction dielectric 207, and finally the magnetic tunnel junction dielectric 207 is planarized, as shown in fig. 4.
The foregoing describes in detail preferred embodiments of the present invention. It should be understood that numerous modifications and variations can be made in accordance with the concepts of the invention by one of ordinary skill in the art without undue burden. Therefore, all technical solutions which can be obtained by logic analysis, reasoning or limited experiments based on the prior art by the person skilled in the art according to the inventive concept shall be within the scope of protection defined by the claims.

Claims (9)

1. A method of etching a magnetic tunnel junction conductive hard mask comprising the steps of:
providing a CMOS substrate with a metal through hole, wherein the surface of the CMOS substrate is polished, and depositing a bottom electrode, a magnetic tunnel junction multilayer film, an etching barrier layer of a conductive hard mould layer, a conductive hard mask and a mask layer of the conductive hard mask on the substrate;
patterning a conductive hard mask pattern by adopting a double-layer structure of a photoresist/bottom anti-reflection layer or a three-layer structure of a photoresist/inorganic anti-reflection layer/carbon-containing film layer, and transferring the pattern to the top of a mask layer of the conductive hard mask;
step three, etching the conductive hard mask and removing residues;
wherein, step three includes the following subdivision steps:
step 3.1: removing the oxide layer of the conductive hard mask by penetrating etching;
step 3.2: cl is selected for use 2 Etching the conductive hard mask as a main etching gas, stopping etching on the etching barrier layer of the conductive hard mask, and maintaining partial over-etching;
step 3.3: the residue is removed using a reactive ion etching process without bias.
2. The method of etching a conductive hard mask of a magnetic tunnel junction of claim 1 wherein the material of the etch stop layer of the conductive hard mask is Ru and the total thickness of the etch stop layer of the conductive hard mask is 1nm to 10nm.
3. The method of etching a magnetic tunnel junction conductive hard mask according to claim 1, wherein the thickness of the conductive hard mask is 20 nm-100 nm, and the material of the conductive hard mask is Ta, taN, ti, tiN, W or WN.
4. The method of etching a magnetic tunnel junction conductive hard mask according to claim 1, wherein the thickness of the mask layer of the conductive hard mask is 10nm to 100nm, and the mask layer of the conductive hard mask is SiO 2 A single layer of SiON, siC, siCN or SiN material, or of SiO 2 A bilayer material of any two of SiON, siC, siCN or SiN.
5. The method for etching the conductive hard mask of the magnetic tunnel junction according to claim 1, wherein in the second step, a C/F gas is used as a main etching gas to etch the mask layer of the conductive hard mask; after etching, use O 2 、N 2 、O 2 /N 2 Mixture gas or N 2 /H 2 And (3) carrying out reactive ion etching removal on the polymer left after etching by the mixed gas.
6. The method of etching a magnetic tunnel junction conductive hard mask of claim 1 wherein the process gas is a C/F gas in step 3.1.
7. The method of etching a magnetic tunnel junction conductive hard mask as claimed in claim 1, wherein in step 3.2, the main etching gas is CF 4 、NF 3 Or SF (sulfur hexafluoride) 6 。
8. The method of etching a magnetic tunnel junction conductive hard mask as claimed in claim 7, wherein in step 3.2, CH is added 4 、N 2 、CH 3 F、CH 2 F 2 、CHF 3 Or one or more of Ar as an auxiliary etching gas.
9. The method of etching a magnetic tunnel junction conductive hard mask as claimed in claim 1, wherein in step 3.3, the etching gas is N 2 /4％H 2 Foaming gas, N 2 /H 2 Mixture gas or NH 3 。
CN201810090020.0A 2018-01-30 2018-01-30 Method for etching conductive hard mask of magnetic tunnel junction Active CN110098320B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810090020.0A CN110098320B (en) 2018-01-30 2018-01-30 Method for etching conductive hard mask of magnetic tunnel junction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810090020.0A CN110098320B (en) 2018-01-30 2018-01-30 Method for etching conductive hard mask of magnetic tunnel junction

Publications (2)

Publication Number Publication Date
CN110098320A CN110098320A (en) 2019-08-06
CN110098320B true CN110098320B (en) 2023-04-28

Family

ID=67441889

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810090020.0A Active CN110098320B (en) 2018-01-30 2018-01-30 Method for etching conductive hard mask of magnetic tunnel junction

Country Status (1)

Country Link
CN (1) CN110098320B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111446206B (en) * 2020-04-27 2023-04-07 上海华力微电子有限公司 Metal wire self-alignment secondary forming process method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011148944A1 (en) * 2010-05-28 2011-12-01 日本電気株式会社 Thin film magnetic device and method for manufacturing same
JP2015046528A (en) * 2013-08-29 2015-03-12 株式会社アルバック Method of manufacturing magnetoresistive element
CN106067513A (en) * 2015-04-20 2016-11-02 朗姆研究公司 The dry plasma etch method of patterning MRAM storehouse
CN107331770A (en) * 2016-04-29 2017-11-07 上海磁宇信息科技有限公司 A kind of method of four layer masks patterned magnetic tunnel knot
CN107452874A (en) * 2016-05-30 2017-12-08 上海磁宇信息科技有限公司 A kind of forming method of MTJ autoregistration tantalum mask

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160351799A1 (en) * 2015-05-30 2016-12-01 Applied Materials, Inc. Hard mask for patterning magnetic tunnel junctions
US9978934B2 (en) * 2015-10-30 2018-05-22 Veeco Instruments Inc. Ion beam etching of STT-RAM structures

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011148944A1 (en) * 2010-05-28 2011-12-01 日本電気株式会社 Thin film magnetic device and method for manufacturing same
JP2015046528A (en) * 2013-08-29 2015-03-12 株式会社アルバック Method of manufacturing magnetoresistive element
CN106067513A (en) * 2015-04-20 2016-11-02 朗姆研究公司 The dry plasma etch method of patterning MRAM storehouse
CN107331770A (en) * 2016-04-29 2017-11-07 上海磁宇信息科技有限公司 A kind of method of four layer masks patterned magnetic tunnel knot
CN107452874A (en) * 2016-05-30 2017-12-08 上海磁宇信息科技有限公司 A kind of forming method of MTJ autoregistration tantalum mask

Also Published As

Publication number Publication date
CN110098320A (en) 2019-08-06

Similar Documents

Publication Publication Date Title
CN108232009B (en) Method for manufacturing magnetic random access memory
US8634231B2 (en) Magnetic tunnel junction structure
CN109994602B (en) Method for preparing magnetic random access memory storage unit and logic unit
CN107623069B (en) Method for etching magnetic tunnel junction and bottom electrode thereof
CN108232008B (en) Bottom electrode contact of magnetic random access memory and preparation method thereof
CN109713006B (en) Method for manufacturing magnetic random access memory cell array and peripheral circuit thereof
CN107527994B (en) Magnetic tunnel junction double-layer side wall and forming method thereof
US11770977B2 (en) Semiconductor structure and method for forming the same
CN109713121B (en) Method for manufacturing magnetic random access memory cell array and peripheral circuit thereof
CN111613719B (en) Method for manufacturing magnetic random access memory cell array
CN108075037B (en) Method for preparing magnetic tunnel junction
CN109545744B (en) Method for manufacturing magnetic random access memory unit array and peripheral circuit connecting line
CN108735895B (en) Magnetic random access memory bottom electrode contact and method of forming the same
CN109994600B (en) Method for manufacturing magnetic random access memory
CN107331770B (en) Method for patterning magnetic tunnel junction by four layers of masks
CN109713120A (en) A kind of manufacturing method of magnetic RAM cell array and peripheral circuit line
CN110098320B (en) Method for etching conductive hard mask of magnetic tunnel junction
CN110098321B (en) Method for preparing magnetic random access memory conductive hard mask
CN107437581B (en) Preparation method of magnetic tunnel junction with tantalum oxide as hard mask
CN110098216A (en) A method of making the conductive hard mask as magnetic RAM top electrode
CN107331769B (en) Method for selectively etching double-layer hard mask of magnetic tunnel junction by reactive ion beam
CN111668368B (en) Preparation method of pseudo-magnetic tunnel junction unit structure
CN111613571B (en) Method for manufacturing magnetic random access memory cell array
CN111490151B (en) Method for manufacturing microminiature magnetic random access memory array
CN108735893B (en) Bottom electrode contact of magnetic random access memory and forming method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant