CN112186097A - Structure for optimizing write performance of magnetic random access memory and preparation method thereof - Google Patents
Structure for optimizing write performance of magnetic random access memory and preparation method thereof Download PDFInfo
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Abstract
The invention discloses a structure for optimizing the writing performance of a magnetic random access memory, which comprises a writing accelerator, wherein the writing accelerator is positioned on the lower side of a bottom electrode and the upper side of a bottom electrode through hole of the magnetic random access memory, and is directly connected with the bottom electrode and the bottom electrode through hole. The invention also discloses a preparation method of the structure for optimizing the writing performance of the magnetic random access memory, which comprises the following steps: the method comprises the following steps: providing a surface-polished CMOS substrate with metal connecting wires Mx; step two: manufacturing a bottom electrode through hole on the flattened CMOS substrate and grinding the bottom electrode through hole to be flat; step three: patterning, defining and etching write accelerator metal on the bottom electrode through hole, filling a write accelerator dielectric, and grinding the write accelerator dielectric by adopting chemical mechanical planarization; step four: and depositing a bottom electrode, a magnetic tunnel junction multilayer film and a top electrode on the writing accelerator in sequence, manufacturing a magnetic tunnel junction storage unit, and finally manufacturing a bit line connection on the top electrode.
Description
Technical Field
The invention relates to the technical field of Magnetic Random Access Memories (MRAM), in particular to a structure for optimizing the writing performance of the MRAM and a preparation method thereof.
Background
In recent years, MRAM using Magnetic Tunnel Junction (MTJ) is considered as a future solid-state nonvolatile memory, which has the characteristics of high speed reading and writing, large capacity and low power consumption, and the ferromagnetic MTJ is usually a sandwich structure in which a Free Layer (FL) is provided, which can change the magnetization direction to record different data; an insulating tunnel Barrier Layer (BL) in the middle; the magnetic Reference Layer (RL) is located on the other side of the tunnel barrier Layer, and its magnetization direction is unchanged, specifically, it may be a Bottom Pinned structure formed by sequentially stacking the Reference Layer (RL), the Barrier Layer (BL), and the Free Layer (FL) upward or a top Pinned structure formed by sequentially stacking the Free Layer (FL), the Barrier Layer (BL), and the Reference Layer (RL) upward, and the Bottom Pinned structure is popular at present.
In order to be able to record information in such magnetoresistive elements, it is proposed to use a writing method based on Spin momentum Transfer or Spin Transfer Torque (STT) switching technology, such MRAM being called STT-MRAM, which is further divided into in-plane STT-MRAM and perpendicular STT-MRAM, the latter having better performance, depending on the direction of magnetic polarization, in a Magnetic Tunnel Junction (MTJ) with perpendicular anisotropy (PMA), as a free layer for storing information, having two magnetization directions in the perpendicular direction, namely: upward and downward, in practical application, the direction of the magnetization vector of the free layer is kept unchanged when information is read or the free layer is empty; in the writing process, if there is a signal input in a state different from the existing state, the direction of the magnetization vector of the free layer will be flipped by 180 degrees in the vertical direction, and the ability of the free layer of the magnetic Memory to keep the magnetization vector direction unchanged under the empty state is called Data Retention (Data Retention) or Thermal Stability (Thermal Stability), which is different in different application scenarios, and the Thermal Stability requirement for a typical Non-volatile Memory (NVM) is that Data can be stored for 10 years under the condition of 125 ℃.
Further, the Data Retention capability (Data Retention) can be calculated by the following formula:
wherein tau is the time when the magnetization vector is unchanged under the condition of thermal disturbance, tau0For trial time, E is the energy barrier of the free layer, kBBoltzmann constant, T is the operating temperature.
The Thermal Stability Factor (Thermal Stability Factor) can then be expressed as the following equation:
wherein, KeffIs the effective isotropic energy density of the free layer, V is the volume of the free layer, KVIs the bulk anisotropy constant, MsSaturation magnetic susceptibility of the free layer, NzDemagnetization constant in the vertical direction, t is the thickness of the free layer, KiCD is the Critical Dimension (CD) of a Magnetic Random Access Memory (MRAM) and As is the stiffness integral exchange constant.
Further, λ is a critical dimension of the transition of the magnetization vector switching mode of the free layer from the domain switching mode to the reverse domain nucleation/expansion mode, and experiments show that the free layer exhibits in-plane anisotropy when the thickness thereof is thick and perpendicular anisotropy when the thickness thereof is thin, KVGenerally negligible, while the contribution of demagnetization energy to the perpendicular anisotropy is negative, so the perpendicular anisotropy comes entirely from the interfacial effect (K)i)。
Further, for Magnetic Tunnel Junctions (MTJs) with Perpendicular Anisotropy (PMA), empirical data indicate that the critical dimensions of domain inversion (I) and inversion domain nucleation/expansion (II) are 40nm to 70 nm.
In addition, as the volume of the magnetic free layer is reduced, the spin polarization current to be injected for writing or switching operation is reduced, and in the conventional PSTT-MRAM, the critical current I for writing operation is reducedc0The relationship between the compound and the thermal stability is strongly related, and can be expressed as the following formula:
wherein, alpha is a damping coefficient,
η is the spin polarizability, which is the approximate planck constant.
As mentioned above, STT-based spin transfer torque is the mainstream writing method of MRAM at present, however, it also has the bottleneck of speed and barrier reliability which is difficult to overcome, the magnitude of the spin transfer torque is in positive correlation with the product of magnetization vectors of the Free Layer (FL) and the Reference Layer (RL), before writing, the magnetization directions of the two ferromagnetic layers are almost collinear (parallel or antiparallel), and a small included angle is mainly caused by thermal fluctuation, so that in the initial stage of writing, the spin transfer torque is relatively weak, the included angle between the two magnetization vectors is gradually increased along with the progress of magnetization reversal process, the spin transfer torque is enhanced, initially, the weak spin transfer torque causes an initial Delay (Incubation Delay), the writing speed is limited, the initial Delay can be reduced by increasing the writing current, but the probability of barrier breakdown is also increased, and the presence of the initial Delay makes STT-MRAM still difficult to satisfy the performance of high-speed cache (e.g. SRAM) at present And (6) obtaining.
In addition, MTJ, which is the core memory cell of magnetic memory (MRAM), must also be compatible with CMOS processes and must be able to withstand long term annealing at 400 ℃.
Disclosure of Invention
The present invention provides a structure for optimizing the write performance of a Magnetic Random Access Memory (MRAM) and a method for manufacturing the same, which aims at the problems and disadvantages of the prior art.
The invention solves the technical problems through the following technical scheme:
the invention provides a structure for optimizing the writing performance of a magnetic random access memory, which comprises a writing accelerator, wherein the writing accelerator is positioned on the lower side of a bottom electrode and the upper side of a bottom electrode through hole of the magnetic random access memory, and is directly connected with the bottom electrode and the bottom electrode through hole.
The invention also provides a preparation method of the structure for optimizing the writing performance of the magnetic random access memory, which comprises the following steps:
the method comprises the following steps: providing a CMOS substrate with a polished surface and a metal connecting line Mx, wherein x is more than or equal to 1;
step two: manufacturing a bottom electrode through hole on the flattened CMOS substrate and grinding the bottom electrode through hole to be flat;
step three: patterning, defining and etching write accelerator metal on the bottom electrode through hole, filling a write accelerator dielectric, and grinding the write accelerator dielectric by adopting chemical mechanical planarization;
step four: and depositing a bottom electrode, a magnetic tunnel junction multilayer film and a top electrode on the writing accelerator in sequence, manufacturing a magnetic tunnel junction storage unit, and finally manufacturing a bit line connection on the top electrode.
On the basis of the common knowledge in the field, the above preferred conditions can be combined randomly to obtain the preferred embodiments of the invention.
The positive progress effects of the invention are as follows:
in an MRAM circuit, when a write operation is performed, the region of the Free Layer (FL) directly above the Write Accelerator (WA) preferentially forms a reversal domain that favors magnetization reversal, which rapidly nucleates, expands, and completes the magnetization reversal. Due to the introduction of the Writing Accelerator (WA), the switching speed of the magnetization vector from parallel to antiparallel or from antiparallel to parallel is greatly improved, namely: the task of writing a "0" or "1" in the MRAM memory cells can be performed more quickly, and the cache (e.g., SRAM) requirements can be met. Also, the power consumption of the device is lower due to the shorter time it takes to write data.
The structure for optimizing the writing performance of the Magnetic Random Access Memory (MRAM) and the preparation method thereof are particularly suitable for a Magnetic Tunnel Junction (MTJ) process (corresponding to a CMOS process node with the length of 20nm and above) with the length of more than 40nm, reduce the power consumption, improve the reading and writing speed, and can be used as a replacement scheme of a cache.
Drawings
FIG. 1: the invention provides a structure for optimizing the writing performance of a magnetic random access memory, which is a schematic diagram of magnetization vector reversal in the writing process.
FIG. 2: the invention provides a preparation method of a structure for optimizing the writing performance of a magnetic random access memory, which provides a schematic diagram of a substrate with a metal connecting wire Mx (x is more than or equal to 1) with a polished surface.
FIG. 3: the invention provides a preparation method of a structure for optimizing the writing performance of a magnetic random access memory, which is a schematic diagram after a bottom electrode through hole (BEV) is manufactured.
FIG. 4: the invention provides a method for manufacturing a structure for optimizing the write performance of a magnetic random access memory, which is a schematic diagram after a Write Accelerator (WA) is manufactured in a better embodiment.
FIG. 5: the invention provides a method for manufacturing a structure for optimizing the write performance of a magnetic random access memory, and in other preferred embodiments, the schematic diagram of a Write Accelerator (WA).
FIG. 6: in a preferred embodiment of the method for manufacturing a structure for optimizing write performance of a magnetic random access memory according to the present invention, a Bottom Electrode (BE), a Magnetic Tunnel Junction (MTJ), a Top Electrode (TE), and a bit line connection (BL) are illustrated after the fabrication is completed.
Shown in the figure: 31-Write Accelerator (WA), 42 a-reference layer, 42 b-barrier layer, 42 c-free layer, 100-surface polished substrate with CMOS metal link Mx (x ≧ 1), 110-metal link Mx (x ≧ 1) interlayer dielectric, 120-metal link Mx (x ≧ 1), 210-Bottom Electrode Via (BEV) etch stop layer, 220-Bottom Electrode Via (BEV) interlayer dielectric, 230-Bottom Electrode Via (BEV), 310-Write Accelerator (WA) metal, 320-Write Accelerator (WA) dielectric, 410-Bottom Electrode (BE), 420-Magnetic Tunnel Junction (MTJ), 430-Top Electrode (TE), 440-insulating cap layer, 450-Magnetic Tunnel Junction (MTJ) interlayer dielectric, 510-bit line connection (BL) interlayer dielectric and 520-bit line connection.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
An architecture for optimizing Magnetic Random Access Memory (MRAM) write performance, comprising: a Write Accelerator (WA) located at a lower side of a Bottom Electrode (BE) and an upper side of a Bottom Electrode through hole (BEV) of a Magnetic Random Access Memory (MRAM), that is, the Write Accelerator (WA) is located between and directly connected to the Bottom Electrode (BE) and the Bottom Electrode through hole (BEV).
Further, the Write Accelerator (WA) is generally much smaller in size than the Bottom Electrode (BE) and the Bottom Electrode Via (BEV) and may BE of any shape, and its position with respect to the Bottom Electrode (BE) and the Bottom Electrode Via (BEV) is adjustable.
In an MRAM circuit, when a write operation is performed, the region of the Free Layer (FL) directly above the Write Accelerator (WA) preferentially forms a reversal domain that favors magnetization reversal, which rapidly nucleates, expands, and completes the magnetization reversal.
Due to the introduction of the Writing Accelerator (WA), the switching speed of the magnetization vector from parallel to antiparallel or from antiparallel to parallel is greatly improved, namely: the task of writing a "0" or "1" in the MRAM memory cells can be performed more quickly, and the cache (e.g., SRAM) requirements can be met.
Also, the power consumption of the device is lower due to the shorter time it takes to write data.
Furthermore, since the size of the Write Accelerator (WA) is relatively small, a better local surface Roughness (RMS) can be obtained in the process of planarizing the WA, and in this case, a Barrier Layer (Tunnel Barrier Layer) with better quality can be obtained, which is beneficial to the improvement of tunneling magneto-resistivity (TMR) and the enhancement of reading performance.
In summary, the structure for optimizing the writing performance of the Magnetic Random Access Memory (MRAM) and the preparation method thereof provided by the invention are particularly suitable for a Magnetic Tunnel Junction (MTJ) process (corresponding to CMOS process nodes of 20nm and above) with a size larger than 40nm, reduce power consumption, improve the reading and writing speed, and can be used as a replacement scheme for a cache.
Fig. 1 is a schematic diagram illustrating a process of accelerating magnetization vector inversion in a Free Layer (FL)42c by introducing a reverse magnetic domain in the Free Layer (FL) by a Write Accelerator (WA)31 during writing according to an embodiment of the present invention for optimizing writing performance of a Magnetic Random Access Memory (MRAM).
More specifically, as shown at I in FIG. 1, when the MTJ is in the high resistance state (i.e., logic "1"), the magnetization vector of the Free Layer (FL)42c and the magnetization vector of the Reference Layer (RL)42a are anti-parallel.
As shown in FIG. 1 at II, in order to realize the inversion of the magnetization vector of the Free Layer (FL)42c, a current higher than the critical current density may BE passed through the upper end of the Free Layer (FL)42c (i.e., a current of non-spin-excited electrons is passed through the lower end of the Reference Layer (RL)42 a), and in order to accelerate the inversion of the magnetization vector of the Free Layer (FL)42c, a Write Accelerator (WA)31 is disposed at a position a below the Bottom Electrode (BE) and below the reference layer 42 a.
Further, the size of the Write Accelerator (WA)31 is much smaller than the Magnetic Tunnel Junction (MTJ), and the Write Accelerator (WA) may BE disposed at an arbitrary position below the Bottom Electrode (BE).
In this case, the electron flow passes through the Write Accelerator (WA)31, and first the reverse magnetic domains 1, 2 are produced in the Free Layer (FL) located directly above the Write Accelerator (WA)31, and then the reverse domains nucleate, expand, and complete the magnetization vector inversion.
After the magnetization vector is completely switched, the magnetization vectors of the Free Layer (FL)42c and the Reference Layer (RL)42c are parallel to each other, as shown in FIG. 1 at III, and the MTJ exhibits a low resistance state (i.e., a logical "0").
By the process I → III, writing from "1" to "0" is completed.
More specifically, as shown in IV, the magnetization vector of the Free Layer (FL)42c and the magnetization vector of the Reference Layer (RL)42a are parallel to each other when the MTJ is in a low resistance state (i.e., a logic "0").
As shown in V, in order to realize the inversion of the magnetization vector of the Free Layer (FL)42c, a current higher than the critical current density may BE passed through the lower end of the Reference Layer (RL)42a (i.e., a non-spin-excited electron current is passed through the upper end of the Free Layer (FL)42 c), and in order to accelerate the inversion of the magnetization vector of the Free Layer (FL)42c, the Write Accelerator (WA)31 is disposed at a position a below the Bottom Electrode (BE) and below the Reference Layer (RL)42 a.
Further, the size of the Write Accelerator (WA)31 is much smaller than the Magnetic Tunnel Junction (MTJ), and the Write Accelerator (WA) may BE disposed at an arbitrary position below the Bottom Electrode (BE).
Under this condition, a current passes through the Write Accelerator (WA)31, and first the reverse magnetic domains 3, 4 are produced in the Free Layer (FL) located directly above the Write Accelerator (WA)31, and then the reverse domains nucleate, expand, and complete magnetization vector inversion.
As shown in IV, after the magnetization vectors are completely switched, the magnetization vectors of the Free Layer (FL)42c and the Reference Layer (RL)42a are antiparallel, and the MTJ now assumes a high resistance state (i.e., a logic "1").
By the process IV → VI, the writing from "0" to "1" is completed.
By making the Write Accelerator (WA)31 much smaller than the Magnetic Tunnel Junction (MTJ) under the Magnetic Tunnel Junction (MTJ), it is advantageous to produce the reverse magnetic domain in the Free Layer (FL)42c, which accelerates the inversion of the magnetization vector of the Free Layer (FL)42c, reduces the writing time and power consumption, is very suitable for an MRAM circuit in which the MTJ size is 40nm or more, and is very advantageous to its application in a cache memory.
A method for preparing a structure for optimizing the writing performance of a Magnetic Random Access Memory (MRAM) comprises the following specific steps:
the method comprises the following steps: a surface-polished CMOS substrate 100 with metal interconnects Mx (x ≧ 1) is provided, and in FIG. 2, the metal interconnects Mx (x ≧ 1)120 is Cu.
Step two: in fig. 3, a bottom electrode via hole (BEV)230 is fabricated on the substrate 100 after the planarization process and ground flat.
Wherein the Bottom Electrode Via (BEV) etch stop layer 210 is SiON, SiN, SiC or SiCN, and the Bottom Electrode Via (BEV) interlayer dielectric 220 is SiO2SiON or Low dielectric constant (Low-K) dielectric.
Further, the Low dielectric constant (Low-k) dielectric refers to a material having a dielectric constant (k) lower than that of silicon dioxide (k ═ 3.9), and in the specific implementation, the Low-k material may be hydrogen Silicate (HSQ, k ═ 2.8 to 3.0), a mixed organosilicone Polymer (HOSP) film (k ═ 2.5 to 2.7) synthesized by combining Hydrogen Silicate (HSQ) and Methyl Silicate (MSQ) containing a Si-CH3 functional group, or a Porous SiOCH film (k ═ 2.3 to 2.7), or even a Porous Silicate (pors Silicate) Organic compound having an ultra-Low dielectric constant (k <2.0) and a Porous sio (k) < 1.9).
The Bottom Electrode Via (BEV)230 is made of W, and the formation method thereof is typically Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or Ion Beam Deposition (IBD). A layer of Ti/TiN is typically deposited as a diffusion barrier prior to deposition.
After depositing the BEV metal 230, the BEV metal is planarized by Chemical Mechanical Planarization (CMP) to the BEV via interlayer dielectric 220.
Step three: in fig. 4, a Write Accelerator (WA) metal 310 is patterned and etched over a Bottom Electrode Via (BEV)230, and then filled with a Write Accelerator (WA) dielectric 320 and planarized using Chemical Mechanical Planarization (CMP).
Wherein, in order to make the Write Accelerator (WA) metal 310 have a sufficient height, the depth of the W Bottom Electrode Via (BEV)230 is selectively etched to be 5nm to 40 nm.
In fig. 4(b) and 5, the size of the Write Accelerator (WA)31 is generally much smaller than the top opening of the Bottom Electrode Via (BEV)230, the pattern may be near the center of the Bottom Electrode Via (BEV)230 or may be off-center, and may be any shape that can be processed, such as: "●", "cyron", "|", "" l "," | "," "□", or "(".
Since the Write Accelerator (WA) metal 310 is fabricated directly by etching the Bottom Electrode Via (BEV)230, the material of the Write Accelerator (WA) metal 310 is also W.
The material of the Write Accelerator (WA) dielectric 320 is SiC, SiN or SiCN, typically by CVD deposition.
Furthermore, due to the relatively small size of the Write Accelerator (WA), a better local surface Roughness (RMS) can be obtained in the CMP process, and under such a condition, a barrier layer with higher quality can be obtained, which is beneficial to the improvement of tunneling Magneto-resistive Ratio (TMR) and the improvement of reading performance.
Step four: in fig. 6, a Bottom Electrode (BE)410, a Magnetic Tunnel Junction (MTJ)420 multilayer film, a Top Electrode (TE)430 are deposited and a Magnetic Tunnel Junction (MTJ)420 memory cell is fabricated, and finally a Bit Line (BL)520 connection is fabricated above the Top Electrode (TE) 430.
The bottom electrode 410 is made of Ti, TiN, Ta, TaN, W, WN, or a combination thereof, and is generally implemented by Physical Vapor Deposition (PVD), and after Deposition, the bottom electrode is usually planarized to achieve surface flatness for fabricating the magnetic tunnel junction.
The Magnetic Tunnel Junction (MTJ)420 multilayer film typically has a total thickness of 3nm to 30nm, and typically includes a sequential upward stack of a buffer Layer, a seed Layer, a synthetic antiferromagnetic Layer (SyAF), a lattice blocking Layer, a Reference Layer (RL), a Barrier Layer (BL), a Free Layer (FL), and a Capping Layer (CL).
(1) The Reference Layer (RL) has a thickness of 0.7nm to 1.5nm and is typically Co, Fe, Ni, CoFe, CoB, FeB, CoFeB, or a combination thereof.
(2) Further, below the Reference Layer (RL), a superlattice synthetic antiferromagnetic layer (SyAF) is fabricated, which has a structure generally [ Co/(Pt, Pd or Ni) ]]nCo/(Ru, Ir or Rh)/Co [ (Pt, Pd or Ni)/Co ]]m(where m.gtoreq.0, the thickness of the individual layers of Co, (Pt, Pd or Ni) and (Ru, Ir or Rh) is less than 1nm, further, the individual layers of Co and (Pt, Pd or Ni) may be below 0.5nm, such as 0.10nm, 0.15nm, 0.20nm, 0.25nm, 0.30nm, 0.35nm, 0.40nm, 0.45nm or 0.50nm, and the magnetic coupling between the Reference Layer (RL) and the synthetic antiferromagnetic layer (SyAF) is achieved by a lattice-blocking layer, typically Ta, W, Mo, Hf, Fe, Co (Ta, W, Mo or Hf), Fe (Ta, W, Mo or Hf), FeCo (Ta, W, Mo or Hf), or FeCoB (Ta, W, Mo or Hf).
(3) The Barrier Layer (BL) is a nonmagnetic metal oxide having a total thickness of 0.6 to 1.5nm, and MgO and Al are preferable2O3ZnO, MgZnO, MgBO or MgAlO, and further MgO may be selected.
(4) The Free Layer (FL) has a variable magnetic polarization and a total thickness of 1.1nm to 3nm, and generally comprises CoB, FeB, CoFeB, CoFe/CoFeB, Fe/CoFeB, CoFeB/(Ta, W, Mo, Hf)/CoFeB, Fe/CoFeB/(W, Mo, Hf)/CoFeB or CoFe/CoFeB/(W, Mo, Hf)/CoFeB, and further CoFeB/(W, Mo, Hf)/CoFeB, Fe/CoFeB/(W, Mo, Hf)/CoFeB or CoFe/CoFeB/(W, Mo, Hf)/CoFeB.
(5) Typically, after the Free Layer (FL) deposition, a Capping Layer (CL), typically (Mg, Al), is again deposited2O3ZnO, MgZnO, MgBO or MgAlO)/(W, Mo, Mg, Nb, Ru, Hf, V, Cr or Pt or their combination) double-layer structure, preferably, MgO/(W, Mo, Hf)/Ru or MgO/Pt/(W, Mo, Hf)/Ru structure may be selected. The superior effect of selecting MgO provides a source of additional interfacial anisotropy for the Free Layer (FL), thereby increasing thermal stability.
(6) The material of the insulating capping Layer (EL) 440 is typically SiC, SiON, SiCN or SiN, and is typically implemented by CVD or ALD.
(7) The Top Electrode (TE)430 has a thickness of 20nm to 100nm, and Ta, TaN, Ti, TiN, W or any combination thereof is selected to obtain a better etching profile in halogen plasma.
The material of the Magnetic Tunnel Junction (MTJ) interlayer dielectric 450 is typically SiO2SiON or Low dielectric constant (Low-k) dielectric; the bitline connection (BL)520 is Cu and typically a TaN/Ta diffusion barrier is deposited prior to deposition.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that these are by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.
Claims (10)
1. A structure for optimizing the writing performance of a magnetic random access memory is characterized by comprising a writing accelerator, wherein the writing accelerator is positioned on the lower side of a bottom electrode and the upper side of a bottom electrode through hole of the magnetic random access memory, and is directly connected with the bottom electrode and the bottom electrode through hole.
2. The structure for optimizing magnetic random access memory write performance of claim 1 wherein the write accelerator is smaller in size than the opening of the bottom electrode via.
3. The structure for optimizing the write performance of a magnetic random access memory according to claim 1, wherein during writing, when the magnetic tunnel junction is in a high resistance state, the magnetization vector of the free layer of the magnetic tunnel junction and the magnetization vector of the reference layer are antiparallel, a current greater than a critical current density is applied from the upper end of the free layer to realize the inversion of the magnetization vector of the free layer, and after the magnetization vectors are completely inverted, the magnetization vectors of the free layer and the reference layer are parallel to each other, and then the magnetic tunnel junction is in a low resistance state.
4. The structure for optimizing the write performance of a magnetic random access memory according to claim 1, wherein during the writing process of the magnetic random access memory, when the magnetic tunnel junction is in a low resistance state, the magnetization vector of the free layer of the magnetic tunnel junction and the magnetization vector of the reference layer are parallel to each other, a current larger than a critical current density is introduced from the lower end of the reference layer to realize the inversion of the magnetization vector of the free layer, and after the magnetization vectors are completely inverted, the magnetization vectors of the free layer and the reference layer are antiparallel, and then the magnetic tunnel junction is in a high resistance state.
5. The structure for optimizing magnetic random access memory write performance of claim 1 wherein the write accelerator is shaped to: "●", "cyron", "|", "" l "," | "," "□", or "(".
6. The method of claim 1, comprising the steps of:
the method comprises the following steps: providing a CMOS substrate with a polished surface and a metal connecting line Mx, wherein x is more than or equal to 1;
step two: manufacturing a bottom electrode through hole on the flattened CMOS substrate and grinding the bottom electrode through hole to be flat;
step three: patterning, defining and etching write accelerator metal on the bottom electrode through hole, filling a write accelerator dielectric, and grinding the write accelerator dielectric by adopting chemical mechanical planarization;
step four: and depositing a bottom electrode, a magnetic tunnel junction multilayer film and a top electrode on the writing accelerator in sequence, manufacturing a magnetic tunnel junction storage unit, and finally manufacturing a bit line connection on the top electrode.
7. The method according to claim 6, wherein in the second step, the bottom electrode via is made of W and formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition or ion beam deposition, and a Ti/TiN layer is deposited as a diffusion barrier layer before deposition; after depositing the bottom electrode through hole metal, grinding the bottom electrode through hole metal to a bottom electrode through hole interlayer dielectric by adopting a chemical mechanical polishing method.
8. The method for preparing a structure for optimizing the write performance of a magnetic random access memory according to claim 6, wherein in the third step, the material for etching the metal of the write accelerator is W, and the etching depth is 5nm to 40 nm; the material of the write accelerator dielectric is SiC, SiN or SiCN, which is achieved by means of chemical vapor deposition.
9. The method according to claim 6, wherein in the fourth step, the bottom electrode is made of Ti, TiN, Ta, TaN, W, WN or their combination by PVD.
10. The method according to claim 6, wherein in step four, after the bottom electrode is deposited, a chemical mechanical planarization process is selected to planarize the bottom electrode.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116723704A (en) * | 2023-08-09 | 2023-09-08 | 苏州凌存科技有限公司 | Magnetic random access memory and preparation method thereof |
Citations (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60124063A (en) * | 1983-12-08 | 1985-07-02 | Fujitsu Ltd | Reproduction system of magnet memory device |
| KR20010070246A (en) * | 2000-01-07 | 2001-07-25 | 아끼구사 나오유끼 | Magnetic element and magnetic memory device |
| CN1308317A (en) * | 1999-09-16 | 2001-08-15 | 株式会社东芝 | Magnetoresistive element and magnetic memory device |
| US20040165427A1 (en) * | 2003-02-20 | 2004-08-26 | Won-Cheol Jeong | Magnetic memories having magnetic tunnel junctions in recessed bit lines and/or digit lines and methods of fabricating the same |
| CN101430932A (en) * | 2007-11-06 | 2009-05-13 | 旺宏电子股份有限公司 | Method of programming cell in memory and memory apparatus utilizing the method |
| US20090251956A1 (en) * | 2008-04-03 | 2009-10-08 | Samsung Electronics Co., Ltd. | Magnetic random access memory devices, methods of driving the same and data writing and reading methods for the same |
| EP2249350A1 (en) * | 2009-05-08 | 2010-11-10 | Crocus Technology | Magnetic memory with a thermally assisted spin transfer torque writing procedure using a low writing current |
| CN102590669A (en) * | 2012-02-21 | 2012-07-18 | 复旦大学 | Method for measuring movement speed of ferroelectric thin film electric domain area and coercive field relationship |
| CN103021449A (en) * | 2011-09-26 | 2013-04-03 | 株式会社东芝 | Magnetic random access memory |
| CN103299370A (en) * | 2010-11-17 | 2013-09-11 | 纽约大学 | Bipolar spin-transfer switching |
| CN104795489A (en) * | 2015-04-20 | 2015-07-22 | 北京航空航天大学 | Novel four-port magnetic storage device |
| WO2016018503A1 (en) * | 2014-07-30 | 2016-02-04 | University Of South Florida | Magnetic memory physically unclonable functions |
| US20160163970A1 (en) * | 2014-12-05 | 2016-06-09 | Shanghai CiYu Information Technologies Co., LTD | Method for makinga magnetic random access memory element with small dimension and high qulity |
| CN105679784A (en) * | 2015-06-26 | 2016-06-15 | 上海磁宇信息科技有限公司 | Method for preparing peripheral conductive path of magnetic random access memory |
| CN106449970A (en) * | 2016-11-03 | 2017-02-22 | 北京航空航天大学 | Low-power-consumption magnetic storage unit |
| CN107017338A (en) * | 2015-12-31 | 2017-08-04 | 台湾积体电路制造股份有限公司 | Semiconductor structure and its forming method |
| CN107623014A (en) * | 2016-07-14 | 2018-01-23 | 上海磁宇信息科技有限公司 | A kind of preparation method of magnetic RAM |
| US20180097173A1 (en) * | 2016-09-30 | 2018-04-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory device having a single bottom electrode layer |
| CN108232002A (en) * | 2016-12-14 | 2018-06-29 | 上海磁宇信息科技有限公司 | A kind of method for preparing magnetic tunnel junction array |
| US20180212142A1 (en) * | 2017-01-24 | 2018-07-26 | Qualcomm Incorporated | Engineered barrier layer interface for high speed spin-transfer torque magnetic random access memory |
| CN109545957A (en) * | 2017-09-21 | 2019-03-29 | 上海磁宇信息科技有限公司 | A kind of manufacturing method of magnetic RAM cell array and peripheral circuit line |
| CN109545745A (en) * | 2017-09-21 | 2019-03-29 | 上海磁宇信息科技有限公司 | A kind of manufacturing method of magnetic RAM cell array and peripheral circuit line |
-
2019
- 2019-07-01 CN CN201910586552.8A patent/CN112186097B/en active Active
Patent Citations (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60124063A (en) * | 1983-12-08 | 1985-07-02 | Fujitsu Ltd | Reproduction system of magnet memory device |
| CN1308317A (en) * | 1999-09-16 | 2001-08-15 | 株式会社东芝 | Magnetoresistive element and magnetic memory device |
| KR20010070246A (en) * | 2000-01-07 | 2001-07-25 | 아끼구사 나오유끼 | Magnetic element and magnetic memory device |
| US20040165427A1 (en) * | 2003-02-20 | 2004-08-26 | Won-Cheol Jeong | Magnetic memories having magnetic tunnel junctions in recessed bit lines and/or digit lines and methods of fabricating the same |
| CN101430932A (en) * | 2007-11-06 | 2009-05-13 | 旺宏电子股份有限公司 | Method of programming cell in memory and memory apparatus utilizing the method |
| US20090251956A1 (en) * | 2008-04-03 | 2009-10-08 | Samsung Electronics Co., Ltd. | Magnetic random access memory devices, methods of driving the same and data writing and reading methods for the same |
| EP2249350A1 (en) * | 2009-05-08 | 2010-11-10 | Crocus Technology | Magnetic memory with a thermally assisted spin transfer torque writing procedure using a low writing current |
| CN103299370A (en) * | 2010-11-17 | 2013-09-11 | 纽约大学 | Bipolar spin-transfer switching |
| CN103021449A (en) * | 2011-09-26 | 2013-04-03 | 株式会社东芝 | Magnetic random access memory |
| CN102590669A (en) * | 2012-02-21 | 2012-07-18 | 复旦大学 | Method for measuring movement speed of ferroelectric thin film electric domain area and coercive field relationship |
| WO2016018503A1 (en) * | 2014-07-30 | 2016-02-04 | University Of South Florida | Magnetic memory physically unclonable functions |
| US20160163970A1 (en) * | 2014-12-05 | 2016-06-09 | Shanghai CiYu Information Technologies Co., LTD | Method for makinga magnetic random access memory element with small dimension and high qulity |
| CN104795489A (en) * | 2015-04-20 | 2015-07-22 | 北京航空航天大学 | Novel four-port magnetic storage device |
| CN105679784A (en) * | 2015-06-26 | 2016-06-15 | 上海磁宇信息科技有限公司 | Method for preparing peripheral conductive path of magnetic random access memory |
| CN107017338A (en) * | 2015-12-31 | 2017-08-04 | 台湾积体电路制造股份有限公司 | Semiconductor structure and its forming method |
| CN107623014A (en) * | 2016-07-14 | 2018-01-23 | 上海磁宇信息科技有限公司 | A kind of preparation method of magnetic RAM |
| US20180097173A1 (en) * | 2016-09-30 | 2018-04-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory device having a single bottom electrode layer |
| CN106449970A (en) * | 2016-11-03 | 2017-02-22 | 北京航空航天大学 | Low-power-consumption magnetic storage unit |
| CN108232002A (en) * | 2016-12-14 | 2018-06-29 | 上海磁宇信息科技有限公司 | A kind of method for preparing magnetic tunnel junction array |
| US20180212142A1 (en) * | 2017-01-24 | 2018-07-26 | Qualcomm Incorporated | Engineered barrier layer interface for high speed spin-transfer torque magnetic random access memory |
| CN109545957A (en) * | 2017-09-21 | 2019-03-29 | 上海磁宇信息科技有限公司 | A kind of manufacturing method of magnetic RAM cell array and peripheral circuit line |
| CN109545745A (en) * | 2017-09-21 | 2019-03-29 | 上海磁宇信息科技有限公司 | A kind of manufacturing method of magnetic RAM cell array and peripheral circuit line |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116723704A (en) * | 2023-08-09 | 2023-09-08 | 苏州凌存科技有限公司 | Magnetic random access memory and preparation method thereof |
| CN116723704B (en) * | 2023-08-09 | 2023-10-17 | 苏州凌存科技有限公司 | Magnetic random access memory and preparation method thereof |
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