CN105679784A - Method for preparing peripheral conductive path of magnetic random access memory - Google Patents
Method for preparing peripheral conductive path of magnetic random access memory Download PDFInfo
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- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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Abstract
The invention relate to a method for preparing high-quality peripheral conductive path (ECM, Electrical Conducting Means) in a nanoscale magnetic random access memory (MRAM). The EMC has high conductivity and can stop Cu electromigration. A diffusion barrier layer (DBL, Diffusion Barrier Layer) and an adhesion enhancement layer (AEL, Adhesion Enhancement Layer) can adopt appropriate materials to obtain MRAM devices with high reliability. To further decrease the total thickness of the DBL and the AEL, a Single-layer alloyed diffusion barrier layer (ADBL, Alloyed Diffusion Barrier Layer). A material of the ADBL can be selected from Co, Ru or Cr alloy, and other elements of the alloy can be selected from W, Ti, Pt, Rd, Hf, Nb, Zr, and V, wherein the content of these elements is 5%-40%.
Description
Technical field
The present invention relates to a kind of method preparing the high-quality magnetic RAM surrounding conductive path of nano-scale.
Background technology
In recent years, adopt MTJ (MTJ, magnetic RAM (the MRAM of magneto-resistance effect MagneticTunnelJunction), MagneticRandomAccessMemory) being it is believed that it is follow-on solid state non-volatile memory body, it has the feature of high-speed read-write, Large Copacity and low energy consumption. Ferromagnetism MTJ is generally sandwich structure, wherein has memory layer, and it can change the direction of magnetization to record different data; The tunnel barrier layer of centrally located insulation; Reference layer, is positioned at the opposite side of tunnel barrier layer, and its direction of magnetization is constant.
For recording information in magnetoresistive element, it is possible to adopting spin momentum transfer or claim the principle of spin moment transfer (STT, SpinTransferTorque), carrying out write operation, this type of MRAM is also referred to as STT-MRAM. According to the method, magnetoresistive element applies spin polarized current and overturns the direction of magnetization of memory layer. Additionally, along with the magnetic material volume constituting memory layer diminishes, write operation needs the spin polarized current injected to diminish too. Therefore, this write method can realize device miniaturization simultaneously and reduce electric current.
Difference according to the direction of magnetization, STT-MRAM is subdivided in face STT-MRAM (iSTT-MRAM, in-planeSTT-MRAM), and vertical STT-MRAM (pSTT-MRAM, perpendicularSTT-MRAM), it is preferable that pSTT-MRAM. Owing to switching electric current reduces with the reduction of MTJ element size, so under state-of-the-art Technology, pSTT-MRAM is meeting more potentiality in size scale. Therefore, peripheral circuit reduces just particularly important with the synchronization of mnemon size, for instance bottom CMOS control circuitry, hearth electrode and the top electrode that through hole (VIA) connects. Regrettably, more little peripheral circuit size, cause bigger non-essential resistance Rext, inevitably reduce tunneling magnetic resistance (TMR, TunnelingMagnetoresistance), TMR=Δ R/ (RMTJ+Rext), wherein RMTJResistance for MTJ itself. So desirable pSTT-MRAM, RextAccomplish little as much as possible.
When MRAM live width is reduced to 20nm or is less, internal memory run duration is due to electron transfer (EM, ElectronMigration) component failure caused by will become a severe problem, particularly in write operation process, need relatively larger spin polarized current, produce sufficiently large spin-transfer torque, to change the polarization state of memory layer. EM is that it is based on the momentum transfer between conduction electronics and the metallic atom dispersed by the dislodgment that slowly motion is caused of conductor intermediate ion. EM can reduce the reliability of MRAM chip, may result in connection open circuit or component failure.
There is multiple method can prevent or reduce EM. Such as, a kind of method is one layer of thin seed of insertion between substrate and relevant layers, is commonly referred to " glue-line ". In current MRAM manufactures, the conduction pattern of periphery electric current, such as VIA, hearth electrode and top electrode, the structure of TaN/Ta/Cu/Ta/TaN (or TiN/Ti/Cu/Ti/TiN) can be adopted, wherein TaN (or TiN) 002 is as Cu atoms permeating trapping layer, to stop it to diffuse to the SiO2 electrolyte of periphery 001, Ta (or Ti) 003 then as the Seed Layer of leading electric material Cu004 or glue-line, as shown in Figure 1. Although this method can be applicable to the MRAM device of bigger live width technique, but the then poor effect when live width is reduced to 20nm or is less, now line need stream super-high-current to switch the magnetization state of memory layer, owing to needing Ta (or Ti) Seed Layer of certain thickness (more than 5nm), thus the selectable leeway of Cu thickness is just smaller. Therefore it is generally desirable to have Seed Layer one layer very thin between TaN and Cu, take electric material Cu as the leading factor and reserve bigger thickness space, so that the periphery electric current guide passage of MRAM device has less resistance and less EM.
Summary of the invention
The present invention is about in the MRAM of nano-scale, the method preparing high-quality surrounding conductive path (ECM, ElectricalConductingMeans), has high conductivity and better stops Cu electromigration. By diffusion trapping layer (DBL, DiffusionBarrierLayer) and adhesion enhancement layers (AEL, AdhesionEnhancementLayer) are selected suitable material, it is possible to obtain the MRAM device that reliability is high. For lowering the gross thickness of DBL and AEL further, it is possible to adopt single layer alloy diffusion trapping layer (ADBL, AlloyedDiffusionBarrierLayer). ADBL material is selected from the alloy of Co, Ru or Cr, and other element of alloy is selected from W, Ti, Pt, Rd, Hf, Nb, Zr, V, and the content of these elements is between 5% to 40%.
In conventional semiconductor processing, being prepared by after its CMOS control circuitry is formed of MRAM core devices. First, form VIA and connect bottom cmos circuit, then hearth electrode (BE is formed, BottomElectrode), Magnetic Memory unit (MMU, and top electrode (TE, TopElectrode), and all of periphery guide passage MagneticMemoryUnit), this guide passage takes electric channel as the leading factor with Cu, and by DBL/AEL double-deck by encirclement.
The following detailed description is merely illustrative in itself, is not limited to the embodiment of this theme, or the application of this type of embodiment and use. Any scheme described herein, is merely illustrative of, it is not necessary to be construed as advantageous over or benefit other scheme. Further, be not limited to prior art, background, brief summary or described in detail below in any theory expressed or imply.
Accompanying drawing explanation
The conductive channel that Fig. 1 is the MRAM device in currently existing technology is arranged, and has VIA and TaN/Ta/Cu/Ta/TaN structure;
Fig. 2 A is that SiO2 electrolyte covers bottom MRAM device control circuit (not shown);
Fig. 2 B opens VIA in SiO2 electrolyte;
Fig. 2 C is formed to surround the DBL of VIA hole wall in SiO2 electrolyte;
Fig. 2 D is that the DBL surface surrounding VIA hole wall in SiO2 electrolyte forms AEL;
Fig. 2 E is optional VIA structure, eliminates DBL and the AEL of bottom;
Fig. 2 F is that VIA passes through plating filling Cu in VIA, is used as leading electric pathway;
Fig. 2 G deposits BE at VIA top surface, and it has DBL/AEL/Cu/AEL/DBL thin film stack;
Fig. 2 H forms BE pattern by photoetching and etching;
Fig. 2 I is optional BE structure, and the open edge DBL/AEL of the BE exposed covers;
Fig. 2 J is filling SiO2 electrolyte in the BE region being etched away, again through cmp planarization top surface;
Fig. 2 K deposits MTJ stacks of thin films at BE surface crown;
Fig. 2 L is MTJ patterning, and etching forms independent mnemon, and the edge of its exposure SiN passivation layer is protected;
Fig. 2 M is filling SiO2 electrolyte in the MTJ region being etched away, again through cmp planarization top surface;
Fig. 2 N forms TE at MTJ stack top, and its structure is DBL/AEL/Cu/AEL/DBL;
Fig. 2 O is optional MTJ cell structure, and its BE edge DBL/AEL protects, and the DBL/AEL bottom VIA is removed;
Fig. 2 P is formed to surround the ADBL of VIA hole wall in SiO2 electrolyte;
Fig. 2 Q deposits BE at VIA top surface, and its structure is ADBL/Cu/ADBL;
Fig. 2 R forms TE at MTJ stack top, and its structure is ADBL/Cu/ADBL.
Detailed description of the invention
There are some researches show recently, in the IC of 20nm or less live width manufactures, substitute Ta Seed Layer with Co liner and can improve the electromigration lifetime (referring to AppliedMaterials website: www.appliedmaterials.com/products/endura-volta-cvd-cobal t) of Cu. In the present invention, we adopt Co and other material as adhesion enhancement layers, to improve the surrounding conductive path in MRAM preparation.
Below in conjunction with accompanying drawing, two exemplary embodiments are elaborated. Accompanying drawing is schematic diagram or concept map, the relation between each several part thickness and width, and the proportionate relationship etc. between each several part, not completely the same with its actual value.
Embodiment one
This processing step:
First pass through chemical vapour deposition (CVD) (CVD, ChemicalVaporDeposition) on Manufactured MRAM control circuit (not shown), deposit SiO2 dielectric layer 100, as shown in Figure 2 A;
VIA hole 200 is formed, as shown in Figure 2 B by photoengraving pattern etching;
Then, by CVD, ald (ALD, AtomicLayerDeposition) or physical vapour deposition (PVD) (PVD, PhysicalVaporDeposition) DBL210 is formed, cover the abutment wall of VIA, by the SiO2 dielectric separates of VIA Yu surrounding, as shown in Figure 2 C;
After DBL is formed, form AEL220 by CVD, ALD or PVD immediately, cover DBL surface, oxygen-free in depositing operation, as shown in Figure 2 D;
Optional step: carry out the etching of vertical direction to remove the bottom of DBL/AEL, as shown in Figure 2 E;
Then, the leading electric channel 200 of electrochemistry plating Cu, to be filled up completely with whole VIA, as shown in Figure 2 F;Before plating Cu, between the leading electric channel of AEL and Cu, may be inserted into Cu Seed Layer, to obtain better Cu coating (not shown).
Above-mentioned with SiO2 for electrolyte, taking as the leading factor with Cu in the VIA technique of electric channel, the material of selecting properly DBL and AEL is most important, and it is based on following principle: set the interface energy respectively γ of each interlayerSiO2-DBL、γSiO2-Cu、γDBL-AEL、γDBL-Cu、γAEL-Cu, then a stable SiO2/ DBL/AEL/Cu need to meet γSiO2-DBL>γDBL-AEL>γAEL-Cu>γDBL-Cu>γSiO2-Cu. It can be pure Co, Ru, Cr or their alloy that DBL is selected from the material of TaN or TiN, AEL, and other element of alloy is selected from W, Pt, Rd, Ta, Ti, Hf, Ag, Nb, Zr, V, Si, and above-mentioned constituent content is 5%～40%. AEL after alloy is usually without the amorphous state of crystal boundary or nano crystal material, and it is finer and close, firmer, is more conducive to resist the diffusion of Cu atom.
After VIA is formed, being formed the stacks of thin films of BE300 by PVD or CVD, its deposition order is DBL310/AEL320/Cu330/AEL320/DBL310, and namely the Cu surface at bottom and top is all protected by DBL/AEL, as shown in Figure 2 G. For the PVD of TaN (or TiN), target both can be pure Ta (or Ti), it is also possible to be TaN (or TiN), and the gas of sputtering is Ar+N2Mixing gas. Then pass through photoetching and form BE pattern with etching, as illustrated in figure 2h.
Optional step: in order to protect the edge come out, it is possible to deposit DBL310/AEL320 on its edge, as shown in figure 2i.
It is subsequently filled SiO2 dielectric layer 340, with the region that covering is etched, and adopts cmp (CMP, ChemicalMechanicalPolishing) to planarize BE end face, as shown in fig. 2j.
After BE is formed, under fine vacuum conditional, in the stacks of thin films of the deposited atop MMU400 on BE surface. First pass through sputtering to clean BE surface, then deposit MTJ Seed Layer, Magnetic memory layer 410, oxide tunneling layers 420, magnetic reference layer 430, surface cover and hard mask layer, as shown in figure 2k. The position of memory layer and reference layer can also overturn, thus obtaining being called the MRAM of top pinning type.
Optional step: MTJ film stack can be annealed after deposition immediately, it is also possible to is annealed in follow-up phase.
Then, MTJ stacks of thin films pattern is formed by photoetching with multistep etching, thus forming memory cylinder. In order to protect the MTJ edge exposed; form SiN passivation layer 435 by CVD and surround with the surface of etching, as shown in figure 2l, be again filled with SiO2 electrolyte 440 in the region removed that is etched subsequently; and by CMP, top surface is planarized, as shown in figure 2m.
In order to form complete conductive channel, forming top electrode TE500 at the top of MMU, its stacked structure is DBL510/AEL520/Cu530/ARL520/DBL510, as shown in Fig. 2 N and 2O. The wire pattern (not shown) of TE is formed again through photoetching and etching.
Embodiment two
Although above-mentioned double-decker (DBL and AEL) has good protective capability, but the thickness of its stacks of thin films is still not enough little of being adapted to following extreme technique live width (tending to 10nm or less). For this, it is possible to adopt ADBL, substituting the DBL/AEL structure of bilayer, ADBL both may be used for diffusion to be stoped, it is also possible to be used for adhering to enhancing. Such as the alloy of Co, Ru or Cr, in this alloy, the material for spreading prevention is selected from W, Ti, Pt, Rd, Hf, Nb, Zr, V, and content is 5%～40%, and need to meet γSiO2-ADBL>γADBL-Cu>γSiO2-Cu., usually without the amorphous state of crystal boundary or nano crystal material, it is finer and close, firmer, is more conducive to resist the diffusion of Cu atom for ADBL after alloy (even if its thickness is 5nm and following). ADBL can be prepared by ALD or CVD, oxygen-free in the raw material of its reactant. VIA can adopt the similar technique in embodiment one; Before plating Cu, it is possible to form Cu Seed Layer and cover ADBL. For BE and TE, it is possible to complete to be formed the whole depositing operation of ADBL/Cu/ADBL by PVD or CVD.
It is simpler, narrower that the conductive path adopting ADBL, MRAM can do, and as shown in Fig. 2 P, 2Q, 2R, 215 is wherein ADBL in VIA, 315 is ADBL in BE, 515 is ADBL in TE.
Then on silicon chip, pin formation, device passivation and various heat treatment are proceeded, to form stable MRAM operational module. In above-described each embodiment, established device needs to be annealed at the temperature of 300 DEG C～400 DEG C, so that Cu backflow, to fill space and crystal boundary, makes DBL/AEL or ADBL can realize better EM protection.
Claims (18)
1. the method preparing magnetic RAM conductive path, it is characterised in that described conductive path is set and includes:
Diffusion trapping layer;
Adhesion enhancement layers; And
The leading electric channel of Cu surrounded by described diffusion trapping layer and described adhesion enhancement layers.
2. the method for claim 1, it is characterised in that described diffusion trapping layer includes metal nitride, the thickness≤6nm of described metal nitride, formed by chemical vapour deposition (CVD), ald or physical vapour deposition (PVD).
3. the method for claim 1, it is characterised in that described adhesion enhancement layers includes the A that pure materials A or itself and material B are formed1-xBxAlloy, A is selected from Co, Ru, Cr, B is selected from W, Pt, Rd, Ta, Ti, Hf, Ag, Nb, Zr, V, Si, the scope of x is 5%～40%, formed by ald, chemical vapour deposition (CVD) or physical vapour deposition (PVD) by oxygen-free A or B raw material, the thickness≤6nm of described adhesion enhancement layers.
4. the method for claim 1, it is characterised in that the leading electric channel of described Cu includes the pure Cu formed by electrochemical plating, physical vapour deposition (PVD) or chemical vapour deposition (CVD).
5. the method for claim 1, it is characterised in that described conductive path also includes:
The through hole of electrical connection bottom device control circuit;
The hearth electrode of described via top;
Top electrode above described hearth electrode; And
The Magnetic memory unit of the mram devices being arranged between described hearth electrode and described top electrode.
6. method as claimed in claim 5, it is characterised in that the preparation of described through hole includes:
Forming diffusion trapping layer one, the SiO2 electrolyte of the sidewall of described through hole Yu surrounding is separated by described diffusion trapping layer one;
Forming adhesion enhancement layers one, described adhesion enhancement layers one covers described diffusion trapping layer one;
Forming Cu Seed Layer, described Cu Seed Layer covers described adhesion enhancement layers one; And
Described through hole is formed the leading electric channel one of described Cu.
7. method as claimed in claim 5, it is characterised in that the preparation of described hearth electrode includes:
Diffusion trapping layer two is formed in described via top;
Adhesion enhancement layers two is formed at described diffusion trapping layer two top;
The leading electric channel two of Cu is formed at described adhesion enhancement layers two top;
The second adhesion enhancement layers two is formed at leading electric channel two top of described Cu;
The second diffusion trapping layer two is formed at described second adhesion enhancement layers two top;
Photoetching and etching is adopted to form the pattern of described hearth electrode;
Chemical vapour deposition (CVD) SiO2Electrolyte covers the hearth electrode patterned; And
Cmp is to planarize hearth electrode top surface.
8. method as claimed in claim 5, it is characterised in that described Magnetic Memory unit includes:
Being arranged on the Magnetic memory layer on described hearth electrode, it has variable magnetization direction;
Being arranged on the magnetic reference layer under described top electrode, it has fixing magnetization direction; And
Tunnel barrier layer, it is arranged between described Magnetic memory layer and described magnetic reference layer.
9. method as claimed in claim 5, it is characterised in that described Magnetic Memory unit includes:
Being arranged on the magnetic reference layer on described hearth electrode, it has fixing magnetization direction;
Being arranged on the Magnetic memory layer under described top electrode, it has variable magnetization direction; And
Tunnel barrier layer, it is arranged between described Magnetic memory layer and described magnetic reference layer.
10. method as claimed in claim 5, it is characterised in that the preparation of described Magnetic Memory unit includes:
The hearth electrode top surface of fine vacuum sputter clean cmp;
Physical vapour deposition (PVD) Seed Layer, described Magnetic Memory unit and surface cover successively;
Photoetching and etching is adopted to form the pattern of described Magnetic Memory unit;
Chemical vapour deposition (CVD) SiN wraps up the Magnetic Memory unit being etched;
Chemical vapour deposition (CVD) SiO2Electrolyte covers whole Magnetic Memory unit; And
Cmp SiO2To planarize top surface and to expose described Magnetic Memory unit.
11. method as claimed in claim 5, it is characterised in that the preparation of described top electrode includes:
Described Magnetic Memory unit top and around SiO2Dielectric surface forms diffusion trapping layer three;
Adhesion enhancement layers three is formed at described diffusion trapping layer three top;
The leading electric channel three of Cu is formed at described adhesion enhancement layers three top;
The second adhesion enhancement layers three is formed at leading electric channel three top of described Cu;
The second diffusion trapping layer three is formed at described second adhesion enhancement layers three top;
Photoetching and etching is adopted to form the pattern of described top electrode; And
Chemical vapour deposition (CVD) SiO2Electrolyte covers the top electrode patterned.
12. the method preparing magnetic RAM conductive path, it is characterised in that described conductive path is set and includes:
Alloy diffusion trapping layer, it is formed by chemical vapour deposition (CVD), ald or physical vapour deposition (PVD), and the raw material of the alloy diffusion trapping layer used in processing is oxygen-free;
Being surrounded the leading electric channel of Cu by alloy diffusion trapping layer, it is formed by electrochemical plating or chemical vapour deposition (CVD).
13. method as claimed in claim 12, it is characterised in that described alloy diffusion trapping layer is alloy CoDx、RuDxOr CrDx, thickness≤6nm, D is selected from W, Ti, Pt, Rd, Hf, Nb, Zr, V, Si, and the scope of x is 5%～40%.
14. method as claimed in claim 12, it is characterised in that described conductive path also includes:
The through hole of electrical connection bottom device control circuit;
The hearth electrode of described via top;
Top electrode above described hearth electrode; And
The Magnetic memory unit of the mram devices being arranged between described hearth electrode and described top electrode.
15. method as claimed in claim 14, it is characterised in that the preparation of described through hole includes:
Forming alloy diffusion trapping layer one, the SiO2 electrolyte of the sidewall of described through hole Yu surrounding is separated by described diffusion trapping layer one;
Form Cu Seed Layer; And
Form the leading electric channel one of Cu, to fill whole cavities of the described through hole surrounded by described alloy diffusion trapping layer one.
16. method as claimed in claim 14, it is characterised in that the preparation of described hearth electrode includes:
Alloy diffusion trapping layer two is formed in described via top;
The leading electric channel two of Cu is formed at described alloy diffusion trapping layer two top;
The second alloy diffusion trapping layer two is formed at leading electric channel two top of described Cu;
Photoetching and etching is adopted to form the pattern of described hearth electrode;
Chemical vapour deposition (CVD) SiO2Electrolyte covers the hearth electrode patterned; And
Cmp is to planarize hearth electrode top surface.
17. method as claimed in claim 14, it is characterised in that the preparation of described top electrode includes:
Described Magnetic Memory unit top and around SiO2Dielectric surface forms alloy diffusion trapping layer three;
The leading electric channel three of Cu is formed at described alloy diffusion trapping layer three top;
The second alloy diffusion trapping layer three is formed at leading electric channel three top of described Cu;
Photoetching and etching is adopted to form the pattern of described top electrode; And
Chemical vapour deposition (CVD) SiO2Electrolyte covers the top electrode patterned.
18. the method as described in as arbitrary in claim 1-17, it is characterised in that the conductive path of established magnetic RAM is annealed at 300 DEG C～400 DEG C, so that Cu backflow, to fill all spaces and crystal boundary produced in described conductive path forming process.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108232010A (en) * | 2016-12-21 | 2018-06-29 | 上海磁宇信息科技有限公司 | A kind of method of gas cluster ion beam planarization magnetic tunnel junction hearth electrode |
| CN109216540A (en) * | 2017-06-30 | 2019-01-15 | 中电海康集团有限公司 | MTJ device and its production method |
| CN112186097A (en) * | 2019-07-01 | 2021-01-05 | 上海磁宇信息科技有限公司 | Structure for optimizing write performance of magnetic random access memory and preparation method thereof |
| CN112864309A (en) * | 2019-11-12 | 2021-05-28 | 上海磁宇信息科技有限公司 | Magnetic tunnel junction structure and magnetic random access memory thereof |
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| CN109216540A (en) * | 2017-06-30 | 2019-01-15 | 中电海康集团有限公司 | MTJ device and its production method |
| CN112186097A (en) * | 2019-07-01 | 2021-01-05 | 上海磁宇信息科技有限公司 | Structure for optimizing write performance of magnetic random access memory and preparation method thereof |
| CN112186097B (en) * | 2019-07-01 | 2023-10-27 | 上海磁宇信息科技有限公司 | Structure for optimizing writing performance of magnetic random access memory and preparation method thereof |
| CN112864309A (en) * | 2019-11-12 | 2021-05-28 | 上海磁宇信息科技有限公司 | Magnetic tunnel junction structure and magnetic random access memory thereof |
| CN112864309B (en) * | 2019-11-12 | 2022-11-08 | 上海磁宇信息科技有限公司 | Magnetic tunnel junction structure and magnetic random access memory thereof |
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