CN112086555B - Method for preparing magnetic tunnel junction cell array - Google Patents
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- H10N50/00—Galvanomagnetic devices
- H10N50/10—Magnetoresistive devices
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- H10N50/00—Galvanomagnetic devices
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Abstract
The invention relates to a method for preparing a magnetic tunnel junction cell array, which comprises the following specific steps: providing a CMOS substrate with a polished surface and a metal connection line Mx; step two, manufacturing a bottom electrode through hole after etching on the CMOS substrate after planarization treatment; depositing BEV and BE deposited metals to form BEV metal filling and BE metal, and flattening the BE metal to enable the BE metal to meet the requirement of depositing the MTJ multilayer film; and fourthly, depositing a magnetic tunnel junction and a top electrode on the flattened BE metal, graphically defining a magnetic tunnel junction pattern, etching the top electrode, the magnetic tunnel junction and the BE metal, and depositing an insulating cover layer around the outer parts of the top electrode, the magnetic tunnel junction and the BE metal after etching.
Description
Technical Field
The invention relates to the technical field of manufacturing of magnetic random access memories (MRAM, magnetic Radom Access Memory), in particular to a method for preparing a magnetic tunnel junction cell array.
Background
In recent years, MRAM using magnetic tunnel junctions (MTJ, magnetic Tunnel Junction) has been considered as a future solid-state nonvolatile memory, which has characteristics of high-speed reading and writing, large capacity, and low power consumption. Ferromagnetic MTJs are typically sandwich structures with a magnetic memory layer that can change the magnetization direction to record different data; an insulating tunnel barrier layer located in the middle; and the magnetic reference layer is positioned on the other side of the tunnel barrier layer, and the magnetization direction of the magnetic reference layer is unchanged.
In order to be able to record information in such magnetoresistive elements, a writing method based on spin momentum transfer or spin transfer Torque (STT, spin Transfer Torque) switching technology is proposed, such MRAM being called STT-MRAM. STT-MRAM is in turn divided into in-plane STT-MRAM and perpendicular STT-MRAM (i.e., pSTT-MRAM), which have better performance, depending on the direction of the magnetic polarization. In this way, the magnetization direction of the magnetic memory layer can be reversed by supplying spin-polarized current to the magnetoresistive element. In addition, as the volume of the magnetic memory layer is reduced, the spin-polarized current to be injected for writing or switching operations is also smaller. Thus, this writing method can achieve both device miniaturization and current reduction.
Meanwhile, since the switching current required for reducing the size of the MTJ element is also reduced, the dimension pSTT-MRAM can be well matched to the most advanced technology node. It is therefore desirable to make pSTT-MRAM devices of very small dimensions, with very good uniformity, and with minimal impact on MTJ magnetic properties, and to employ fabrication methods that also achieve Gao Liang rates, high accuracy, high reliability, low power consumption, and maintain a temperature coefficient suitable for good data storage. Meanwhile, the write operation in the nonvolatile memory is based on the resistance state change, so that it is necessary to control the damage and shortening of the life of the MTJ memory device caused thereby. However, the fabrication of a small MTJ element may increase the variation in MTJ resistance, so that the write voltage or current of pSTT-MRAM may also be greatly varied, which may impair the performance of MRAM.
In current MRAM fabrication processes, fabrication directly on surface polished CMOS VIAs (VIA) is typically employed, with MTJ patterns aligned with VIA patterns. However, when performing chemical mechanical planarization (CHEMICAL MECHANICAL Polarization, CMP) on patterned CMOS vias, the surface flatness is not as good as that required to fabricate Magnetic Tunnel Junctions (MTJ) due to the presence of butterfly defects (Dishing).
Disclosure of Invention
The present invention is directed to a method for fabricating a magnetic tunnel junction cell array, which solves the problem of the conventional MRAM fabrication process, and generally employs directly fabricating on a surface-polished CMOS VIA (VIA), and aligning MTJ patterns with VIA patterns. However, when performing chemical mechanical planarization (CHEMICAL MECHANICAL Polarization, CMP) on patterned CMOS vias, the surface flatness is not as good as required to fabricate Magnetic Tunnel Junctions (MTJ) due to the presence of butterfly defects (Dishing).
In order to achieve the above purpose, the present invention provides the following technical solutions: a method for preparing a magnetic tunnel junction cell array comprises the following specific steps:
providing a CMOS substrate with a polished surface and a metal connection line Mx, wherein x is more than or equal to 1;
Step two, manufacturing a bottom electrode through hole after etching on the CMOS substrate after planarization treatment;
Depositing bottom electrode through holes (Bottom Electrode Via, BEVs) and bottom electrode (Bottom Elctrode, BE) metals to form BEV metal filling and BE metal, and flattening the BE metal to enable the BE metal to meet the requirement of depositing the MTJ multilayer film;
And fourthly, depositing a magnetic tunnel junction and a top electrode on the flattened BE metal, graphically defining a magnetic tunnel junction pattern, etching the top electrode, the magnetic tunnel junction and the BE metal, and depositing an insulating cover layer around the outer parts of the top electrode, the magnetic tunnel junction and the BE metal after etching.
Compared with the prior art, the invention has the following beneficial effects:
a method for preparing a magnetic tunnel junction cell array of the invention is to manufacture a W Bottom Electrode via (Bottom Electrode Via, BEV), a W Bottom Electrode (BE), a Magnetic Tunnel Junction (MTJ) and a Top Electrode (TE) on a surface polished CMOS metal wire, and sequentially and upwardly superimpose and align BEV, BE, MTJ and TE.
More specifically, BEV fill metal and BE deposit metal are deposited once and after the deposition is completed, CMP planarized, and then a Magnetic Tunnel Junction (MTJ) and top electrode film layer are deposited on the CMP processed BE.
As the BEV opening is not required to BE ground in the execution process of the CMP process after the BEV and BE metals are deposited, the butterfly-shaped defect (Dishing) is effectively avoided, and meanwhile, the BEV and BE metals are deposited once, the magnetic performance, the electrical performance and the yield of the MTJ unit structure are obviously improved greatly, and the production cost is reduced.
Drawings
FIG. 1 is a schematic diagram of a CMOS substrate structure for a method of fabricating an array of magnetic tunnel junction cells according to the present invention;
FIG. 2 is a schematic diagram of a structure after BEV etching in accordance with one method of the present invention for fabricating an array of magnetic tunnel junction cells;
FIG. 3 is a schematic diagram of a structure after BEV and BE metals are deposited in accordance with one method of fabricating an array of magnetic tunnel junction cells of the present invention;
FIG. 4 is a graph of PH-P Redox during a mechanical planarization (CMP) process for BE metal in accordance with one method of fabricating an array of magnetic tunnel junction cells in accordance with the present invention;
FIG. 5 is a schematic diagram of the structure of a method of fabricating an array of magnetic tunnel junction cells according to the present invention after BEV and BE metals are deposited.
FIG. 6 is a schematic diagram of a method of fabricating an array of magnetic tunnel junction cells according to the present invention, after deposition of Magnetic Tunnel Junctions (MTJs) and Top Electrodes (TE).
FIG. 7 is a schematic diagram of a method of fabricating an array of magnetic tunnel junction cells according to the present invention after etching the Top Electrode (TE), the Magnetic Tunnel Junction (MTJ) and the Bottom Electrode (BE).
Fig. 8 is a schematic diagram of a method of fabricating an array of magnetic tunnel junction cells according to the present invention after deposition of an insulating cap layer.
In the figure: 1. a CMOS substrate; 101. a metal wiring Mx (x is more than or equal to 1) interlayer dielectric; 102. metal connection Mx (x is more than or equal to 1); 2. BEV etch barrier; 3. BEV interlayer dielectrics; 4. BEV after etching; 5. BEV metal diffusion barriers; 6. BEV and BE deposit metals; 7. BEV metal filling; 8. a BE metal; 9. a Magnetic Tunnel Junction (MTJ) buffer/seed layer; 10. a Magnetic Tunnel Junction (MTJ); 11. a top electrode TE; 12. an insulating cover layer.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1-8, the present invention provides a technical solution: a method of fabricating a magnetic tunnel junction cell array includes a CMOS substrate 1, a metal interconnect Mx (x.gtoreq.1) interlayer dielectric 101, a metal interconnect Mx (x.gtoreq.1) 102, a BEV etch stop layer 2, a BEV interlayer dielectric 3, a BEV4 after etching, a BEV metal diffusion stop layer 5, BEV and BE deposited metal 6, a BEV metal fill 7, a BE metal 8, a Magnetic Tunnel Junction (MTJ) buffer/seed layer 9, a Magnetic Tunnel Junction (MTJ) 10, a Top Electrode (TE) 11, and an insulating cap layer 12. A BEV etch stop layer 2 is deposited over the CMOS substrate 1, a BEV interlayer dielectric 3 is deposited over the BEV etch stop layer 2, a BEV metal diffusion stop layer 5 is disposed over the outer wall of the BEV interlayer dielectric 3, BEV4 after etching is distributed over the BEV metal diffusion stop layer 5, BEV and BE deposition metal 6 are distributed inside the BEV4 after etching, BEV metal fill 7 is covered in the recess of the BEV4 after etching, BE metal 8 is covered on top of the BEV interlayer dielectric 3, and a Magnetic Tunnel Junction (MTJ) buffer/seed layer 9 is deposited over the BE metal 8, a Magnetic Tunnel Junction (MTJ) 10 is deposited over the Magnetic Tunnel Junction (MTJ) buffer/seed layer 9, a top electrode TE11 is deposited over the Magnetic Tunnel Junction (MTJ) 10, and an insulating cover layer 12 is deposited over the top electrode TE 11.
The method comprises the following specific steps:
The CMOS substrate (1) comprises a metal wire Mx (x is more than or equal to 1) interlayer dielectric 101 and a metal wire Mx (x is more than or equal to 1) 102, wherein the metal wire Mx (x is more than or equal to 1) 102 is distributed in the middle of the metal wire Mx (x is more than or equal to 1) interlayer dielectric 101, and the metal wire Mx (x is more than or equal to 1) 102 is made of Cu.
1) A surface polished CMOS substrate 1 with metal lines Mx (x.gtoreq.1) is provided, as shown in FIG. 1.
2) On the CMOS substrate 1 after the planarization process, a Bottom Electrode Via (BEV) 4 after etching is fabricated as shown in fig. 2.
The BEV etching barrier layer 2 is SiN, siN, siC or SiCN, and the BEV interlayer dielectric 3 is SiO 2, siON or Low-K dielectric.
3) BEV and BE deposition metals 6 are deposited to form BEV metal fills 7 and BE metals 8, and the BE metals 8 are planarized to meet the requirements for deposition of MTJ multilayer films, as shown in fig. 3-5.
The BEV and BE metals 6 are W, typically formed by chemical vapor deposition (ChemicalVapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), atomic layer deposition (Atomic Layer Deposition, ALD) or ion beam deposition (Ion Beam Deposition, IBD).
Typically, before the BEV and BE deposition metals 6 are deposited, a BEV metal diffusion barrier layer 5, in particular a Ti/TiN diffusion barrier layer 5, is deposited.
The BEV and BE deposited metal 6 is filled within the BEV4 after etching and covers the BEV interlayer dielectric 3.
Wherein the W metal filled within the BEV 4 after etching is generally referred to as BEV metal fill 7 and the W metal overlying the BEV interlayer dielectric 3 is BE metal 8.
And flattening the BE metal by adopting a CMP process so as to enable the BE metal to meet the requirement of depositing the MTJ multilayer film.
In the CMP process, the pH value of the CMP is controlled to be 0-7, and oxidizing agents such as H 2O2、KIO3、Fe(NO3)3 or K 3Fe(CN)6 and the like can be added into the aqueous solution of the grinding slurry so as to increase the oxidation-reduction potential of the aqueous solution; still further, siO 2、Al2O3、CeO2 or MnO 2 may be selected as abrasives.
The thickness of the bottom electrode after the planarization treatment is 0nm-60nm.
4) On the planarized BE metal 8, a Magnetic Tunnel Junction (MTJ) 10 and a Top Electrode (TE) 11 are deposited, the Magnetic Tunnel Junction (MTJ) 10 pattern is graphically defined, and the Top Electrode (TE) 11, the Magnetic Tunnel Junction (MTJ) 10 and the BE metal are etched, finally, an insulating cap layer 12 is deposited around the outside of the Top Electrode (TE) 11, the Magnetic Tunnel Junction (MTJ) 10 and the BE metal 8 after etching, as shown in fig. 6-8.
The total thickness of the Magnetic Tunnel Junction (MTJ) 10 is 3nm-40nm, and may be a bottom pinned (Bottom Pinned) structure that is stacked up in sequence by the reference layer, barrier layer, and memory layer, or a top pinned (Top Pinned) structure that is stacked up in sequence by the memory layer, barrier layer, and reference layer.
The reference layer has magnetic polarization invariance and typically has a TbCoFe or [ Co/Pt ] n/Co/(Ru,Ir,Rh)/Co[Pt/Co]m (Ta, W, hf, mo, coBTa, feBTa, coFeBTa)/CoFeB (where m.gtoreq.0) superlattice multilayer film structure, typically with a buffer/seed layer 9 below. The structure is as follows: ta/Pt, ta/Ru/Pt, coFeB/Ta/Pt, ta/CoFeB/Pt, coFeB/Ru/Pt or CoFeB/Ta/Ru/Pt.
The barrier layer is a non-magnetic metal oxide, preferably MgO, mgBO, mgAlO or Al 2O3.
The memory layer is CoFeB, coFe/CoFeB, fe/CoFeB, coFeB (Ta, W, mo)/CoFeB.
The Top Electrode (TE) 11 has a thickness of 20nm-100nm, ta, taN, ti, tiN, W, WN or any combination thereof.
Etching the Magnetic Tunnel Junction (MTJ) 10 and the BE metal 8 thereof by using a method of reactive Ion Etching (Reactive Ion Etching, RIE) and/or Ion Beam Etching (IBE), where IBE mainly uses Ne, ar, kr or Xe as an Ion source, and a small amount of O 2 and/or N 2 may BE added; RIE mainly uses CH 3OH,CH4/Ar,C2H5OH,CH3 OH/Ar or CO/NH 3, etc. as the main etching gas.
Further, the side wall of the top electrode/magnetic tunnel junction/bottom electrode after etching is trimmed by using an IBE process to remove the side wall damage/deposition layer, wherein the gas is Ne, ar, kr or Xe, and the process parameters are strictly controlled, such as: the parameters of ion incidence angle, power, gas species and temperature are such that all sidewall damage/coating can be effectively removed.
The insulating cap layer 12 is formed of SiO 2, siON, siC, siN, siCN, or the like, and is formed by Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), ion Beam Deposition (IBD), or the like.
Although the present invention has been described with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described, or equivalents may be substituted for elements thereof, and any modifications, equivalents, improvements and changes may be made without departing from the spirit and principles of the present invention.
Claims (9)
1. A method for preparing an array of magnetic tunnel junction cells, comprising the steps of:
providing a CMOS substrate with a polished surface and a metal connection line Mx, wherein x is more than or equal to 1;
Step two, manufacturing a bottom electrode through hole after etching on the CMOS substrate after planarization treatment;
Depositing bottom electrode through holes (BEVs) and Bottom Electrode (BEs) to form bottom electrode through holes (BEVs) metal filling and Bottom Electrode (BE) metal, and flattening the Bottom Electrode (BE) metal to enable the Bottom Electrode (BE) metal to meet the requirement of depositing a magnetic tunnel junction multilayer film; the Bottom Electrode Via (BEV) metal fill and Bottom Electrode (BE) metal formed is one-time deposited; the Bottom Electrode Via (BEV) and Bottom Electrode (BE) deposited metal within the bottom electrode via after etching and covering a Bottom Electrode Via (BEV) interlayer dielectric; wherein the metal filled in the bottom electrode via after etching is Bottom Electrode Via (BEV) metal fill and the metal covered over the Bottom Electrode Via (BEV) interlayer dielectric is Bottom Electrode (BE) metal;
And fourthly, depositing a magnetic tunnel junction and a top electrode on the planarized Bottom Electrode (BE) metal, graphically defining a magnetic tunnel junction pattern, etching the top electrode, the magnetic tunnel junction and the Bottom Electrode (BE) metal, and depositing an insulating cover layer around the outer parts of the top electrode, the magnetic tunnel junction and the Bottom Electrode (BE) metal after etching.
2. A method of fabricating an array of magnetic tunnel junction cells according to claim 1, wherein: in the first step, the bottom electrode through hole etching barrier layer is SiN, siN, siC or SiCN, and the dielectric between the bottom electrode through hole layers is SiO 2, siON or low dielectric constant dielectric.
3. A method of fabricating an array of magnetic tunnel junction cells according to claim 1, wherein: the Bottom Electrode Via (BEV) and Bottom Electrode (BE) deposit metal W by chemical vapor deposition, physical vapor deposition, atomic layer deposition or ion beam deposition.
4. A method of fabricating an array of magnetic tunnel junction cells according to claim 1, wherein: a Bottom Electrode Via (BEV) metal diffusion barrier layer is deposited prior to Bottom Electrode Via (BEV) and Bottom Electrode (BE) deposition metal deposition.
5. A method of fabricating an array of magnetic tunnel junction cells according to claim 1, wherein: flattening the Bottom Electrode (BE) metal by adopting a chemical mechanical flattening process, wherein the thickness of the bottom electrode after flattening is 0-60 nm, controlling the PH value of CMP to BE 0-7 in the chemical mechanical flattening process, adding H 2O2、KIO3、Fe(NO3)3 or K 3Fe(CN)6 into the aqueous solution of grinding slurry, and selecting SiO 2、Al2O3、CeO2 or MnO 2 as grinding materials.
6. A method of fabricating an array of magnetic tunnel junction cells according to claim 1, wherein: in step four, a magnetic tunnel junction buffer/seed layer is deposited over the Bottom Electrode (BE) metal, and a magnetic tunnel junction is deposited over the magnetic tunnel junction buffer/seed layer.
7. A method of fabricating an array of magnetic tunnel junction cells according to claim 1, wherein: the total thickness of the magnetic tunnel junction is 3nm-40nm, and the magnetic tunnel junction is a bottom pinning structure formed by sequentially and upwardly superposing a reference layer, a barrier layer and a memory layer or a top pinning structure formed by sequentially and upwardly superposing the memory layer, the barrier layer and the reference layer.
8. A method of fabricating an array of magnetic tunnel junction cells according to claim 1, wherein: the thickness of the top electrode is 20nm-100nm, ta, taN, ti, tiN, W, WN or any combination thereof is selected;
The insulating cover layer material is SiO 2, siON, siC, siN or SiCN, and the forming method is chemical vapor deposition, atomic layer deposition or ion beam deposition.
9. A method of fabricating an array of magnetic tunnel junction cells according to claim 1, wherein: and (3) etching the magnetic tunnel junction and Bottom Electrode (BE) metal by adopting a reactive ion etching and/or ion beam etching method.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008277848A (en) * | 1996-07-26 | 2008-11-13 | Ekc Technol Inc | Chemical mechanical polishing composition and process |
| CN106409814A (en) * | 2015-07-28 | 2017-02-15 | 台湾积体电路制造股份有限公司 | Dummy bottom electrode in interconnect to reduce cmp dishing |
| CN107017338A (en) * | 2015-12-31 | 2017-08-04 | 台湾积体电路制造股份有限公司 | Semiconductor structure and its forming method |
| CN108232010A (en) * | 2016-12-21 | 2018-06-29 | 上海磁宇信息科技有限公司 | A kind of method of gas cluster ion beam planarization magnetic tunnel junction hearth electrode |
| CN108807664A (en) * | 2017-05-05 | 2018-11-13 | 上海磁宇信息科技有限公司 | A method of making small-size magnetic accidental memory structure unit |
| CN109216538A (en) * | 2017-06-30 | 2019-01-15 | 中电海康集团有限公司 | The production method of MRAM and its |
| CN109713006A (en) * | 2017-10-25 | 2019-05-03 | 上海磁宇信息科技有限公司 | A method of making magnetic RAM cell array and its peripheral circuits |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160027998A1 (en) * | 2014-07-24 | 2016-01-28 | Everspin Technologies, Inc. | Via formed underlying a mangetoresistive device and method of manufacture |
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Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008277848A (en) * | 1996-07-26 | 2008-11-13 | Ekc Technol Inc | Chemical mechanical polishing composition and process |
| CN106409814A (en) * | 2015-07-28 | 2017-02-15 | 台湾积体电路制造股份有限公司 | Dummy bottom electrode in interconnect to reduce cmp dishing |
| CN107017338A (en) * | 2015-12-31 | 2017-08-04 | 台湾积体电路制造股份有限公司 | Semiconductor structure and its forming method |
| CN108232010A (en) * | 2016-12-21 | 2018-06-29 | 上海磁宇信息科技有限公司 | A kind of method of gas cluster ion beam planarization magnetic tunnel junction hearth electrode |
| CN108807664A (en) * | 2017-05-05 | 2018-11-13 | 上海磁宇信息科技有限公司 | A method of making small-size magnetic accidental memory structure unit |
| CN109216538A (en) * | 2017-06-30 | 2019-01-15 | 中电海康集团有限公司 | The production method of MRAM and its |
| CN109713006A (en) * | 2017-10-25 | 2019-05-03 | 上海磁宇信息科技有限公司 | A method of making magnetic RAM cell array and its peripheral circuits |
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