CN112151596A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN112151596A
CN112151596A CN201910579447.1A CN201910579447A CN112151596A CN 112151596 A CN112151596 A CN 112151596A CN 201910579447 A CN201910579447 A CN 201910579447A CN 112151596 A CN112151596 A CN 112151596A
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isolation
layer
forming
channel
semiconductor structure
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CN112151596B (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a base, wherein the base comprises a substrate and a fin part positioned on the substrate; etching back the fin part with partial thickness to form a bottom fin part; forming an isolation layer and a channel fin part on the isolation layer on the bottom fin part; and forming a grid structure crossing the channel fin part and the isolation layer, wherein the grid structure covers part of the side wall of the isolation layer and part of the top and the side wall of the channel fin part. When the semiconductor structure works, the channel fin portion is used as a channel, and the isolation layer is formed between the channel fin portion and the bottom fin portion, so that the channel fin portion is electrically isolated from the bottom fin portion, the probability of current leakage of the semiconductor structure is reduced, and the electrical performance of the semiconductor structure is improved.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
In Semiconductor manufacturing, with the trend of ultra-large scale integrated circuits, the feature size of the integrated circuit is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is also continuously shortened correspondingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the controllability of the gate structure to the channel is deteriorated, and the difficulty of the gate voltage to pinch off the channel is increased, so that a sub-threshold leakage (SCE) phenomenon, which is a so-called short-channel effect (SCE), is more likely to occur.
Therefore, in order to better accommodate the reduction of feature sizes, semiconductor processing is gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) at least from two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit a short-channel effect; the gate structure is also transformed from the original polysilicon gate structure to a metal gate structure, and the work function layer in the metal gate structure can adjust the threshold voltage of the semiconductor structure.
Disclosure of Invention
The embodiment of the invention provides a semiconductor structure and a forming method thereof, and aims to improve the electrical performance of a device.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base, wherein the base comprises a substrate and a fin part positioned on the substrate; etching back the fin part with partial thickness to form a bottom fin part; forming an isolation layer and a channel fin part on the isolation layer on the bottom fin part; and forming a grid structure crossing the channel fin part and the isolation layer, wherein the grid structure covers part of the side wall of the isolation layer and part of the top and the side wall of the channel fin part.
Optionally, the step of forming the bottom fin portion includes: forming an isolation structure material layer covering the substrate, wherein the isolation structure material layer covers the side wall of the fin part and exposes the top wall of the fin part; and etching back the fin part with partial thickness, taking the residual fin part as the bottom fin part, and taking a region surrounded by the bottom fin part and the isolation structure material layer as a groove.
Optionally, the step of forming the isolation layer on the bottom fin portion and the channel fin portion on the isolation layer includes: forming the channel fin portion in the groove; etching back the isolation structure material layer with partial thickness to form an isolation structure exposing the channel fin part and the bottom fin part with partial thickness; and oxidizing the bottom fin part of the isolation structure to form the isolation layer.
Optionally, the step of forming the isolation layer on the bottom fin portion and the channel fin portion on the isolation layer includes: forming an isolation layer in the groove; after the isolation layer is formed, forming the channel fin part in the groove; the method for forming the semiconductor structure further comprises the following steps: and after the channel fin part is formed and before the grid structure is formed, etching back the isolation structure material layer with partial thickness to form an isolation structure exposing the channel fin part and the isolation layer.
Optionally, the material of the isolation layer is silicon oxide.
Optionally, the thickness of the isolation layer is 2 nm to 4 nm.
Optionally, the semiconductor structure is used to form a PMOS, and the material of the channel fin portion includes SiGe; or the semiconductor structure is used for forming an NMOS, and the material of the channel fin part comprises one or two of gallium arsenide and gallium indium arsenide.
Optionally, the bottom fin portion of the isolation structure is exposed by oxidation through a thermal oxidation process to form the isolation layer.
Optionally, the step of forming the isolation layer includes: forming an isolation material layer covering the groove, wherein the top of the isolation material layer is flush with the top of the isolation structure material layer; forming an isolation mask layer exposing the isolation material layer on the isolation structure material layer; etching the partial thickness of the isolation material layer by taking the isolation mask layer as a mask, and taking the rest isolation material layer as an isolation layer; or oxidizing the bottom fin part exposed out of the groove by adopting an oxidation process to form the isolation layer.
Optionally, after the forming the groove, the method further includes: forming a side wall layer on the side wall of the groove; the step of forming a channel fin in the recess comprises: forming the channel fin part in the groove between the side wall layers; the method for forming the semiconductor structure further comprises the following steps: and after the isolation layer and the channel fin part are formed, removing the side wall layer.
Optionally, the material of the sidewall layer includes one or more of silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
Optionally, the thickness of the sidewall layer is 1 nm to 5 nm.
Optionally, the sidewall layer is formed by an atomic layer deposition process or a chemical vapor deposition process.
Accordingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate; the fin structure is positioned on the substrate and comprises a bottom fin part, an isolation layer positioned on the bottom fin part and a channel fin part positioned on the isolation layer; and the grid structure spans the channel fin part and the isolation layer, and covers part of the side wall of the isolation layer and part of the top wall and the side wall of the channel fin part.
Optionally, the material of the isolation layer is silicon oxide.
Optionally, the thickness of the isolation layer is 2 nm to 4 nm.
Optionally, the semiconductor structure is a PMOS, and the material of the channel fin portion includes SiGe; or the semiconductor structure is an NMOS, and the material of the channel fin part comprises one or two of gallium arsenide and gallium indium arsenide.
Optionally, in an extending direction parallel to the gate structure, a size of the channel fin portion is smaller than a size of the bottom fin portion, and a projection of the channel fin portion on the substrate is located in a projection of the bottom fin portion on the substrate.
Optionally, the distance between the sidewall of the channel fin portion and the sidewall of the bottom fin portion is 1 nm to 5 nm.
Optionally, the semiconductor structure further includes: and the isolation structure is positioned on the substrate, covers the side wall of the bottom fin part and exposes the channel fin part and the isolation layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the embodiment of the invention provides a base, which comprises a substrate and a fin part positioned on the substrate; etching back the fin part with partial thickness to form a bottom fin part; and forming an isolation layer and a channel fin part positioned on the isolation layer on the bottom fin part. When the semiconductor structure works, the channel fin portion is used as a channel, and the isolation layer is formed between the channel fin portion and the bottom fin portion, so that the channel fin portion is electrically isolated from the bottom fin portion, the probability of current leakage of the semiconductor structure is reduced, and the electrical performance of the semiconductor structure is improved.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
fig. 2 to 10 are schematic structural views corresponding to steps in a first embodiment of a method for forming a semiconductor structure according to the present invention;
fig. 11 to 14 are schematic structural diagrams corresponding to steps in a second embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The devices formed at present still have the problem of poor performance. The reason for the poor performance of the device is analyzed in combination with a method for forming a semiconductor structure.
Referring to fig. 1, a schematic diagram of a semiconductor structure is shown.
As shown in fig. 1, the semiconductor structure includes a base, which includes a substrate 1 and a fin portion 2 located on the substrate 1; the isolation structure 3 is located on the substrate 1 where the fin portion 2 is exposed, and the isolation structure 3 covers a part of the sidewall of the fin portion 2; the gate structure 4 crosses the fin portion 2 and covers part of the top wall and part of the side wall of the fin portion 2; and source and drain doped regions (not shown) located in the fin portions 2 at two sides of the gate structure 4.
The fin portion 2 covered by the gate structure 4 serves as a channel region. When the semiconductor structure works, the gate structure 4 can directly control the part of the fin portion 2 covered by the gate structure, the migration rate of carriers in the controlled fin portion 2 region is high, but the carriers easily flow in the part of the fin portion 2 in the isolation structure 3, so that electric leakage is easily generated between the fin portion 2 and the substrate 1, and the electrical performance of the semiconductor structure is poor.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base, wherein the base comprises a substrate and a fin part positioned on the substrate; etching back the fin part with partial thickness to form a bottom fin part; forming an isolation layer and a channel fin part on the isolation layer on the bottom fin part; and forming a grid structure crossing the channel fin part and the isolation layer, wherein the grid structure covers part of the side wall of the isolation layer and part of the top and the side wall of the channel fin part.
The embodiment of the invention provides a base, which comprises a substrate and a fin part positioned on the substrate; etching back the fin part with partial thickness to form a bottom fin part; and forming an isolation layer and a channel fin part positioned on the isolation layer on the bottom fin part. When the semiconductor structure works, the channel fin portion is used as a channel, and the isolation layer is formed between the channel fin portion and the bottom fin portion, so that the channel fin portion is electrically isolated from the bottom fin portion, the probability of current leakage of the semiconductor structure is reduced, and the electrical performance of the semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 2 to 10 are schematic structural diagrams corresponding to steps in the first embodiment of the method for forming a semiconductor structure according to the present invention.
As shown in fig. 2, a base is provided, which includes a substrate 100 and a fin 101 on the substrate 100.
The substrate provides a process foundation for the subsequent formation of a semiconductor structure.
In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
In this embodiment, the fin 101 is made of silicon. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
As shown in fig. 3 and 4, the fin 101 is etched back to a certain thickness to form a bottom fin 102 (as shown in fig. 4).
It should be noted that, in the process of forming the bottom fin portion 102, a groove 104 (as shown in fig. 4) on the bottom fin portion 102 is also formed, and the groove 104 provides a space for forming a channel fin portion on the bottom fin portion 102 in the following step.
The steps of forming the bottom fin 102 and the recess 104 include: forming an isolation structure material layer 103 (as shown in fig. 3) covering the substrate 100, wherein the isolation structure material layer 103 covers sidewalls of the fin 101, and exposes a top wall of the fin 101; and etching back the fin part 101 with a part of thickness, wherein the remaining fin part 101 is used as the bottom fin part 102, and a region enclosed by the bottom fin part 102 and the isolation structure material layer 103 is used as the groove 104.
In this embodiment, the isolation structure material layer 103 is made of silicon oxide. The silicon oxide is a dielectric material which is common in process and low in cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the isolation structure material layer 103; in addition, the dielectric constant of the silicon oxide is small, and the effect of a subsequent isolation layer for isolating adjacent devices is improved.
In this embodiment, the isolation structure material layer 103 is formed by a Flowable Chemical Vapor Deposition (FCVD) process. The flow-type chemical vapor deposition process has good filling capability, and is beneficial to reducing the probability of forming defects such as voids in the isolation structure material layer 103.
In this embodiment, the fin portion 101 is etched by a dry etching process to form the groove 104. The dry etching process is an anisotropic etching process and has good etching profile controllability, so that the isolation structure material layer 103 is less damaged in the etching process, and the shape of the groove 104 can meet the process requirements. And the dry etching process is favorable for accurately controlling the removal thickness of the fin part 101 material, so that the depth of the groove 104 can be accurately controlled.
Referring to fig. 5-9, an isolation layer 105 (shown in fig. 9) and a trench fin 106 (shown in fig. 9) on the isolation layer 105 are formed on the bottom fin 102.
When the semiconductor structure works, the channel fin portion 106 serves as a channel, and the isolation layer 105 is formed between the channel fin portion 106 and the bottom fin portion 102, so that the channel fin portion 106 and the bottom fin portion 102 are electrically isolated, the probability of leakage current of the semiconductor structure is reduced, and the electrical performance of the semiconductor structure is improved.
In this embodiment, the channel fin portion 106 is formed first; after forming the trench fin 106, an isolation layer 105 is formed. Specifically, the steps of forming the isolation layer 105 and the channel fin 106 on the isolation layer 105 include:
as shown in fig. 5, the method for forming the semiconductor structure includes: after the groove 104 is formed, a sidewall layer 107 is formed on the sidewall of the groove 104.
In the subsequent process, channel fin portions are formed in the grooves 104 between the side wall layers 107; after the channel fin part is formed, etching the isolation structure material layer 103 to form an isolation structure exposing a part of the thickness of the bottom fin part 102; the bottom fin portion 102 exposing the isolation structure is oxidized to an isolation layer using a thermal oxidation process. The side wall layer 107 protects the channel fin portion from being damaged in the process of etching the isolation structure material layer 103 to form an isolation structure; and the sidewall layer 107 is used for protecting the channel fin portion from being oxidized easily in the process of forming the isolation layer by thermally oxidizing the exposed part of the thickness of the bottom fin portion 102 of the isolation structure 108 in the subsequent process, so that the migration rate of carriers in the channel fin portion is improved when the semiconductor structure works.
The sidewall layer 107 is a dielectric material.
Specifically, the material of the sidewall layer 107 includes one or more of silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall layer 107 is made of silicon nitride. The hardness of the silicon nitride is higher, which is beneficial to protecting the channel fin portion from being etched in the subsequent process of etching the isolation structure material layer 103 to form the isolation layer. The silicon nitride is a dielectric material which is common in process and low in cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the side wall layer 107; in addition, the process for removing the silicon nitride is mature, and the damage to the isolation layer and the channel fin part in the process of removing the side wall layer 107 can be reduced.
The step of forming the sidewall layer 107 includes: conformally covering a side wall material layer (not shown) in the groove 104 and on the isolation structure material layer 103; and removing the side wall material layers on the bottom fin portion 102 and the isolation structure material layer 103, wherein the side wall material layers on the side wall of the isolation structure material layer 103 are used as side wall layers 107.
It should be noted that the sidewall layer 107 is not too thick nor too thin. If the sidewall layer 107 is too thick, too much process time is easily spent for forming the sidewall layer 107, too much process time is easily spent for removing the sidewall layer 107 after the isolation layer is formed subsequently, and the size of the channel fin portion is small in the extending direction perpendicular to the bottom fin portion 102, so that the mobility rate of carriers is not high when the semiconductor structure works. If the sidewall layer 107 is too thin, the channel fin portion is easily damaged in the subsequent etching process of the isolation structure material layer 103 to form the isolation structure; in the subsequent process of oxidizing the bottom fin portion exposed by the isolation structure to form the isolation layer, the sidewall layer 107 cannot well protect the channel fin portion from oxidation, and thus the carrier migration rate in the channel fin portion is not high when the semiconductor structure works. In this embodiment, the thickness of the sidewall layer is 1 nm to 5 nm.
In this embodiment, the sidewall layer 107 is formed by an Atomic Layer Deposition (ALD) process. The ald process includes performing a plurality of ald cycles to form a sidewall layer 107 of a desired thickness. By selecting the atomic layer deposition process, the thickness uniformity of the side wall layer 107 can be improved, so that the thickness of the side wall layer 107 can be accurately controlled; in addition, the atomic layer deposition process has good gap filling performance and step coverage, and accordingly conformal coverage of the sidewall layer 107 is improved. In other embodiments, other deposition processes may be used to form the sidewall layer, such as: chemical Vapor Deposition (CVD) and the like.
It should be noted that the forming of the sidewall layer 107 by using the atomic layer deposition process means forming the sidewall material layer by using the atomic layer deposition process.
As shown in fig. 6, channel fins 106 are formed in the recess 104.
The channel fin 106 acts as a channel during operation of the semiconductor structure.
In this embodiment, the semiconductor structure is used to form a PMOS, and the material of the channel fin 106 includes SiGe.
The bottom fin portion 102 is made of Si, the molar volume percentage of Ge in the channel fin portion 106 is higher than that of Ge in the bottom fin portion 102, and because the Ge lattice constant is larger than that of Si, the bottom fin portion 102 with low Ge concentration is in contact with the channel fin portion 106 with high Ge concentration, so that compressive stress is generated in the channel fin portion 106, and the channel fin portion 106 has the compressive stress, so that when the semiconductor structure works, the channel carrier mobility in PMOS can be improved, and the electrical performance of the semiconductor structure can be improved.
In other embodiments, the semiconductor structure is an NMOS, and the material of the channel fin 106 includes one or both of gallium arsenide and gallium indium arsenide.
The channel fin portion grows on the bottom fin portion, the material of bottom fin portion is Si, the material of channel fin portion is one or two kinds in gallium arsenide and the indium gallium arsenic, is favorable to improving carrier mobility and saturation migration rate in the channel fin portion, and the concrete principle is prior art, and no longer gives details here.
The method comprises the following specific steps: forming a channel fin material layer (not shown) in the recess 104 between the sidewall layers 107; and removing the channel fin material layer on the isolation structure material layer 103, wherein the remaining channel fin material layer in the groove 104 is used as a channel fin 106. In other embodiments, a selective epitaxial growth method can be used to directly form the channel fin portion in the groove, so that the forming process of the semiconductor structure is simplified.
In this embodiment, the channel fin material layer is formed by using a Selective Epitaxial Growth (SEG) process. The single crystal formed by the selective epitaxial growth process has high purity, and the corresponding channel fin material layer is not easy to have defects.
In this embodiment, a planarization process is used to remove the channel fin material layer on the isolation structure material layer 103.
As shown in fig. 7, a portion of the thickness of the isolation structure material layer 103 is etched back (as shown in fig. 6), so as to form an isolation structure 108 exposing the channel fin 106 and the bottom fin 102.
The isolation structure 108 exposes a portion of the bottom fin portion 102, and provides for subsequent oxidation of the exposed bottom fin portion 102 of the isolation structure 108 to form an isolation layer.
It should be noted that the bottom fin 102 exposed by the isolation structure 108 is not too thick or too thin. If the exposed bottom fin portion 102 is too thick, the isolation structure 108 is too thin, which may cause the isolation structure 108 to have a poor electrical isolation between the gate structure and the substrate 100. If the exposed bottom fin portion 102 is too thin, an isolation layer formed by oxidizing the bottom fin portion 102 exposed by the isolation structure 108 may be too thin, and thus the isolation layer may not function to isolate the channel fin portion 106 from the bottom fin portion 102 during operation of the semiconductor structure. In this embodiment, the thickness of the bottom fin portion 102 exposed by the isolation structure 108 is 2 nm to 4 nm.
In this embodiment, the isolation structure material layer 103 with a partial thickness is etched back by using a dry etching process to form the isolation structure 108. The dry etching process is an anisotropic etching process, has good etching profile controllability, is favorable for enabling the appearance of the isolation structure 108 to meet the process requirements, is also favorable for improving the removal efficiency of the isolation structure material layer 103, and is favorable for accurately controlling the removal thickness of the isolation structure material layer 103 by adopting the dry etching process.
As shown in fig. 8, the bottom fin portion 102 of the isolation structure 108 is oxidized to form the isolation layer 105.
The isolation layer 105 enables the bottom fin portion 102 and the channel fin portion 106 to be electrically isolated, so that the probability of leakage current of the semiconductor structure is reduced, and the electrical performance of the semiconductor structure is improved.
The material of the isolation layer 105 is silicon oxide. The silicon oxide is a dielectric material which is common in process and low in cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the isolation layer 105; in addition, the smaller dielectric constant of silicon oxide is also beneficial to improve the effect of isolating the trench fin 106 and the bottom fin 102.
In this embodiment, a thermal oxidation process is used to oxidize and expose a portion of the bottom fin portion 102 of the isolation structure 108, so as to form the isolation layer 105.
In this embodiment, the thermal oxidation process is a rapid thermal oxidation process. The technological parameters of the rapid thermal oxidation technology comprise: the process temperature is 700 ℃ to 1100 ℃, the process time is 5 seconds to 50 seconds, the pressure is 50 torr to 300 torr, the reaction gas is oxygen, the auxiliary gas is nitrogen, and the gas flow ratio of the oxygen to the nitrogen is 1:20 to 1: 5.
It should be noted that the process temperature of the rapid thermal oxidation process is not too low and is not too high. If the process temperature of the rapid thermal oxidation process is too low, the formation quality of the isolation layer 105 is poor, the process time is too long, and the process stability is difficult to control; if the process temperature of the rapid thermal oxidation process is too high, the thermal budget is easily increased, and the process stability is easily poor. In this embodiment, the temperature of the rapid thermal oxidation process is 700 to 1100 ℃.
In this embodiment, the thickness of the bottom fin portion 102 exposed by the isolation structure 108 is 2 nm to 4 nm, and correspondingly, the thickness of the isolation layer 105 formed by the thermal oxidation process is 2 nm to 4 nm.
It should be noted that, during the process of forming the isolation layer 105 by using the thermal oxidation process, the sidewall layer 107 plays a role of protecting the channel fin 106, so as to prevent the channel fin 106 from being oxidized.
As shown in fig. 9, after the isolation layer 105 and the channel fin 106 are formed, the sidewall layer 107 is removed.
The sidewall layer 107 is removed to prepare for the subsequent formation of the gate structure crossing the channel fin 106, thereby improving the control of the gate structure on the channel fin 106.
In this embodiment, a wet etching process is adopted to remove the sidewall layer 107. In other embodiments, the sidewall layer may be removed by a dry etching process.
Specifically, the wet etching solution is a phosphoric acid solution.
Referring to fig. 10, a gate structure 109 is formed to cross the channel fin 106 and the isolation layer 105, and the gate structure 109 covers a portion of the sidewall of the isolation layer 105 and a portion of the top and sidewall of the channel fin 106.
The gate structure 109 is used to control the opening and closing of the channel during operation of the semiconductor structure. The gate structure 109 has good control capability on the channel fin portion 106 covered by the gate structure, the migration rate of current carriers in the channel fin portion 106 is high, and the channel fin portion 106 and the bottom fin portion 102 are electrically isolated by the isolation layer 105, so that the current carriers in the channel fin portion 106 are not easy to pass through the isolation layer 105, and the probability of current leakage of the channel fin portion 106 is reduced.
The gate structure 109 is a polysilicon gate structure or a metal gate structure. In this embodiment, the gate structure 109 is a polysilicon gate structure.
In this embodiment, the gate structure 109 is a stacked structure including a gate oxide layer (not shown) conformally covering a portion of the top surface and a portion of the sidewall of the fin 101 and a gate layer (not shown) on the gate oxide layer. In other embodiments, the gate structure may also be a single-layer structure, i.e., the gate structure includes only the gate layer.
In this embodiment, the gate oxide layer is made of silicon oxide. In other embodiments, the gate oxide layer may also be silicon oxynitride.
In this embodiment, the gate layer is made of polysilicon. In other embodiments, the material of the gate layer may also be amorphous carbon.
Fig. 11 to 14 are schematic structural diagrams corresponding to a second embodiment of the method for forming a semiconductor structure according to the present invention.
The same parts of this embodiment as those of the first embodiment will not be described herein again. The present embodiment is different from the first embodiment in that: the isolation layer 205 is formed first and then the channel fin 206 is formed.
When the semiconductor structure works, the channel fin portion 206 serves as a channel, and the isolation layer 205 is formed between the channel fin portion 206 and the bottom fin portion 202, so that the channel fin portion 206 and the bottom fin portion 202 are electrically isolated, the probability of leakage current of the semiconductor structure is reduced, and the electrical performance of the semiconductor structure is improved.
In the embodiment of the present invention, the channel fin portion 206 is formed after the isolation layer 205, so that the probability of oxidation of the channel fin portion 206 is greatly reduced, and when the semiconductor structure operates, the carrier migration rate in the channel fin portion 206 is high.
Specifically, the steps of forming the isolation layer 205 on the bottom fin portion 202 and the channel fin portion 206 on the isolation layer 205 include:
as shown in fig. 11, an isolation layer 205 is formed in the recess 204.
In this embodiment, the step of forming the isolation layer 205 in the groove 204 includes: after the recess 204 is formed, an isolation layer 205 is formed on the bottom fin portion 202 exposed by the recess 204 by using a thermal oxidation process.
For the description of the thermal oxidation process, reference is made to the previous embodiment, and details thereof are not repeated
In other embodiments, the step of forming the isolation layer may further include: forming an isolation material layer in the groove, wherein the top of the isolation material layer is flush with the top of the isolation structure material layer; forming an isolation mask layer exposing the isolation material layer; and etching back the partial thickness of the isolation material layer by taking the isolation mask layer as a mask, and taking the rest isolation material layer as an isolation layer.
As shown in fig. 12, a sidewall layer 207 is formed on the sidewall of the groove 204.
The first embodiment is referred to for the related description of the method for forming the sidewall layer 207, and is not repeated herein.
With continued reference to fig. 12, after forming the isolation layer 205, the channel fin 206 is formed in the recess 204.
Specifically, the step of forming the channel fin 206 includes: channel fins 206 are formed in the recess 204 between the sidewall layers 207.
The first embodiment is referred to for a related description of a method for forming the trench fin 206, which is not repeated herein.
As shown in fig. 13, a portion of the thickness of the isolation structure material layer 203 is etched back (as shown in fig. 12), so as to form an isolation structure 208 exposing the channel fin 206 and a portion of the thickness of the isolation layer 205.
The first embodiment is referred to for a related description of a method for forming the isolation structure 208, which is not repeated herein.
As shown in fig. 14, the sidewall layer 207 on the sidewalls of the trench fin 206 is removed (as shown in fig. 13); after removing the sidewall layer 207, a gate structure 209 spanning the channel fin 206 and the isolation layer 205 is formed, and the gate structure 209 covers a portion of the sidewall of the isolation layer 205 and a portion of the top and sidewall of the channel fin 206.
The first embodiment is referred to for a description of a method for forming the gate structure 209 and the sidewall layer 207, which will not be described herein again.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 10, a schematic structural diagram of a first embodiment of the semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate 100; a fin structure (not shown) on the substrate 100; the fin structure includes: a bottom fin 102, an isolation layer 105 on the bottom fin 102, and a channel fin 106 on the isolation layer 105; and a gate structure 109 spanning the channel fin 106 and the isolation layer 105, wherein the gate structure 109 covers a part of the sidewall of the isolation layer 105 and a part of the top wall and the sidewall of the channel fin 106.
When the semiconductor structure works, the channel fin portion 106 serves as a channel, and the isolation layer 105 is located between the channel fin portion 106 and the bottom fin portion 102, so that the channel fin portion 106 and the bottom fin portion 102 are electrically isolated, the probability of leakage current of the semiconductor structure is reduced, and the electrical performance of the semiconductor structure is improved.
The substrate 100 provides a process foundation for subsequently forming semiconductor structures.
In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
In this embodiment, the material of the bottom fin portion 102 is silicon. In other embodiments, the material of the bottom fin portion may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
In this embodiment, the semiconductor structure further includes: an isolation structure 108 is located on the substrate 102, covering sidewalls of the bottom fin 102, and exposing the trench fin 106 and the isolation layer 105.
In this embodiment, the isolation structure 108 is made of silicon oxide. The silicon oxide is a dielectric material with common process and low cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the isolation structure 108; in addition, the silicon oxide has a small dielectric constant, which is beneficial to improving the function of isolating adjacent devices.
The material of the isolation layer 105 is silicon oxide. The silicon oxide is a dielectric material which is common in process and low in cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the isolation layer 105; in addition, the smaller dielectric constant of silicon oxide is also beneficial for improving the electrical isolation between the channel fin 106 and the bottom fin 102.
Note that the isolation layer 105 is not too thick nor too thin. In the process of forming the semiconductor structure, the isolation layer 105 is formed by oxidizing the bottom fin portion 102 exposed by the isolation structure 108. If the isolation layer 105 is too thick, the isolation structure 108 is too thin, which may cause the isolation structure 108 to have a poor electrical isolation between the gate structure 109 and the substrate 100. If the isolation layer 105 is too thin, the isolation layer 105 may not function to isolate the channel fin 106 from the bottom fin 102 during operation of the semiconductor structure. In this embodiment, the thickness of the isolation layer 105 is 2 nm to 4 nm.
The channel fin 106 acts as a channel during operation of the semiconductor structure.
In this embodiment, the semiconductor structure is used to form a PMOS, and the material of the channel fin 106 includes SiGe.
The material of the bottom fin portion 102 is Si, the molar volume percentage of Ge in the channel fin portion 106 is higher than that of Ge in the bottom fin portion 102, and since Ge atoms are larger than Si atoms, the bottom fin portion 102 with low Ge concentration is in contact with the channel fin portion 106 with high Ge concentration, so that compressive stress is generated in the channel fin portion 106, and the channel fin portion 106 has compressive stress, so that when the semiconductor structure works, the mobility of channel carriers in PMOS is improved, and the electrical performance of the semiconductor structure is improved.
In other embodiments, the semiconductor structure is an NMOS, and the material of the channel fin 106 includes one or both of gallium arsenide and gallium indium arsenide.
The channel fin portion grows on the bottom fin portion, the material of bottom fin portion is Si, the material of channel fin portion is one or two kinds in gallium arsenide and the indium gallium arsenic, is favorable to improving carrier mobility and saturation migration rate in the channel fin portion, and the specific principle is that prior art no longer gives details here.
The gate structure 109 is used to control the opening and closing of the channel during operation of the semiconductor structure. The gate structure 109 has good control capability on the channel fin portion 106 covered by the gate structure, the migration rate of carriers in the channel fin portion 106 is high, and the channel fin portion 106 and the bottom fin portion 102 are electrically isolated by the isolation layer 105, so that the carriers in the channel fin portion 106 are not easy to pass through the isolation layer 105, and the probability of leakage current of the channel fin portion 106 is reduced.
The gate structure 109 is a polysilicon gate structure or a metal gate structure. In this embodiment, the gate structure 109 is a polysilicon gate structure.
In this embodiment, the gate structure 109 is a stacked structure including a gate oxide layer (not shown) conformally covering a portion of the top surface and a portion of the sidewall of the fin 101 and a gate layer (not shown) on the gate oxide layer. In other embodiments, the gate structure may also be a single-layer structure, i.e., the gate structure includes only the gate layer.
In this embodiment, the gate oxide layer is made of silicon oxide. In other embodiments, the gate oxide layer may also be silicon oxynitride.
In this embodiment, the gate layer is made of polysilicon. In other embodiments, the material of the gate layer may also be amorphous carbon.
In this embodiment, in the extending direction parallel to the gate structure 109, the size of the channel fin portion 106 is smaller than the size of the bottom fin portion 102, and the projection of the channel fin portion 106 on the substrate 100 is located in the projection of the bottom fin portion 102 on the substrate 100.
In the formation process of the semiconductor structure, a sidewall layer 107 (as shown in fig. 6) is formed at a position between the sidewall of the channel fin 106 and the sidewall of the bottom fin 102, and in the process of oxidizing the bottom fin 102 exposing the isolation structure 108 to form the isolation layer 105, the sidewall layer 107 makes the channel fin 106 not easily oxidized. The sidewall layer 107 also protects the channel fin 106 from damage during etching of the isolation structure material layer 103 (as shown in fig. 6) to form the isolation structure 108.
It should be noted that the distance between the sidewalls of the channel fin 106 and the sidewalls of the bottom fin 102 is not too large or too small. If the distance is too large, the dimension of the channel fin portion 106 in the direction perpendicular to the extension direction of the bottom fin portion 102 is small, and the carrier migration rate is not high during the operation of the semiconductor structure. If the distance is too small, that is, the sidewall layer 107 is too thin, the channel fin 106 is easily damaged during the process of etching the isolation structure material layer 103 to form the isolation structure 108; in addition, in the process of oxidizing the bottom fin portion 102 exposed by the isolation structure 108 to form the isolation layer 105, the channel fin portion 106 is susceptible to oxidation, and thus, when the semiconductor structure operates, the carrier mobility rate in the channel fin portion 106 is not high. In this embodiment, the distance between the sidewall of the channel fin 106 and the sidewall of the bottom fin 102 is 1 nm to 5 nm.
The semiconductor structure of this embodiment may be formed by the formation method described in the foregoing embodiment, or may be formed by other formation methods. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a base, wherein the base comprises a substrate and a fin part positioned on the substrate;
etching back the fin part with partial thickness to form a bottom fin part;
forming an isolation layer and a channel fin part on the isolation layer on the bottom fin part;
and forming a grid structure crossing the channel fin part and the isolation layer, wherein the grid structure covers part of the side wall of the isolation layer and part of the top and the side wall of the channel fin part.
2. The method of forming a semiconductor structure of claim 1, wherein the step of forming the bottom fin portion comprises: forming an isolation structure material layer covering the substrate, wherein the isolation structure material layer covers the side wall of the fin part and exposes the top wall of the fin part;
and etching back the fin part with partial thickness, taking the residual fin part as the bottom fin part, and taking a region surrounded by the bottom fin part and the isolation structure material layer as a groove.
3. The method of forming a semiconductor structure of claim 2, wherein forming an isolation layer on the bottom fin and a channel fin on the isolation layer comprises:
forming the channel fin portion in the groove;
etching back the isolation structure material layer with partial thickness to form an isolation structure exposing the channel fin part and the bottom fin part with partial thickness;
and oxidizing the bottom fin part of the isolation structure to form the isolation layer.
4. The method of forming a semiconductor structure of claim 2, wherein forming an isolation layer on the bottom fin and a channel fin on the isolation layer comprises: forming an isolation layer in the groove;
after the isolation layer is formed, forming the channel fin part in the groove;
the method for forming the semiconductor structure further comprises the following steps: and after the channel fin part is formed and before the grid structure is formed, etching back the isolation structure material layer with partial thickness to form an isolation structure exposing the channel fin part and the isolation layer.
5. The method of forming a semiconductor structure according to any one of claims 1 to 4, wherein a material of the isolation layer is silicon oxide.
6. The method of forming a semiconductor structure of any of claims 1 to 4, wherein the spacer layer has a thickness of 2 nm to 4 nm.
7. The method of forming a semiconductor structure according to any one of claims 1 to 4, wherein the semiconductor structure is used to form a PMOS, and the material of the channel fin comprises SiGe;
or the semiconductor structure is used for forming an NMOS, and the material of the channel fin part comprises one or two of gallium arsenide and gallium indium arsenide.
8. The method of claim 3, wherein said isolation layer is formed by oxidizing said bottom fin portion of said isolation structure exposed by a thermal oxidation process.
9. The method of forming a semiconductor structure of claim 4, wherein the step of forming the isolation layer comprises: forming an isolation material layer covering the groove, wherein the top of the isolation material layer is flush with the top of the isolation structure material layer; forming an isolation mask layer exposing the isolation material layer on the isolation structure material layer; etching the partial thickness of the isolation material layer by taking the isolation mask layer as a mask, and taking the rest isolation material layer as an isolation layer;
or oxidizing the bottom fin part exposed out of the groove by adopting an oxidation process to form the isolation layer.
10. The method of forming a semiconductor structure according to claim 3 or 4, further comprising, after forming the recess: forming a side wall layer on the side wall of the groove;
the step of forming a channel fin in the recess comprises: forming the channel fin part in the groove between the side wall layers;
the method for forming the semiconductor structure further comprises the following steps: and after the isolation layer and the channel fin part are formed, removing the side wall layer.
11. The method of claim 10, wherein the material of the sidewall layer comprises one or more of silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
12. The method of claim 10, wherein the thickness of the sidewall layer is between 1 nm and 5 nm.
13. The method of claim 10, wherein the sidewall layer is formed using an atomic layer deposition process or a chemical vapor deposition process.
14. A semiconductor structure, comprising:
a substrate;
the fin structure is positioned on the substrate and comprises a bottom fin part, an isolation layer positioned on the bottom fin part and a channel fin part positioned on the isolation layer;
and the grid structure spans the channel fin part and the isolation layer, and covers part of the side wall of the isolation layer and part of the top wall and the side wall of the channel fin part.
15. The semiconductor structure of claim 14, wherein a material of the isolation layer is silicon oxide.
16. The semiconductor structure of claim 14, wherein the spacer layer has a thickness of 2 nm to 4 nm.
17. The semiconductor structure of claim 14, wherein the semiconductor structure is a PMOS, the material of the channel fin comprises SiGe;
or the semiconductor structure is an NMOS, and the material of the channel fin part comprises one or two of gallium arsenide and gallium indium arsenide.
18. The semiconductor structure of claim 14, wherein a dimension of the channel fin is smaller than a dimension of the bottom fin in a direction parallel to an extension direction of the gate structure, and a projection of the channel fin on the substrate is in a projection of the bottom fin on the substrate.
19. The semiconductor structure of claim 18, wherein a distance between sidewalls of the channel fin and sidewalls of the bottom fin is between 1 nm and 5 nm.
20. The semiconductor structure of claim 15, wherein the semiconductor structure further comprises: and the isolation structure is positioned on the substrate, covers the side wall of the bottom fin part and exposes the channel fin part and the isolation layer.
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Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102856205A (en) * 2011-06-30 2013-01-02 中国科学院微电子研究所 Formation method of multi-gate device
US20130037869A1 (en) * 2011-08-10 2013-02-14 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method of semiconductor device
JP2013069770A (en) * 2011-09-21 2013-04-18 Elpida Memory Inc Semiconductor device and manufacturing method of the same
CN103367131A (en) * 2012-04-09 2013-10-23 中芯国际集成电路制造(上海)有限公司 Fins and formation methods for fins and fin field effect transistor
US8691640B1 (en) * 2013-01-21 2014-04-08 Globalfoundries Inc. Methods of forming dielectrically isolated fins for a FinFET semiconductor by performing an etching process wherein the etch rate is modified via inclusion of a dopant material
CN103915501A (en) * 2013-01-09 2014-07-09 国际商业机器公司 Finfet With Dielectric Isolation By Silicon-on-nothing And Method Of Fabrication
US20150129934A1 (en) * 2013-11-13 2015-05-14 Globalfoundries Inc. Methods of forming substantially self-aligned isolation regions on finfet semiconductor devices and the resulting devices
US9455199B1 (en) * 2016-02-16 2016-09-27 Globalfoundries Inc. Methods of forming strained and relaxed germanium fins for PMOS and NMOS finFET devices, respectively
CN106298921A (en) * 2015-06-01 2017-01-04 中芯国际集成电路制造(上海)有限公司 Semiconductor device, fin formula field effect transistor and forming method thereof
CN106298919A (en) * 2015-05-29 2017-01-04 中芯国际集成电路制造(上海)有限公司 Semiconductor device, fin formula field effect transistor and forming method thereof
US20170256540A1 (en) * 2016-03-07 2017-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with low defect and method for forming the same
US20170338323A1 (en) * 2016-05-18 2017-11-23 International Business Machines Corporation Dummy dielectric fins for finfets with silicon and silicon germanium channels
CN107591331A (en) * 2016-07-08 2018-01-16 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102856205A (en) * 2011-06-30 2013-01-02 中国科学院微电子研究所 Formation method of multi-gate device
US20130037869A1 (en) * 2011-08-10 2013-02-14 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method of semiconductor device
JP2013069770A (en) * 2011-09-21 2013-04-18 Elpida Memory Inc Semiconductor device and manufacturing method of the same
CN103367131A (en) * 2012-04-09 2013-10-23 中芯国际集成电路制造(上海)有限公司 Fins and formation methods for fins and fin field effect transistor
CN103915501A (en) * 2013-01-09 2014-07-09 国际商业机器公司 Finfet With Dielectric Isolation By Silicon-on-nothing And Method Of Fabrication
US8691640B1 (en) * 2013-01-21 2014-04-08 Globalfoundries Inc. Methods of forming dielectrically isolated fins for a FinFET semiconductor by performing an etching process wherein the etch rate is modified via inclusion of a dopant material
US20150129934A1 (en) * 2013-11-13 2015-05-14 Globalfoundries Inc. Methods of forming substantially self-aligned isolation regions on finfet semiconductor devices and the resulting devices
CN106298919A (en) * 2015-05-29 2017-01-04 中芯国际集成电路制造(上海)有限公司 Semiconductor device, fin formula field effect transistor and forming method thereof
CN106298921A (en) * 2015-06-01 2017-01-04 中芯国际集成电路制造(上海)有限公司 Semiconductor device, fin formula field effect transistor and forming method thereof
US9455199B1 (en) * 2016-02-16 2016-09-27 Globalfoundries Inc. Methods of forming strained and relaxed germanium fins for PMOS and NMOS finFET devices, respectively
US20170256540A1 (en) * 2016-03-07 2017-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with low defect and method for forming the same
US20170338323A1 (en) * 2016-05-18 2017-11-23 International Business Machines Corporation Dummy dielectric fins for finfets with silicon and silicon germanium channels
CN107591331A (en) * 2016-07-08 2018-01-16 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

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