CN112133802A - 一种GaN薄膜及其制备方法 - Google Patents

一种GaN薄膜及其制备方法 Download PDF

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CN112133802A
CN112133802A CN202011005050.0A CN202011005050A CN112133802A CN 112133802 A CN112133802 A CN 112133802A CN 202011005050 A CN202011005050 A CN 202011005050A CN 112133802 A CN112133802 A CN 112133802A
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赵桂娟
邢树安
刘贵鹏
汤金金
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Abstract

本发明涉及一种GaN薄膜及其制备方法。其中GaN薄膜，包括Si衬底和位于Si衬底上图形化的SiO2掩膜层，所述Si衬底的Si{111}晶面上有Si3N4缓冲层，所述SiO2掩膜层和不参与GaN生长的Si3N4缓冲层上有溅射SiO2膜；所述参与GaN生长的Si3N4缓冲层上有GaN插入层，所述GaN插入层上生长有GaN薄膜层。本发明的GaN薄膜，通过在Si图形衬底上外延生长非极性GaN薄膜的方法制得，不仅成本低廉，且性能优良能够广泛地用于器件的制作中。

Description

一种GaN薄膜及其制备方法
技术领域
本发明涉及半导体领域，具体涉及一种在Si图形衬底上外延生长非极性GaN的GaN薄膜及其制备方法。
背景技术
GaN是一种直接带隙的宽禁带半导体，由于其高热导率、高强场漂移速度和高击穿电压等优良特性受到了人们的广泛关注，且已经被应用于许多光电和大功率电子器件。目前，在充电器方面，GaN材料可以做成小尺寸、大功率的快速充电器，在快充市场有很大的前景；而由GaN材料制造的如LED等照明器件更是已经实现了商品化生产，且其中由GaN材料制造的蓝光LED获得2014年诺贝尔物理学奖；此外在5G时代，GaN也会由于其小尺寸、高效率和高的功率密度等特点而被用于基站功放之中。
现阶段，以蓝宝石(Al2O3)和碳化硅(SiC)为衬底来生长GaN薄膜的技术已经比较成熟，但是蓝宝石材料的导电导热性比较差，碳化硅材料的价格又十分的昂贵，因此对应器件的成本高。而相反，Si材料作为当今应用最广的半导体材料，有着价格低廉、导热好、尺寸大等优点。因此，以Si材料作为生长Ga N的衬底不仅可以在很大的程度上降低GaN器件的制造成本，而且还可以提高GaN器件的兼容性，在未来有望应用到集成电路中。传统的GaN基器件多采用GaN的极性面，将会产生沿[0001]方向的自发极化和压电极化，从而引起量子限制斯塔克效应(QCSE)。这种效应会降低电子-空穴复合几率，从而导致器件发光效率下降，对发光器件有很大的影响。而采用非极性的GaN材料能极大的改善这一情况。
但是，在Si衬底上直接生长GaN时，由于较大的晶格失配和热失配会在G aN薄膜中产生很大的应力和较高的位错密度，从而使得生长的GaN薄膜无法用来制作器件。
发明内容
本发明的目的在于克服现有技术的不足，提出一种成本低廉且性能优良的在Si图形衬底上外延生长非极性GaN薄膜的方法，且制得的薄膜能够广泛地用于器件的制作。
本发明的一种GaN薄膜，包括Si衬底和位于Si衬底上图形化的SiO2掩膜层，所述Si衬底的Si{111}晶面上有Si3N4缓冲层，所述SiO2掩膜层和不参与GaN生长的Si3N4缓冲层上有溅射SiO2膜；所述参与GaN生长的Si3N4缓冲层上有GaN插入层，所述GaN插入层上生长有GaN薄膜层。本发明的GaN薄膜中的缓冲层Si3N4层为有序的密排六方结构，不仅可以很好的解决晶格失配和热失配所带来的问题，而且可以避免Ga-Si回熔刻蚀，以及弛豫和补偿后续GaN生长累积的残余应力。其中GaN插入层可以使生长出来的GaN表面快速愈合，从而提高GaN薄膜层的质量。本发明所生长的GaN薄膜层为非极性的GaN，非极性的GaN在发光器件中有十分良好的性能，可以避免由于极化所引起量子限制斯塔克效应(QCSE)。
进一步，本发明的GaN薄膜，所述SiO2掩膜层(2a)的厚度为50-100nm，所述不参与GaN生长的Si3N4缓冲层(3)厚度为20-100nm，所述GaN插入层(5)的厚度为200-400nm，所述溅射SiO2膜(4)的厚度为40-60nm，所述GaN薄膜层(6)的厚度为1000-2000nm。其中SiO2掩膜层一方面可以通过光刻与刻蚀形成所需的条状掩膜，为下一步刻蚀硅片做准备，同时也能够阻止Si衬底与GaN的直接接触。若SiO2掩膜层厚度小于50nm，则会导致Ga-Si回熔刻蚀，降低最后生长出的GaN薄膜质量；若SiO2掩膜层厚度大于100nm，则GaN薄膜层的生长愈合速度变慢。所述Si3N4缓冲层可以缓解Si与GaN晶格失配与热失配的问题，同时将Si衬底与GaN插入层隔开，可以避免Ga-Si回熔刻蚀。但当Si3N4缓冲层的厚度超过100nm，将会由于晶格失配而导致后续生长的GaN插入层开裂，当Si3N4缓冲层的厚度小于20nm，则会导致Ga-Si回熔刻蚀。
进一步，本发明的GaN薄膜，所述SiO2掩膜层为条状掩膜层，其中条状掩膜的宽度为1-3μm，各条状掩膜之间的间距为3-10μm。当条状掩膜之间的间距过大时，会使得在Si3N4缓冲层上生长出的GaN插入层以及GaN薄膜层很难愈合，需要长很厚的GaN薄膜层；间距过小则会导致GaN薄膜层愈合过快，生长的厚度不足，使位错密度增大。条状掩膜的宽度同样会影响GaN薄膜层的愈合效果；而且若条状掩膜的宽度太小还会导致对下方Si衬底的保护减弱，可能会在后续湿法刻蚀中将条状掩膜下方的Si衬底腐蚀掉，导致穿通。同时由于光刻工艺的限制，条状掩膜的宽度过小更会极大地提高生产成本。
进一步，本发明的GaN薄膜，所述的Si衬底的晶面包括(110)晶面和/或(112)晶面，所述用于生长GaN的晶面包括(-111)晶面和(-1-11)晶面。
本发明的一种GaN薄膜的制备方法，包括首先在Si衬底上制作一层图形化的SiO2掩膜层，并在Si衬底表面刻蚀出Si{111}晶面；然后在刻蚀出的Si{111}晶面上生长一层Si3N4缓冲层，在SiO2掩膜层和不参与GaN生长的Si3N4缓冲层上溅射一层溅射SiO2膜；最后在参与GaN生长的Si3N4缓冲层上依次生长GaN插入层和GaN薄膜层。
进一步，本发明的GaN薄膜的制备方法，具体包括如下步骤：
步骤1)、在Si衬底上用等离子体增强型化学气相沉积法(PECVD)生长一层50-100nm的SiO2膜，通过光刻显影的方法对覆盖SiO2膜的Si衬底进行光刻显影，制作出图形化的SiO2掩膜层，所述SiO2掩膜层为条状掩膜层，其中条状掩膜层的宽度为1-3μm，各条状掩膜层之间的间距为3-10μm；然后通过湿法刻蚀的方法，用质量浓度为20％-40％的KOH溶液在30℃-40℃的温度下腐蚀10-20min，在Si衬底表面刻蚀出凹槽，凹槽的侧面是Si{111}晶面；
步骤2)、将步骤1)中刻蚀出的Si{111}晶面氮化，即在所述Si{111}晶面上生长一层Si3N4缓冲层，在SiO2掩膜层和不参与GaN生长的Si3N4缓冲层上溅射一层溅射SiO2膜；
步骤3)、在参与GaN生长的Si3N4缓冲层上利用金属有机化学气相沉积法(MOCVD)依次生长GaN插入层和GaN薄膜层。
进一步，本发明的GaN薄膜的制备方法，所述步骤1)中的Si衬底的晶面包括(112)晶面和/或(110)晶面，所述Si{111}晶面包括(-1-11)晶面、(111)晶面、(-111)晶面以及(1-1-1)晶面。
进一步，本发明的GaN薄膜的制备方法，所述步骤2)中，氮化Si{111}晶面的过程具体包括，将刻蚀好的Si衬底放入真空石英管中，通入高纯氮气，在温度为1100-1300℃，气压为104-105Pa的条件下氮化1-2h，得到Si3N4缓冲层；合适的氮化温度不仅能很好地生成Si3N4更能够避免能源的浪费。而且需要保证石英管中为高纯氮气，并通过氮化时间的长短来控制生成Si3N4缓冲层的厚度。
进一步，所述通过在溅射过程中倾斜Si衬底来保证Si3N4缓冲层上用于生长GaN的面不被溅射SiO2膜覆盖，所述溅射SiO2膜的厚度为40-60nm；
进一步，所述所述溅射过程中Si衬底倾斜角度为10°-20°。
进一步，本发明的GaN薄膜的制备方法，其特征在于，所述步骤2)中用于生长Si3N4缓冲层和GaN薄膜的Si{111}晶面有(-1-11)晶面和(-111)晶面。
进一步，本发明的GaN薄膜的制备方法，其特征在于，所述步骤3)中所述的GaN插入层的生长条件为：温度1000-1100℃、反应腔内的气压为500-600Torr、Ⅴ/Ⅲ比为400-500，GaN插入层的厚度控制在200-400nm。且高压低Ⅴ/Ⅲ比会推迟岛与岛的合并时间，能够在合并前先长出一定厚度的GaN插入层从而使穿透位错的密度降低，有利于形核。此外，由于GaN插入层的存在，避免了使用异质衬底生长GaN薄膜层时产生的晶格失配和热失配的问题，从而提高GaN薄膜层的质量。
进一步，所述步骤3)中所述的GaN薄膜层的生长条件为：温度1100-1300℃、反应腔内的气压为250-350Torr、Ⅴ/Ⅲ比为1000-5000，GaN薄膜层的厚度控制在1000-2000nm。低压高Ⅴ/Ⅲ比有助于加速合并过程，使GaN薄膜层快速形成平整的表面。采用两步法可以获得光滑平整的表面。生长的GaN薄膜层厚度太薄的话可能会导致GaN薄膜层愈合的不是太好，表面不平整。在具体操作过程中，可以根据需要自行调整制备适合厚度的GaN薄膜。
进一步，步骤3)中生长的GaN薄膜层的晶面包括(1-100)晶面和(11-20)晶面；
进一步，所述步骤3)中所需的镓源和氮源分别为三甲基镓和氨气。
与现有技术相比，本发明具有以下有益的技术效果：
本发明的GaN薄膜，通过在Si图形衬底上外延生长非极性GaN薄膜的方法制得，不仅成本低廉，且性能优良能够广泛地用于器件的制作中。所述GaN薄膜中的缓冲层Si3N4层为有序的密排六方结构，不仅可以很好的解决晶格失配和热失配所带来的问题，而且可以避免Ga-Si回熔刻蚀，以及弛豫和补偿后续GaN生长累积的残余应力。其中GaN插入层可以降低生长过程中产生的位错，从而提高GaN薄膜层的质量。本发明所生长的GaN薄膜层为非极性的GaN，非极性的GaN在发光器件中有十分良好的性能，可以避免由于极化所引起量子限制斯塔克效应(QCSE)。
附图说明
图1是本发明实施例1所述GaN薄膜的结构示意图；
图2是本发明实施例2所述GaN薄膜的结构示意图；
图3是本发明实施例3和实施例4所述的SiO2掩膜层的结构示意图；
图4是本发明实施例3详细过程示意图；
图5是本发明实施例3完成步骤1后的结构示意图；
图6是本发明实施例4完成步骤1后的结构示意图。
其中，1.Si衬底，1a.(110)晶向Si衬底，1b.(112)晶向Si衬底，2.SiO2膜，2a.SiO2掩膜层，3.Si3N4缓冲层，4.溅射SiO2膜，5.GaN插入层，6.GaN薄膜层。
具体实施方式
下面结合具体的实施例对本发明做进一步的详细说明。
实施例1：
如图1所示，一种GaN薄膜，包括Si衬底1a和位于Si衬底1a上图形化的SiO2掩膜层2a，所述Si衬底1a的Si{111}晶面上有Si3N4缓冲层3，所述SiO2掩膜层2a和不参与GaN生长的Si3N4缓冲层3上有溅射SiO2膜4；所述参与GaN生长的Si3N4缓冲层3上有GaN插入层5，所述GaN插入层5上生长有GaN薄膜层6。所述SiO2掩膜层2a的厚度为50-100nm，且为条状掩膜层，其中条状掩膜层的宽度为1-3μm，各条状掩膜层之间的间距为3-10μm。所述不参与GaN生长的Si3N4缓冲层3厚度为20-100nm，所述GaN插入层5的厚度为200-400nm，所述溅射SiO2膜4的厚度为40-60nm，所述GaN薄膜层6的厚度为1000-2000nm。
其中，所述的GaN薄膜的Si衬底1a为(110)晶向，Si衬底1a的晶面包括(110)晶面，所述刻蚀出的Si{111}包括(-111)晶面和(1-1-1)晶面；用于生长Si3N4缓冲层3的Si{111}晶面为(-111)晶面；生长出所述GaN薄膜层6的晶面为(11-20)晶面。
其中，Si衬底上的Si3N4缓冲层，其晶格匹配程度和热膨胀系数均介于Si和GaN之间，见下表1。在Si3N4缓冲层上生长的GaN插入层，其作用是用于形核，在岛与岛合并前生长一定的厚度来降低位错密度；最后生长的GaN薄膜层是我们的目标产物。该层是在GaN插入层上生长的，属于同质外延，因此本发明的GaN薄膜不存在晶格失配和热失配的问题。此外，本发明得到的非极性的GaN薄膜性能良好。传统的GaN基发光二极管(LED)都是在[0001]c轴方向上生长的，这是一个高度极性取向，因此在器件中常常会发生自发极化和压电极化的现象。极化效应会在GaN中引起能带的倾斜，从而在电子器件中形成高密度的二维电子气，这造成电子与空穴在空间上分离，使得两者的波函数交叠变小，材料的发光效率降低，而且发光波长会产生红移现象，这被称为量子限制斯塔克效应(QCSE)。而对于非极性以及半极性材料而言，由于沿着材料生长方向的极化效应消失或者削弱，因此可以消除QCSE，从而提高器件性能。
表1不同材料参数
Figure BDA0002695598990000071
实施例2：
如图2所示：本实施例2与实施例1的不同之处仅在于，所述的GaN薄膜的Si衬底1b为(112)晶向，Si衬底1b的晶面包括(112)晶面，所述刻蚀出的Si{111}包括(-1-11)晶面和(111)晶面；用于生长Si3N4缓冲层3的Si{111}晶面为(-1-11)晶面；生长出所述GaN薄膜层6的晶面为(1-100)晶面。
实施例3：
一种GaN薄膜的制备方法，具体包括如下步骤：
步骤1)、在Si(110)的衬底1a上用等离子体增强型化学气相沉积法(PECVD)生长一层50-100nm的SiO2膜2，通过光刻工艺将光刻板图案转移到SiO2膜2上，然后通过感应耦合等离子体(ICP)刻蚀工艺制作出图形化的SiO2掩膜层2a，所述SiO2掩膜层2a为条状掩膜层，其中条状掩膜层的宽度为1-3μm，各条状掩膜层之间的间距为3-10μm，如图3所示；然后通过湿法刻蚀的方法，用质量浓度为20％-40％的KOH溶液在30℃-40℃的温度下腐蚀10-20min，在Si衬底1a表面刻蚀形成凹槽，凹槽的侧面是Si{111}晶面，包括(-111)晶面和(1-1-1)晶面，如图5所示；
步骤2)、将步骤1)中刻蚀出的Si{111}晶面氮化，即在所述Si{111}晶面上生长一层Si3N4缓冲层3。氮化Si{111}晶面的过程具体包括，将刻蚀好的Si衬底1a放入真空石英管中，通入高纯氮气，在温度为1100-1300℃，压力为104-105Pa的条件下氮化1-2h，得到Si3N4缓冲层3；通过在溅射过程中倾斜Si衬底1a来保证Si3N4缓冲层3上用于生长GaN的面不被溅射SiO2膜4覆盖，倾斜角度为10°-20°。所述溅射SiO2膜4的厚度为40-60nm；在SiO2掩膜层2a和不参与GaN生长的Si3N4缓冲层3上溅射一层溅射SiO2膜4；
其中，用于生长Si3N4缓冲层3的Si{111}晶面为(-111)晶面。
步骤3)、在参与GaN生长的Si3N4缓冲层3上利用金属有机化学气相沉积法(MOCVD)依次生长GaN插入层5和GaN薄膜层6。所述的GaN插入层5的生长条件为：温度1000-1100℃、反应腔内的气压为500-600Torr、Ⅴ/Ⅲ比为400-500，GaN插入层5的厚度控制在200-400nm；所述的GaN薄膜层6的生长条件为：温度1100-1300℃、反应腔内的气压为250-350Torr、Ⅴ/Ⅲ比为1000-5000，GaN薄膜层6的厚度控制在1000-2000nm。生长出的GaN薄膜层6的晶面为(11-20)晶面；所需的镓源和氮源分别为三甲基镓和氨气。
实施例4：
一种GaN薄膜的制备方法，本实施例4与实施例3的不同之处仅在于：
所述的GaN薄膜的Si衬底1b为(112)晶向，Si衬底1a的晶面包括(112)晶面，所述湿法刻蚀出的Si{111}晶面包括(-1-11)晶面和(111)晶面，如图6所示；用于生长Si3N4缓冲层3的Si{111}晶面为(-1-11)晶面；最终生长出的GaN薄膜层6的晶面为(1-100)晶面。

Claims (10)

1.一种GaN薄膜，其特征在于：所述GaN薄膜包括Si衬底(1)和位于Si衬底(1)上图形化的SiO2掩膜层(2a)，所述Si衬底(1)的Si{111}晶面上有Si3N4缓冲层(3)，所述SiO2掩膜层(2a)和不参与GaN生长的Si3N4缓冲层(3)上有溅射SiO2膜(4)；所述参与GaN生长的Si3N4缓冲层(3)上有GaN插入层(5)，所述GaN插入层(5)上生长有GaN薄膜层(6)。
2.根据权利要求1所述的GaN薄膜，其特征在于；所述SiO2掩膜层(2a)的厚度为50-100nm，所述不参与GaN生长的Si3N4缓冲层(3)厚度为20-100nm，所述GaN插入层(5)的厚度为200-400nm，所述溅射SiO2膜(4)的厚度为40-60nm，所述GaN薄膜层(6)的厚度为1000-2000nm。
3.根据权利要求1或2所述的GaN薄膜，其特征在于，所述SiO2掩膜层(2a)为条状掩膜层，其中条状掩膜层的宽度为1-3μm，各条状掩膜层之间的间距为3-10μm。
4.根据权利要求3所述的GaN薄膜，其特征在于，所述的Si衬底(1)包括(110)晶向Si衬底(1a)和(112)晶向Si衬底(1b)，所述Si衬底(1)的晶面包括(110)晶面和/或(112)晶面，所述用于生长GaN的晶面包括(-1-11)晶面和(-111)晶面。
5.一种GaN薄膜的制备方法，其特征在于，所述制备方法包括首先在Si衬底(1)上制作一层图形化的SiO2掩膜层(2a)，并在Si衬底(1)表面刻蚀出Si{111}晶面；然后在刻蚀出的Si{111}晶面上生长一层Si3N4缓冲层(3)，在SiO2掩膜层(2a)和不参与GaN生长的Si3N4缓冲层(3)上溅射一层溅射SiO2膜(4)；最后在参与GaN生长的Si3N4缓冲层(3)上依次生长GaN插入层(5)和GaN薄膜层(6)。
6.根据权利要求5所述的GaN薄膜的制备方法，具体包括如下步骤：
步骤1)、在Si衬底(1)上用等离子体增强型化学气相沉积法(PECVD)生长一层50-100nm的SiO2膜(2)，通过光刻工艺将光刻板图案转移到SiO2膜(2)上，然后通过感应耦合等离子体(ICP)刻蚀工艺制作出图形化的SiO2掩膜层(2a)，所述SiO2掩膜层(2a)为条状掩膜层，其中条状掩膜层的宽度为1-3μm，各条状掩膜层之间的间距为3-10μm；然后通过湿法刻蚀的方法，用质量浓度为20％-40％的KOH溶液在30℃-40℃的温度下腐蚀10-20min，在Si衬底(1)表面刻蚀形成凹槽，凹槽的侧面是Si{111}晶面；
步骤2)、将步骤1)中刻蚀出的Si{111}晶面氮化，即在所述Si{111}晶面上生长一层Si3N4缓冲层(3)，在SiO2掩膜层(2a)和不参与GaN生长的Si3N4缓冲层(3)上溅射一层溅射SiO2膜(4)；
步骤3)、在参与GaN生长的Si3N4缓冲层(3)上利用金属有机化学气相沉积法(MOCVD)依次生长GaN插入层(5)和GaN薄膜层(6)。
7.根据权利要求6所述的GaN薄膜的制备方法，其特征在于，所述步骤1)中的Si衬底(1)的晶面包括(112)晶面和/或(110)晶面，所述Si{111}晶面包括(-1-11)晶面、(111)晶面、(-111)晶面以及(1-1-1)晶面。
8.根据权利要求7所述的GaN薄膜的制备方法，其特征在于，所述步骤2)中，氮化Si{111}晶面的过程具体包括，将刻蚀好的Si衬底(1)放入真空石英管中，通入高纯氮气，在温度为1100-1300℃，压力为104-105Pa的条件下氮化1-2h，得到Si3N4缓冲层(3)；
进一步地，通过在溅射过程中倾斜Si衬底(1a)来保证Si3N4缓冲层(3)上用于生长GaN的面不被溅射SiO2膜(4)覆盖，所述溅射SiO2膜(4)的厚度为40-60nm；
进一步地，所述溅射过程中Si衬底(1)倾斜角度为10°-20°。
9.根据权利要求8所述的GaN薄膜的制备方法，其特征在于，所述步骤2)中用于生长Si3N4缓冲层(3)的Si{111}晶面有(-1-11)晶面和(-111)晶面。
10.根据权利要求9所述的GaN薄膜的制备方法，其特征在于，所述步骤3)中所述的GaN插入层(5)的生长条件为：温度1000-1100℃、反应腔内的气压为500-600Torr、Ⅴ/Ⅲ比为400-500，GaN插入层(5)的厚度控制在200-400nm；
进一步，所述步骤3)中所述的GaN薄膜层(6)的生长条件为：温度1100-1300℃、反应腔内的气压为250-350Torr、Ⅴ/Ⅲ比为1000-5000，GaN薄膜层(6)的厚度控制在1000-2000nm。
进一步地，步骤3)中生长的GaN薄膜层(6)的晶面包括(1-100)晶面和(11-20)晶面；
进一步地，所述步骤3)中所需的镓源和氮源分别为三甲基镓和氨气。
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