CN112133748A - HEMT device with large-size Si substrate and preparation method thereof - Google Patents
HEMT device with large-size Si substrate and preparation method thereof Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 33
- 238000002360 preparation method Methods 0.000 title abstract description 9
- 238000010899 nucleation Methods 0.000 claims abstract description 42
- 230000006911 nucleation Effects 0.000 claims abstract description 41
- 230000004888 barrier function Effects 0.000 claims abstract description 14
- 239000002073 nanorod Substances 0.000 claims abstract description 7
- 229910002601 GaN Inorganic materials 0.000 claims description 45
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 45
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 24
- 239000010408 film Substances 0.000 claims description 24
- 229910052710 silicon Inorganic materials 0.000 claims description 24
- 239000010703 silicon Substances 0.000 claims description 24
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 11
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 10
- 238000005516 engineering process Methods 0.000 claims description 7
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 7
- 239000010409 thin film Substances 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 238000001556 precipitation Methods 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 5
- 239000002210 silicon-based material Substances 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- IWBUYGUPYWKAMK-UHFFFAOYSA-N [AlH3].[N] Chemical compound [AlH3].[N] IWBUYGUPYWKAMK-UHFFFAOYSA-N 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 239000002061 nanopillar Substances 0.000 claims 3
- 230000008021 deposition Effects 0.000 claims 1
- 238000000206 photolithography Methods 0.000 claims 1
- 238000004377 microelectronic Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 description 6
- 239000013078 crystal Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 238000002441 X-ray diffraction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
Abstract
The invention discloses a HEMT device with a large-size Si substrate and a preparation method thereof, belonging to the technical field of microelectronics, and comprising a substrate L1, a nanorod layer L2, a nucleation layer L3, a rapid merging layer L4, a high-resistance layer L5, a channel layer L6 and a barrier layer L7 which are sequentially stacked from bottom to top.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and relates to epitaxial preparation of a semiconductor device, namely an HEMT device with a large-size Si substrate and a preparation method thereof.
Background
The third generation Semiconductor material, i.e. the Wide Band Gap Semiconductor (WBGS) Semiconductor material, is developed following the first generation silicon, germanium, the second generation gallium arsenide, indium phosphide, etc. Among the third generation semiconductor materials, gallium nitride (GaN) has superior properties such as wide band gap, direct band gap, high breakdown electric field, lower dielectric constant, high electron saturation drift velocity, strong radiation resistance, and good chemical stability, and becomes a key semiconductor material for manufacturing a new generation of microelectronic devices and circuits following germanium, silicon, and gallium arsenide.
High electron mobility transistors with an ALGaN/GaN heterojunction as a core become a main research direction, the cost of the existing gallium nitride electronic device is still high, and the epitaxial gallium nitride-based HEMT based on the large-size silicon substrate is an important way for reducing the cost. The silicon substrate has low cost, large size, easy preparation and good thermal conductivity, and can be compatible with the traditional silicon process, so that the silicon substrate becomes the preferred material for the epitaxy of the gallium nitride device. However, the gallium nitride epitaxial film has huge lattice mismatch and thermal mismatch with the silicon substrate, so that the dislocation density of the gallium nitride epitaxial film is high, the warpage is large, and edge cracks are caused. The preparation of the gallium nitride electronic device is difficult, and the wide application of the gallium nitride electronic device is limited.
Disclosure of Invention
The invention aims to overcome the problems and provide a HEMT device with a large-size Si substrate and a preparation method thereof, which aim to improve the lattice quality of a gallium nitride epitaxial film on the silicon substrate and improve the performance of the device.
The silicon nanorod layer is inserted between the silicon substrate and the gallium nitride epitaxial layer, so that the cracking problem caused by thermal mismatch can be effectively solved, and the defects caused by stress can be well relieved.
The nucleation layer is grown by two growth methods, so that the meltback etching between the GaN and the Si can be effectively prevented, a layer of ALN layer with better crystal growth quality and complete film coverage can be provided by growing ALN by PECVD, and then the ALGaN/GaN nucleation layer is fed back to the MOCVD for growing the ALGaN/GaN nucleation layer, so that the stress engagement and the seed crystal are improved for the subsequent GaN filling layer.
And then, the two-dimensional and three-dimensional alternate growth modes are adopted to realize rapid combination to obtain a smooth gallium nitride surface, and the defects can be effectively annihilated by the two-dimensional and three-dimensional alternate growth.
The device structure comprises a substrate, a nanorod layer, a nucleation layer, a rapid merging layer, a high-resistance layer, a channel layer and a barrier layer, wherein all the layers are sequentially arranged from bottom to top.
Preferably, the size of the substrate is 2-8inch, and the material is silicon.
Preferably, the nano-column layer is a silicon nano-column which is formed by Molecular Beam Epitaxy (MBE) precipitation or a photoetching technology and is arranged in order, the diameter of the silicon nano-column is 10 nm-2 um, the height of the silicon nano-column is 50 nm-2 um, and the distance between the column and the center of the column is 50 nm-4 um.
Preferably, the nucleation layer comprises a lower nucleation layer I and an upper nucleation layer II, the first nucleation layer is an aluminum-nitrogen layer grown by PECVD and has the thickness of 50nm-300nm, and the second nucleation layer is an aluminum-gallium-nitrogen/gallium-nitrogen layer grown by MOCVD and has the thickness of 20-150 nm.
Preferably, the rapid merging layer is grown by MOCVD, the temperature is increased in a variable speed manner, the V/III ratio is changed, and the thickness range of the film is 0.5-2 um by using a two-dimensional/three-dimensional alternative growth mode.
Preferably, the high-resistance layer is a semi-insulating high-quality gallium nitride thin film layer formed by the unintentional doping growth of MOCVD growth, and the thickness of the thin film is in the range of 1-3 um.
Preferably, the channel layer is a semi-insulating high-quality gallium nitride channel thin film layer grown by MOCVD, and the thickness range of the thin film is 50-200nm.
Preferably, the structural formula of the barrier layer is ALxGa1-xN with a thickness of 10-35nm, wherein x is 10-30%.
A preparation method of an HEMT device with a large-size Si substrate comprises the following steps:
(1) providing a substrate, wherein the substrate is made of silicon materials and has the size range of 2-8 inch;
(2) the silicon nano-columns which are formed by Molecular Beam Epitaxy (MBE) precipitation or photoetching technology and are arranged regularly have the diameter of 10 nm-2 um and the height of 50 nm-2 um, and the distance between the center of the column and the center of the column is 50 nm-4 um;
(3) depositing a first nucleating layer, namely an ALN layer by adopting PECVD (plasma enhanced chemical vapor deposition) with the vacuum degree lower than 2 x 10-3Pa, the temperature is 200-500 ℃, the growth is carried out in the mixed gas environment of N2/Ar, the growth speed is about 100nm/min, and the total thickness is 20-300 nm;
(4) after the growth of the nucleation layer is finished, transferring to MOCVD to grow a nucleation layer II which is an ALGaN/GaN material, wherein the growth temperature is 500-550 ℃, and the film thickness is 50-150 nm;
(5) continuously growing a rapid merging layer on the nucleation layer by using MOCVD, and realizing two-dimensional/three-dimensional alternate growth by adopting temperature variable speed rise and V/III ratio change, wherein the specific steps are as follows:
the first section grows for 4min, the temperature is from 1040 ℃ to 1080 ℃, and the V/III ratio is reduced by 40-50 percent;
the second stage is constantly growing for 2 min;
growing in the third stage for 4min at 1070-1110 deg.c and V/III ratio increased by 40-45%;
the fourth section grows constantly for 2 min;
the total thickness is 0.5um-2 um;
(6) and continuing to grow the unintentionally doped gallium nitride high-resistance layer, wherein the thickness of the film is in the range of 1-3 um, and the growth temperature is 1120-1150 ℃.
(7) Growing a gallium nitride channel layer on the high-resistance layer, wherein the thickness range of the film is 50-200 nm;
(8) the structural formula of the barrier layer grown on the channel layer is ALGaN, the thickness is 10-35nm, and the temperature is 800-1000 ℃.
Compared with the prior art, the invention has the following advantages: provides a new structure and a growing method, realizes the high lattice quality of the gallium nitride epitaxial film on the silicon substrate, and improves the performance of the device. The main technology comprises the following steps:
1. the silicon nanorod layer is inserted between the silicon substrate and the gallium nitride epitaxial layer, so that the problem of cracking caused by thermal mismatch can be effectively solved, and the defects caused by stress can be well relieved.
2. The nucleation layer is grown by two growth methods, so that the remelting etching between GaN and Si can be effectively prevented, a bit of pre-stress is provided for the gallium nitride epitaxial layer, a layer of ALN layer with better crystal growth quality and complete film coverage can be provided for growing ALN by PECVD, and then the ALN/GaN nucleation layer is sent back to MOCVD to grow the ALGaN/GaN nucleation layer, so that stress engagement and seed crystal are improved for the subsequent GaN combined layer.
3. The two-dimensional and three-dimensional alternate growth modes are rapidly combined by changing the temperature and the V/III ratio to obtain a flat gallium nitride surface, and the defects can be effectively annihilated by the two-dimensional and three-dimensional alternate growth. The new structure and the long method can effectively improve the crystal lattice quality of the epitaxial layer of the gallium nitride HEMT, thereby improving the characteristics of the HEMT device such as electron mobility, breakdown voltage, leakage current and the like.
Drawings
FIG. 1 is a schematic structural diagram of the present invention.
Fig. 2 is a schematic structural view of the nucleation layer L3 according to the present invention.
FIG. 3 shows the results of the experiment according to example 1.
Wherein: l1-substrate, L2-nanorod layer, L3-nucleation layer, L4-rapid merging layer, L5-high resistance layer, L6-channel layer and L7-barrier layer.
Detailed Description
In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further described with the specific embodiments.
As shown in fig. 1 and fig. 2, the HEMT device of the large Si substrate of the present invention includes a substrate L1, a nanorod layer L2, a nucleation layer L3, a rapid merging layer L4, a high resistance layer L5, a channel layer L6, and a barrier layer L7 stacked in this order from bottom to top,
example 1
(1) A substrate L1 is provided, which is a silicon material with dimensions in the range of 2-8 inch.
(2) The silicon nano-columns L2 which are formed by adopting Molecular Beam Epitaxy (MBE) precipitation or photoetching technology and are regularly arranged have the diameter of 10 nm-2 um and the height of 50 nm-2 um, and the distance between the center of the column and the center of the column is 50 nm-4 um.
(3) The nucleation layer L3_1 is deposited as an ALN layer using PECVD. Vacuum degree lower than 2X 10-3Pa, the temperature is 200 ℃, the growth is carried out in the mixed gas environment of N2/Ar, the growth speed is about 100nm/min, and the total thickness is 150 nm.
(4) After the growth of the nucleation layer L3_1 is finished, turning to MOCVD to grow a nucleation layer L3_2 which is an ALGaN/GaN material, wherein the growth temperature is 500 ℃, and the film thickness is 50 nm.
(5) The rapid merged layer L4 was grown on the nucleation layer using MOCVD, and two-dimensional/three-dimensional alternating growth was achieved by using a temperature ramp-up, v/iii ratio change, for example: the first stage of growth for 4min, the temperature is reduced by 40% from 1040 → 1070, V/III ratio; the second stage is constantly growing for 2 min; the third stage is 4min growth, the temperature is 1070 → 1100, and the V/III ratio is increased by 40 percent; the fourth stage was constantly grown for 2 min. The total thickness is 1 um.
(6) And continuing to grow the unintentionally doped gallium nitride high-resistance layer L5, wherein the thickness of the film is in the range of 1um-3um, and the growth temperature is between 1120 ℃ and 1150 ℃.
(7) And growing a gallium nitride channel layer L6 on the high-resistance layer, wherein the thickness of the film is 50-200nm.
(8) The barrier layer L7 growing on the channel layer has a structural formula of ALGaN, the thickness of the barrier layer is 10-35nm, and the temperature is 800-1000 ℃.
Example 2
(1) A substrate L1 is provided, which is a silicon material with dimensions in the range of 2-8 inch.
(2) The silicon nano-columns L2 which are formed by adopting Molecular Beam Epitaxy (MBE) precipitation or photoetching technology and are regularly arranged have the diameter of 10 nm-2 um and the height of 50 nm-2 um, and the distance between the center of the column and the center of the column is 50 nm-4 um.
(3) The nucleation layer L3_1 is deposited as an ALN layer using PECVD. Vacuum degree lower than 2X 10-3Pa, the temperature is 250 ℃, the growth is carried out in the mixed gas environment of N2/Ar, the growth speed is about 100nm/min, and the total thickness is 200nm.
(4) After the growth of the nucleation layer L3_1 is finished, turning to MOCVD to grow a nucleation layer L3_2 which is an ALGaN/GaN material, wherein the growth temperature is 550 ℃, and the film thickness is 100 nm.
(5) The rapid merged layer L4 was grown on the nucleation layer using MOCVD, and two-dimensional/three-dimensional alternating growth was achieved by using a temperature ramp-up, v/iii ratio change, for example: the first stage is 4min growth, the temperature is 1050 → 1080, and the V/III ratio is reduced by 50%; the second stage is constantly growing for 2 min; the third stage is 4min growth, the temperature is from 1080 → 1110, and the V/III ratio is increased by 40%; the fourth stage was constantly grown for 2 min. The total thickness is 0.5um-2 um.
(6) And continuing to grow the unintentionally doped gallium nitride high-resistance layer L5, wherein the thickness of the film is in the range of 1um-3um, and the growth temperature is between 1120 ℃ and 1150 ℃.
(7) And growing a gallium nitride channel layer L6 on the high-resistance layer, wherein the thickness of the film is 50-200nm.
(8) The barrier layer L7 growing on the channel layer has a structural formula of ALGaN, the thickness of the barrier layer is 10-35nm, and the temperature is 800-1000 ℃.
Example 3
(1) A substrate L1 is provided, which is a silicon material with dimensions in the range of 2-8 inch.
(2) The silicon nano-columns L2 which are formed by adopting Molecular Beam Epitaxy (MBE) precipitation or photoetching technology and are regularly arranged have the diameter of 10 nm-2 um and the height of 50 nm-2 um, and the distance between the center of the column and the center of the column is 50 nm-4 um.
(3) The nucleation layer L3_1 is deposited as an ALN layer using PECVD. Vacuum degree lower than 2X 10-3Pa, the temperature is 500 ℃, the growth is carried out in the mixed gas environment of N2/Ar, the growth speed is about 100nm/min, and the total thickness is 250 nm.
(4) After the growth of the nucleation layer L3_1 is finished, turning to MOCVD to grow a nucleation layer L3_2 which is an ALGaN/GaN material, wherein the growth temperature is 550 ℃, and the film thickness is 130 nm.
(5) The rapid merged layer L4 was grown on the nucleation layer using MOCVD, and two-dimensional/three-dimensional alternating growth was achieved by using a temperature ramp-up, v/iii ratio change, for example: the first stage of growth for 4min, the temperature is reduced by 45% from 1040 → 1070, V/III ratio; the second stage is constantly growing for 2 min; the third stage is 4min growth, the temperature is 1070 → 1100, and the V/III ratio is increased by 45 percent; the fourth stage was constantly grown for 2 min. The total thickness is 1.5 um.
(6) And continuing to grow the unintentionally doped gallium nitride high-resistance layer L5, wherein the thickness of the film is in the range of 1um-3um, and the growth temperature is between 1120 ℃ and 1150 ℃.
(7) And growing a gallium nitride channel layer L6 on the high-resistance layer, wherein the thickness of the film is 50-200nm.
(8) The barrier layer L7 growing on the channel layer has a structural formula of ALGaN, the thickness of the barrier layer is 10-35nm, and the temperature is 800-1000 ℃.
Fig. 3 shows a comparison graph of X-ray diffraction (XRD) test results of the epitaxial layer of the device prepared under the conditions of embodiment 1 and the epitaxial layer of the conventional device, and the data comparison under the same test conditions shows that the full width at half maximum of the (002) plane diffraction peak of the epitaxial layer of the gallium nitride device prepared under the conditions of embodiment 1 is 10% to 15% smaller than the full width at half maximum of the (002) plane of the epitaxial layer of the conventional gallium nitride device, and the lattice quality of the epitaxial layer is obviously improved.
It will be appreciated by those skilled in the art that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The embodiments disclosed above are therefore to be considered in all respects as illustrative and not restrictive. All changes which come within the scope of or equivalence to the invention are intended to be embraced therein.
Claims (9)
1. The HEMT device with the large-size Si substrate is characterized by comprising a substrate (L1), a nanorod layer (L2), a nucleation layer (L3), a rapid merging layer (L4), a high-resistance layer (L5), a channel layer (L6) and a barrier layer (L7) which are sequentially stacked from bottom to top.
2. The HEMT device of claim 1, wherein said substrate (L1) is 2-8inch in size and is made of silicon.
3. The HEMT device with the large-size Si substrate as claimed in claim 1, wherein the nanopillar layer (L2) is an orderly-arranged silicon nanopillar formed by Molecular Beam Epitaxy (MBE) deposition or photolithography, and has a diameter of 10 nm-2 um and a height of 50 nm-2 um, and the distance between the centers of the nanopillars is 50 nm-4 um.
4. The HEMT device of claim 1, wherein said nucleation layer (L3) comprises a lower nucleation layer (L3-1) and an upper nucleation layer (L3-2), said nucleation layer (L3-1) is an aluminum-nitrogen layer grown by PECVD and has a thickness of 50nm-300nm, and said nucleation layer (L3-2) is an aluminum-gallium-nitrogen/gallium-nitrogen layer grown by MOCVD and has a thickness of 20-150 nm.
5. The HEMT device of claim 1, wherein said rapid merged layer (L4) is MOCVD grown with a two-dimensional/three-dimensional alternating growth regime of film thickness ranging from 0.5um to 2um with a temperature ramp-up, v/iii ratio variation.
6. The HEMT device of claim 1, wherein said high resistance layer (L5) is a semi-insulating high quality gallium nitride thin film layer grown by unintentional doping growth grown by MOCVD, and the thickness of the thin film is in the range of 1um-3 um.
7. The HEMT device of claim 1, wherein said channel layer (L6) is a semi-insulating high quality gallium nitride channel thin film layer grown by MOCVD with a film thickness in the range of 50-200nm.
8. The HEMT device of a large-size Si substrate according to claim 1, wherein the structural formula of the barrier layer (L7) is ALxGa1-xN with a thickness of 10-35nm, wherein x is 10-30%.
9. A method for manufacturing a HEMT device of a large-size Si substrate according to any one of claims 1 to 8, comprising the steps of:
(1) providing a substrate (L1), wherein the substrate is made of silicon material and has the size ranging from 2 inch to 8 inch;
(2) the silicon nano-columns (L2) which are formed by Molecular Beam Epitaxy (MBE) precipitation or photoetching technology and are arranged orderly have the diameter of 10 nm-2 um and the height of 50 nm-2 um, and the distance between the center of the column and the center of the column is 50 nm-4 um;
(3) depositing a nucleation layer (L3_1) as ALN layer by PECVD in a vacuum degree lower than 2 × 10-3Pa, the temperature is 200-500 ℃, the growth is carried out in the mixed gas environment of N2/Ar, the growth speed is about 100nm/min, and the total thickness is 50-300 nm;
(4) after the growth of the nucleation layer (L3_1) is finished, transferring to MOCVD to grow the nucleation layer (L3_2), wherein the nucleation layer is made of ALGaN/GaN material, the growth temperature is 500-550 ℃, and the film thickness is 50-150 nm;
(5) continuing to grow a rapid merged layer (L4) on the nucleation layer by MOCVD, and realizing two-dimensional/three-dimensional alternate growth by adopting temperature variable speed rise and V/III ratio change, which are as follows:
the first section grows for 4min, the temperature is from 1040 ℃ to 1080 ℃, and the V/III ratio is reduced by 40-50 percent;
the second stage is constantly growing for 2 min;
growing in the third stage for 4min at 1070-1110 deg.c and V/III ratio increased by 40-45%;
the fourth section grows constantly for 2 min;
the total thickness is 0.5um-2 um;
(6) continuing to grow an unintentionally doped gallium nitride high-resistance layer (L5), wherein the film thickness is in the range of 1um-3um, and the growth temperature is between 1120 ℃ and 1150 ℃.
(7) Growing a gallium nitride channel layer (L6) on the high-resistance layer, wherein the thickness of the film is 50-200 nm;
(8) the structural formula of the barrier layer (L7) growing on the channel layer is ALGaN, the thickness is 10-35nm, and the temperature is 800-1000 ℃.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110049681A1 (en) * | 2009-08-31 | 2011-03-03 | Martin Henning Albrecht Vielemeyer | Semiconductor Structure and a Method of Forming the Same |
| CN109103070A (en) * | 2018-07-20 | 2018-12-28 | 北京大学 | Method based on nano graph silicon substrate preparation high quality thick film AlN |
| CN110752146A (en) * | 2019-10-28 | 2020-02-04 | 北京华进创威电子有限公司 | Method for growing gallium nitride film on silicon substrate |
| CN111593408A (en) * | 2020-06-02 | 2020-08-28 | 无锡吴越半导体有限公司 | Oversized self-supporting gallium nitride single crystal and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110049681A1 (en) * | 2009-08-31 | 2011-03-03 | Martin Henning Albrecht Vielemeyer | Semiconductor Structure and a Method of Forming the Same |
| CN109103070A (en) * | 2018-07-20 | 2018-12-28 | 北京大学 | Method based on nano graph silicon substrate preparation high quality thick film AlN |
| CN110752146A (en) * | 2019-10-28 | 2020-02-04 | 北京华进创威电子有限公司 | Method for growing gallium nitride film on silicon substrate |
| CN111593408A (en) * | 2020-06-02 | 2020-08-28 | 无锡吴越半导体有限公司 | Oversized self-supporting gallium nitride single crystal and preparation method thereof |
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