CN112130053B

CN112130053B - Method for synchronously testing chip functions on ATE

Info

Publication number: CN112130053B
Application number: CN202010798718.5A
Authority: CN
Inventors: 曹佳; 鲁豪
Original assignee: Shanghai Huahong Integrated Circuit Co Ltd; Beijing CEC Huada Electronic Design Co Ltd
Current assignee: Shanghai Huahong Integrated Circuit Co Ltd; Beijing CEC Huada Electronic Design Co Ltd
Filing date: 2020-08-11
Publication date: 2024-05-14
Anticipated expiration: 2040-08-11

Abstract

The invention discloses a synchronous test method capable of realizing test synchronization by using an internal clock of a chip on ATE (automatic test equipment). According to the method, chips with different test completion time and test response time can be synchronized based on the internal clock of the chip, so that multi-chip synchronous test during test based on the internal clock of the chip is realized in a mass production stage.

Description

Method for synchronously testing chip functions on ATE

Technical Field

The invention is used in the field of mass production test of integrated circuit chips, and particularly relates to a method for realizing synchronous test by counting the number of externally input low-frequency clocks through a chip internal timer/counter on ATE in the mass production process.

Background

In the mass production test process of the integrated circuit chip, some functions of the chip need to be tested, the function test needs to use an internal clock of the chip, when the integrated circuit chip works based on the internal clock, due to the difference of clock frequencies of the integrated circuit chip, the test items with shorter test time can be ignored, the accumulated clock running errors of the integrated circuit chip during the test can be ignored, and the ATE can realize synchronous test. In the face of test items with long test time, the accumulated clock running error is larger when the integrated circuit chip is tested, and the ATE is difficult to realize synchronous test.

At present, when a chip uses an internal clock for functional test, the following 3-point difficulties are mainly faced:

1. In integrated circuit chips, the internal clock of the chip is still distributed over a range after calibration. If the target frequency of the clock in the chip is X, the specification of the clock frequency of the chip is +/-5% of the target frequency, and the difference between the upper limit and the lower limit of the frequency is (1- (X-0.05X)/(X+0.05X)). 100%. Apprxeq. 9.524%. I.e. when the clock frequency specification is + -5% of the target frequency, the difference between the slowest chip and the fastest chip of the internal clock meeting the clock frequency specification is about 9.524% of the target frequency. When the function test is performed based on the internal clock of the chip, the difference of the internal clock can be accumulated along with the running number of instructions, and obvious asynchronous phenomenon occurs when test response is output after the test is completed.

2. Most ATE devices at present provide a matching function, and synchronous test can be carried out on chips with asynchronous responses, but the function requires that clock difference between different responses is within 65535 clocks, and if the clock number difference between different responses exceeds 65535, ATE can be directly judged to be invalid, so that false detection is caused. That is, when the clock number difference between different responses caused by the clock running error accumulated at the time of the test is accumulated to exceed 65535 clocks, the "matching" function cannot be adopted.

3. At present, some ATE (automatic test equipment) does not have a matching function, cannot synchronously test chips which do not synchronously respond, and cannot test by adopting ATE with the matching function due to the requirements of test environment, test productivity and test cost, so that some ATE cannot meet the functional test requirements.

Disclosure of Invention

Aiming at the defects of the prior art, the invention aims to provide a synchronous test method which can be applied to different types of ATE and is based on the internal clock of the chip to be tested for functional test.

The implementation of the method of the invention comprises two parts, ATE and a control program thereof, and a chip to be tested and a functional test program thereof.

The ATE and the control program thereof are used for sending a start test instruction, providing an external input low-speed clock, receiving a test response and controlling the whole test process.

The chip to be tested and the functional test program thereof are used for starting the test after receiving the test starting instruction, counting the externally input low-speed clock, and sending test response after counting the preset number.

A further improvement is that the ATE sends start test instructions and receives test replies, independent of the communication interface protocol. The start test instruction and the test response can be packaged into the form of communication protocol instructions by communicating through the I2C, SPI, UART or 7816 interface protocol of the chip. The jump of the input logic level of the digital port can be used as a start test, and the jump of the output logic level can be used as a test response output. The communication protocol which can be simulated by the ATE can be customized, and the start test instruction and the test response are packaged into the form of the customized communication protocol instruction.

A further improvement is that the timing/counting function is contained within the chip product and can operate independently of the other functions. The method can be used for realizing the function test of synchronizing the internal clock of the chip.

A further improvement is that the method can be implemented on most ATE at present, and is not limited by the presence or absence of a 'matching' function. The ATE can realize the function test of synchronizing the internal clock of the chip by using the method disclosed by the invention by only providing an external input clock.

The method is further improved in that the number of counts of the counting part in the chip function test program to be tested is estimated according to the test time required by the slowest clock conforming to the chip clock specification. The test time is estimated by adding a certain margin to the simulation time of the functional test COS after the clock frequency is regulated to the lower limit of the chip clock specification in the simulation environment. Since the chip clock calibration is always performed before the functional test, adding a certain time margin is used for eliminating the inconsistency between the actual chip operation and the simulation environment, and the functional test failure caused by that the internal clock frequency of the chip does not meet the internal clock specification requirement of the chip does not occur.

The method of the invention comprises the following steps:

1. the ATE sends a start test instruction to each chip to be tested;

2. the ATE stops sending test instructions. The ATE switches the input clock into a low-speed clock and is used for adapting to the upper limit of the count value of the internal timing/counter of different integrated circuit chip products, so that the situation that the count value overflows to cause the asynchronous count because of different upper limits of the internal timing/counter of different integrated circuit chip products is prevented, and the method cannot be applied is avoided.

3. After receiving a start test instruction sent by the ATE, the chip immediately starts to use the internal clock to perform functional test, and counts the external clock input by the ATE on the clock port. The internal functional test is performed at the same time as the clock count.

4. According to simulation of the simulation environment on the test COS time in advance, meanwhile, according to the upper limit of the count of the internal clock, the count number of the low-speed clock input by the ATE is set in the test COS, the count number of the external clock input by the ATE is consistent with the count number set in the test COS, and according to the pre-estimation, after the chip of the slowest clock conforming to the chip clock specification has finished the test, the internal clock/counter of the chip counts the number of the external clock input by the ATE.

5. The ATE switches back to the receiving response state and synchronously receives the test response sent by the chip. And judging whether each chip tests pass or fail according to the response.

Drawings

FIG. 1 is a schematic flow chart of the present invention;

Fig. 2 is a functional schematic of the present invention. The left side is ATE equipment, and the right side is a plurality of circuits to be tested in parallel. The ATE equipment and the plurality of circuits under test communicate in parallel through the communication port and the clock port.

Detailed Description

The present invention will be further described in detail with reference to the following examples, which are only for the purpose of illustrating the invention and are not to be construed as limiting the scope of the invention.

The functional diagram of the implementation is shown in FIG. 2, and includes ATE and a chip under test. The ATE and the chip to be tested are connected with a clock port and a communication port of the ATE and the chip to be tested through a test cable. The ATE control program is communicated with the function test program and the counting program of the chip to be tested through a clock port and a communication port which are connected through a test cable.

The implementation flow diagram is shown in fig. 1, and the implementation steps are as follows:

1. After the chips are electrified, the ATE control program sends a test starting instruction to each chip through the communication interface, and each chip does not need to send a response after receiving the test starting instruction.

2. After the ATE issues the start test instruction, communication is stopped. The clock input at this time is not used as a communication clock but is used as an external input for the internal timing/counter count of the chip. Before switching to the low speed clock, the low level should be maintained for 1 low speed clock cycle time, ensuring that the chip internal communication has terminated and the functional test has started.

3. After each chip receives the start test instruction, stopping the communication process of receiving the start test instruction. And after the function test is finished, the internal function test program inquires the count value of the timer/counter and compares the count value with the set count value.

4. And when the count value of the timer/counter is inquired and is the same as the preset count value, the communication mode is restored, and the test response is output. If the communication mode needs to respond in advance, the response of the communication mode is executed, and after the ATE and the chip to be tested are confirmed to start communication, a test response is output.

5. After the set number of external clocks is input, the communication mode is switched to, and the test response is immediately started to be received. If the communication mode needs to respond in advance, the response of the communication mode is executed, and after the ATE and the chip to be tested are confirmed to start communication, the test response is received. After receiving the test response, ATE determines the function test pass or fail for the response information.

Claims

1. A method for synchronously testing chip function on ATE can synchronously test the chip with asynchronous test completion time and test response time, and is characterized in that the communication is carried out through I2C, SPI, UART or 7816 interface protocol of the chip, and the start test instruction and the test response are packaged into a communication protocol instruction form; or taking the jump of the input logic level of the digital port as a start test and outputting the jump of the output logic level as a test response; or the self-defined ATE can simulate a communication protocol, and the start test instruction and the test response are packaged into a self-defined communication protocol instruction form; the method comprises the following steps:

The method comprises the steps that communication connection is established between ATE and chips to be tested, the ATE sends a start test instruction to each chip to be tested, and after the chips to be tested receive the start test instruction, each chip to be tested starts to be tested by using an internal clock respectively, and the start test instruction does not need to be responded;

the method comprises the steps that ATE stops sending instructions, the ATE switches an instruction operation clock input from a clock port of a chip to be tested into an external low-frequency clock, and when the chip to be tested is tested, the number of the external low-frequency clocks needs to be counted by using an internal timer/counter of the chip to be tested;

the chip to be tested tests by using an internal clock, counts the number of external low-frequency clocks input on a clock port, and tests the internal of the chip to be tested and counts the external input low-frequency clocks simultaneously with the internal timing/counter of the chip to be tested;

Inputting a certain number of external low-frequency clocks from a clock port of a chip to be tested according to the requirement of test time by ATE, wherein the number of the external low-frequency clocks is multiplied by the period of the external input low-frequency clock, and the obtained total time length is matched with the time length used for testing the chip;

and switching the external input clock back to the instruction operation clock by the ATE, reestablishing communication connection between the ATE and the chips to be tested, receiving the response of each chip to be tested by the ATE, completing synchronous test, and reestablishing communication connection between the ATE and the chips to be tested after the internal timing/counter of the chips to be tested counts the number of the external input low-frequency clock, and simultaneously sending the response by all the chips to be tested.