CA1159104A - Programmable power line interrupter - Google Patents
Programmable power line interrupterInfo
- Publication number
- CA1159104A CA1159104A CA000372911A CA372911A CA1159104A CA 1159104 A CA1159104 A CA 1159104A CA 000372911 A CA000372911 A CA 000372911A CA 372911 A CA372911 A CA 372911A CA 1159104 A CA1159104 A CA 1159104A
- Authority
- CA
- Canada
- Prior art keywords
- clock
- interrupter
- power line
- control signal
- flip flop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H47/00—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current
- H01H47/02—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current for modifying the operation of the relay
- H01H47/18—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current for modifying the operation of the relay for introducing delay in the operation of the relay
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/316—Testing of analog circuits
- G01R31/3161—Marginal testing
-
- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F1/00—Apparatus which can be set and started to measure-off predetermined or adjustably-fixed time intervals without driving mechanisms, e.g. egg timers
- G04F1/005—Apparatus which can be set and started to measure-off predetermined or adjustably-fixed time intervals without driving mechanisms, e.g. egg timers using electronic timing, e.g. counting means
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Measurement Of Unknown Time Intervals (AREA)
Abstract
Case 2763 PROGRAMMABLE POWER LINE INTERRUPTER
ABSTRACT OF THE DISCLOSURE
There is disclosed a programmable power line interrupter for interrupting the flow of electrical current on a power line for a predetermined time duration. The interrupter is adaptable for use with a 120 volt 60 hertz power line and includes a solid state relay which interrupts the flow of power to a device. The interrupter further includes a programmable counter which can be programmed to cause the solid state relay to interrupt power to the device for a predetermined time duration. A visual display is also provided which provides a visual indication of the amount of time elapsed during the power interruption. The novel interrupter is a useful device for testing electronic equipment as well as other equipment to see if this equipment will continue to operate after discrete timed power outages.
ABSTRACT OF THE DISCLOSURE
There is disclosed a programmable power line interrupter for interrupting the flow of electrical current on a power line for a predetermined time duration. The interrupter is adaptable for use with a 120 volt 60 hertz power line and includes a solid state relay which interrupts the flow of power to a device. The interrupter further includes a programmable counter which can be programmed to cause the solid state relay to interrupt power to the device for a predetermined time duration. A visual display is also provided which provides a visual indication of the amount of time elapsed during the power interruption. The novel interrupter is a useful device for testing electronic equipment as well as other equipment to see if this equipment will continue to operate after discrete timed power outages.
Description
~5~0~
- l - Case 2763 PROGRAMMABLE POWER LINE INTERRUPTER
The present invention relates to a power line interrupter. In particular, it relates to a programmable power line interrupter suitable for use in testing the operation of electrical equipment after the occurrence of a discrete timed power outage.
Power failures and power outages are frequently experienced in local plant or office facilities. A power failure or a power outage has a considerable adverse effect on the operation of electrical equipment, electronic equipment, and computers. The ability of the equipment to continue to operate after a power outage is a major consideration of a customer when the customer is considering the reliability of the equipment. In view of this, manufacturers have been specifying the time interval of a power outage after which their electrical equipment, electronic equipment, and computers should continue to operate. The specifications provided by the manufacturers regarding the time interval of a power outage after which the manufacturers expect their equipment to continue to function, are usually determined in the laboratories of the manufacturers by employing elaborate equipment. Experience has shown, however, that assembly line manufactured equipment does not always continue to operate after the occurrence of ,,~
q~
~591()4 Case 2763 a power outage whose duration is less than or equal to the manufacturer's specified time interval.
Further, the customer has no way of knowing whether or not the equipment will meet the specifications given by the manufacturer. Therefore, there is a need for inexpensive testing equipment that can be readily used either by the manufacturer or the customer to test electrical equipment to see if the equipment will continue to operate after a power outage of a predetermined timed interval which interval may or may not be specified by the manufacturer.
Therefore, it is a feature of the present invention to provide a programmable power line interrupter that creates a power outage of predetermined timed duration on a power line so as to test the operability of electrical devices connected to the power line.
Briefly, the present invention provides a programmable power line interrupter that interrupts the flow of electrical current on a power line for a predetermined timed duration. The interrupter includes a clock means, starting means, synchronous means, programmable counting means, and switching means. The synchronous means provides a control signal in response to the generation of a start signal from the starting means and the presence of a clock pulse from the clock means. The programmable counting means counts the number of clock pulses that are generated by the clock means once a control signal has been generated by the synchronous means.
The switching means interrupts the flow of electrical current on the power line once the control signal has been generated. Thus, once the programmable power line interrupter is started, the synchronous means coordinates the start signal and the clock pulses ~159104 Case 2763 from the clock means to commence the programmable counting means and has the switching means interrupt the flow of electrical current on the power line.
The programmable counting means is programmed to generate a reset signal once the count reaches a predetermined number. Once the reset signal is generated, the switching means again permits the flow of electrical current on the power line. By choosing the clock pulses of a predetermined frequency and duration, the programmable counting means can be programmed to count a predetermined number of clock pulses and thereby cause the switching means to interrupt the flow of electrical current on the power line for a predetermined timed duration. An electrical device may be connected in circuit with the power line so as to determine readily whether or not the device will continue to operate.
Further, the clock means may have an input connected to an AC power supply such that the programmable power line interrupter may comprise a hand-held device that can be plugged into an outlet or a source of power and be connected in circuit with an electrical device to be tested.
Additionally, the interrupter may further comprise a gate means which provides an output signal representative of the clock pulses to the programmable counting means only when the control signal and the clock signals are each present at a respective input of the gate means.
The interrupter may still further comprise a visual display means and additional counting means.
The additional counting means has its count displayed by the display means. The additional counting means will begin a count of the number of clock pulses generated by the clock means once the control signal ~ iS~10~
Case 2763 has been generated. Further, the additional counting means will cease its count upon the generation of the reset signal from the programmable counting means.
In accordance with one aspect of the present invention, there is provided a programmable power line interrupter for interrup~ing the flow of electrical current on a power line for a predetermined timed duration, the interrupter comprising: clock means for generating a series of clock pulses of a predetermined frequency and time duration; starting means for generating a start signal; synchronous means in response to the generation of the start signal and one of the clock pulses providing a control signal; programmable counting means which, upon generation of the control signal, commences a count of the number of clock pulses generated by the clock means, and the counting means generating a reset signal when the count reaches a predetermined number; and, switching means for controlling the flow of electrical current on the power line, the switching means being responsive to generation of the control signal to interrupt the flow of electrical current on the power line and being responsive to the generation of the reset signal to permit the flow of electrical current on the power line.
For a better understanding of the nature and objects of the present invention, reference may be had, by way of example, to the accompanying diagramatic drawings in which:
Figure 1 is a schematic representation of the programmable power line interrupter of the present invention;
~L59104 Case 2763 Figure 2 is a detailed circuit drawing of the clock means;
Figure 3 is a detailed circuit drawing of the starting means; and, Figure 4 is a detailed circuit drawing of the synchronous means.
Referring to Figure 1, there is shown a programmable power line interrupter 10 having a clock means or clock 12, a starting means or starter 14, a synchronizing means or synchronizer 16, a gate means or gate 18, a switching means or switch 20, a programmable counting means or programmable counter 22, a visual display means and additional counting means or visual display and counter 24, and a reset 26.
The switch 20 is provided with outputs 28 and 30, which are connected to an AC power line.
It should be understood that connected to this power line is the electrical device (not shown) that is to be tested by switch 20 interrupting the supply of electrical power to the device for a predetermined period of time to determine whether or not the device will continue to operate once switch 20 resumes the supply of power to the device. The switch 20 may comprise a solid state relay having a power rating commensurate with the AC power line rating. The switch 20 is provided with an input 32 along which a control signal is transmitted from synchronizer 16.
Synchronizer 16 outputs a control signal at output 34 which signal is transmitted to gate 18 and to switch 20. Synchronizer 16 generates the control signal in response to a start signal being present from starter 14 on synchronizer input 36 and clock pulse from clockl2 being present on synchronizer input 38.
~L59~()4 Case 2763 Clock 12 generates a continuous train of clock pulses when operating. 'rhe clock pulses are of a predetermined frequency and time duration.
The clock pulses, besides being transmitted to synchronizer 16, are also transmitted along line 40 to gate 18.
Gate 18 operates in such fashion that only upon the presence of both the control signal at its input 35 and the clock signal on line or gate input 40 does it permit an output on line 42. The output on line 42 comprises clock pulses representative of the clock pulses present on line 40. The clock pulses provided on line 42 are transmitted to visual display and counter 24 and programmable counter 22 along lines 42a and 42b, respectively.
The programmable counter 22 and the counter of the visual display and counter 24 each count the number of clock pulses that occur after the generation of the control signal by synchronizer 16 on line 34. The programmable counter 22 is programmed to generate a reset signal once the count reaches a predetermined number. The reset signal is transmitted along line 44 to synchronizer 16 so as to inhibit the generation of the control signal by synchronizer 16.
Once generation of the control signal is inhibited, gate 18 inhibits the transmission of the clock pulses along line 42 and thus counters 22 and 24 cease their respective counts. At this time, the visual display of the visual display and counter 24 reads the count contained in its counter to provide visual verification to the operator of the time elapsed for the power outage. Also, when generation of the control sigr.al is inhibited, the control signal is no longer present at input 32 of switch 20. This permits the switch 20 to reclose resuming the flow of electrical power on AC
P~59~04 Case 2763 power lines 28 and 30. The frequency and time duration of the clock pulses may be chosen such that the prede~ermined number of counts counted by programmable counter 22 represents the desired time duration for which the power outage is to last.
The programmable power line interrupter 10 is further provided with the reset 26 which is a switch that can be manually operated to clear the count in both the programmable counter 22 and in the visual display and counter 24. ~lthough the reset clears the count in these counters, it should be understood that it does not change the predetermined count number programmed into counter 22. The count programmed in counter 22 may be changed by a suitable means such as, for example, providing programmable counter 22 with thumbwheel switches.
Referring now to Figure 2. The clock 12 of the present invention is shown in more detail.
The clock 12 is shown to comprise a transformer 46 having its primary winding 4~ having its power line inputs adapted for connection across a power supply.
The secondary winding 48 of the transformer 46 is provided with a first branch circuit 50 and a second branch circuit 52 in parallel with the first branch citcuit 50. The first branch circuit 50 is provided with a capacitor 54, resistor 56, a second capacitor 58, and resistors 60 and 62, arranged substantially as shown in the drawing. This circuitry is provided as shown to ensure the proper operation of the pulse shaper 64 which comprises a Schmitt trigger. Thus, the output of the pulse shaper 64 is a squared pulse having a frequency of 60 hertz, the power supply frequency, and a reduced voltage magnitude proportional to the secondary voltage of the transformer 46.
The output of the pulse shaper 64 is transmitted ~159~09~
Case 2763 to a frequency divider 66 which divides the frequency of the pulses in such a fashion so that a pulse is provided once every 0.1 seconds and a train of clock pulses is outputed on line 38 to synchronizer 16.
S The second branch circuit 52 includes a diode 68, capacitor 70, a voltage regu]ator 72, and a capacitor 74 arranged substantially as shown which together provide for a direct current high level voltage supply to the electrical elements of the programmable power line interrupter at line 76.
Referring to Figure 3, the starter 14 is shown in more detail. Starter 14 comprises a pushbutton 78 which is manually operated to close switch 80. Once switch 80 is closed, capacitor 82 discharges to ground and a resistor 84 is also provided to complete the circuitry. The discharged pulse provided by capacitor 82 is shaped by pulse shaper 86 which comprises a Schmitt trigger. The output of the starter 14 is a pulse which is outputed on line 36 to synchronizer 16.
Although figure 1 shows line 32 connecting up with line 34, it should be understood that in this one preferred embodiment the control signal transmitted to the gate 18 and switch 20 is one in the same.
However, in another preferred embodiment, lines 32 and 34 are outputed separately from synchronizer 16 such that the control signal is transmitted on line 32 to switch 20 and a complementary version of the control signal is transmitted along line 34 to gate 18.
This latter preferred embodiment is the one shown in Figure 4.
Referring to Figure 4, synchronizer 16 is shown in more detail. Synchronizer 16 is shown to comprise a first D-type flip flop 90, a second D-type flip flop 92, a third D-type flip flop 94, ~L5~104 Case 2763 g and a fourth D-type flip flop 96. Within each of the flip flops 90 through 96, only the inputs which are used have their designations shown. The D designation represents the input value, the CLK
represents the clock, the S represents the set, the R represents the reset, and the Q represents the output and the Q represents the complementary output. The starter signal is fed via line 36 into the clock of the first flip flop 90. The output of the first flip flop 90 is input into the input of the second flip flop 92. In this manner, the first flip flop 90 once clocked by the starting pulse will hold the output high until it is reset. The high output of flip flop 90 is fed into the D-input of flip flop 92. The output of flip flop 92 is fed back into the reset of flip flop 90 and also the clock of flip flop 94. The clock of flip flop 92 is connected to clock 12 via line 38. In this manner, the output of flip flop 92 is provided when both the starting signal is present and a clock pulse is present.
It should also be noted that the reset of flip flop 90 is connected to the output of flip flop 92 so that once flip flop 92 outputs a high logic level this high logic level resets flip flop 90 to have its output 0 which resets the flip flop 92 on the next clock pulse. By this time, however, the output of clock 92 has clocked flip flop 94 which has its D
input connected to a high logic level. Thus, there will be an output present on the output of flip flop 94.
The output of flip flop 94 is transmitted to the input of flip flop 96 and to line 32 of switch 20. As previously noted, in this preferred embodiment the control signal has two versions, its normal version and its complementary version. The output to line 32 is the normal version. The output to gate 18, which ~1591()~
Case 2763 would be similar to line 35, is the complementary version. This is because D-flip flop 96 takes the control signal and inverts it upon reception of a clock pulse at its input. As shown in these figures, flip flops 94 and 96 also have their reset buttons connected to the programmable counter along line 44.
This is to complement or invert the outputs of each of flip flops 94 and 96 upon the completion of a count by the programmable counter. Once the outputs of flip flops 94 and 96 are complemented, the control signal (both versions) acts to inhibit the gate 18 from permitting a signal representative of the clock pulses therethrough and closes the switch 20 providing a flow of AC power through lines 28 and 30.
It should be further understood that alternate embodiments of the present invention may be readily apparent to a man skilled in the art in view of the foregoing description of the invention.
Accordingly, the invention should be limited only to that which is claimed in the accompanying claims.
- l - Case 2763 PROGRAMMABLE POWER LINE INTERRUPTER
The present invention relates to a power line interrupter. In particular, it relates to a programmable power line interrupter suitable for use in testing the operation of electrical equipment after the occurrence of a discrete timed power outage.
Power failures and power outages are frequently experienced in local plant or office facilities. A power failure or a power outage has a considerable adverse effect on the operation of electrical equipment, electronic equipment, and computers. The ability of the equipment to continue to operate after a power outage is a major consideration of a customer when the customer is considering the reliability of the equipment. In view of this, manufacturers have been specifying the time interval of a power outage after which their electrical equipment, electronic equipment, and computers should continue to operate. The specifications provided by the manufacturers regarding the time interval of a power outage after which the manufacturers expect their equipment to continue to function, are usually determined in the laboratories of the manufacturers by employing elaborate equipment. Experience has shown, however, that assembly line manufactured equipment does not always continue to operate after the occurrence of ,,~
q~
~591()4 Case 2763 a power outage whose duration is less than or equal to the manufacturer's specified time interval.
Further, the customer has no way of knowing whether or not the equipment will meet the specifications given by the manufacturer. Therefore, there is a need for inexpensive testing equipment that can be readily used either by the manufacturer or the customer to test electrical equipment to see if the equipment will continue to operate after a power outage of a predetermined timed interval which interval may or may not be specified by the manufacturer.
Therefore, it is a feature of the present invention to provide a programmable power line interrupter that creates a power outage of predetermined timed duration on a power line so as to test the operability of electrical devices connected to the power line.
Briefly, the present invention provides a programmable power line interrupter that interrupts the flow of electrical current on a power line for a predetermined timed duration. The interrupter includes a clock means, starting means, synchronous means, programmable counting means, and switching means. The synchronous means provides a control signal in response to the generation of a start signal from the starting means and the presence of a clock pulse from the clock means. The programmable counting means counts the number of clock pulses that are generated by the clock means once a control signal has been generated by the synchronous means.
The switching means interrupts the flow of electrical current on the power line once the control signal has been generated. Thus, once the programmable power line interrupter is started, the synchronous means coordinates the start signal and the clock pulses ~159104 Case 2763 from the clock means to commence the programmable counting means and has the switching means interrupt the flow of electrical current on the power line.
The programmable counting means is programmed to generate a reset signal once the count reaches a predetermined number. Once the reset signal is generated, the switching means again permits the flow of electrical current on the power line. By choosing the clock pulses of a predetermined frequency and duration, the programmable counting means can be programmed to count a predetermined number of clock pulses and thereby cause the switching means to interrupt the flow of electrical current on the power line for a predetermined timed duration. An electrical device may be connected in circuit with the power line so as to determine readily whether or not the device will continue to operate.
Further, the clock means may have an input connected to an AC power supply such that the programmable power line interrupter may comprise a hand-held device that can be plugged into an outlet or a source of power and be connected in circuit with an electrical device to be tested.
Additionally, the interrupter may further comprise a gate means which provides an output signal representative of the clock pulses to the programmable counting means only when the control signal and the clock signals are each present at a respective input of the gate means.
The interrupter may still further comprise a visual display means and additional counting means.
The additional counting means has its count displayed by the display means. The additional counting means will begin a count of the number of clock pulses generated by the clock means once the control signal ~ iS~10~
Case 2763 has been generated. Further, the additional counting means will cease its count upon the generation of the reset signal from the programmable counting means.
In accordance with one aspect of the present invention, there is provided a programmable power line interrupter for interrup~ing the flow of electrical current on a power line for a predetermined timed duration, the interrupter comprising: clock means for generating a series of clock pulses of a predetermined frequency and time duration; starting means for generating a start signal; synchronous means in response to the generation of the start signal and one of the clock pulses providing a control signal; programmable counting means which, upon generation of the control signal, commences a count of the number of clock pulses generated by the clock means, and the counting means generating a reset signal when the count reaches a predetermined number; and, switching means for controlling the flow of electrical current on the power line, the switching means being responsive to generation of the control signal to interrupt the flow of electrical current on the power line and being responsive to the generation of the reset signal to permit the flow of electrical current on the power line.
For a better understanding of the nature and objects of the present invention, reference may be had, by way of example, to the accompanying diagramatic drawings in which:
Figure 1 is a schematic representation of the programmable power line interrupter of the present invention;
~L59104 Case 2763 Figure 2 is a detailed circuit drawing of the clock means;
Figure 3 is a detailed circuit drawing of the starting means; and, Figure 4 is a detailed circuit drawing of the synchronous means.
Referring to Figure 1, there is shown a programmable power line interrupter 10 having a clock means or clock 12, a starting means or starter 14, a synchronizing means or synchronizer 16, a gate means or gate 18, a switching means or switch 20, a programmable counting means or programmable counter 22, a visual display means and additional counting means or visual display and counter 24, and a reset 26.
The switch 20 is provided with outputs 28 and 30, which are connected to an AC power line.
It should be understood that connected to this power line is the electrical device (not shown) that is to be tested by switch 20 interrupting the supply of electrical power to the device for a predetermined period of time to determine whether or not the device will continue to operate once switch 20 resumes the supply of power to the device. The switch 20 may comprise a solid state relay having a power rating commensurate with the AC power line rating. The switch 20 is provided with an input 32 along which a control signal is transmitted from synchronizer 16.
Synchronizer 16 outputs a control signal at output 34 which signal is transmitted to gate 18 and to switch 20. Synchronizer 16 generates the control signal in response to a start signal being present from starter 14 on synchronizer input 36 and clock pulse from clockl2 being present on synchronizer input 38.
~L59~()4 Case 2763 Clock 12 generates a continuous train of clock pulses when operating. 'rhe clock pulses are of a predetermined frequency and time duration.
The clock pulses, besides being transmitted to synchronizer 16, are also transmitted along line 40 to gate 18.
Gate 18 operates in such fashion that only upon the presence of both the control signal at its input 35 and the clock signal on line or gate input 40 does it permit an output on line 42. The output on line 42 comprises clock pulses representative of the clock pulses present on line 40. The clock pulses provided on line 42 are transmitted to visual display and counter 24 and programmable counter 22 along lines 42a and 42b, respectively.
The programmable counter 22 and the counter of the visual display and counter 24 each count the number of clock pulses that occur after the generation of the control signal by synchronizer 16 on line 34. The programmable counter 22 is programmed to generate a reset signal once the count reaches a predetermined number. The reset signal is transmitted along line 44 to synchronizer 16 so as to inhibit the generation of the control signal by synchronizer 16.
Once generation of the control signal is inhibited, gate 18 inhibits the transmission of the clock pulses along line 42 and thus counters 22 and 24 cease their respective counts. At this time, the visual display of the visual display and counter 24 reads the count contained in its counter to provide visual verification to the operator of the time elapsed for the power outage. Also, when generation of the control sigr.al is inhibited, the control signal is no longer present at input 32 of switch 20. This permits the switch 20 to reclose resuming the flow of electrical power on AC
P~59~04 Case 2763 power lines 28 and 30. The frequency and time duration of the clock pulses may be chosen such that the prede~ermined number of counts counted by programmable counter 22 represents the desired time duration for which the power outage is to last.
The programmable power line interrupter 10 is further provided with the reset 26 which is a switch that can be manually operated to clear the count in both the programmable counter 22 and in the visual display and counter 24. ~lthough the reset clears the count in these counters, it should be understood that it does not change the predetermined count number programmed into counter 22. The count programmed in counter 22 may be changed by a suitable means such as, for example, providing programmable counter 22 with thumbwheel switches.
Referring now to Figure 2. The clock 12 of the present invention is shown in more detail.
The clock 12 is shown to comprise a transformer 46 having its primary winding 4~ having its power line inputs adapted for connection across a power supply.
The secondary winding 48 of the transformer 46 is provided with a first branch circuit 50 and a second branch circuit 52 in parallel with the first branch citcuit 50. The first branch circuit 50 is provided with a capacitor 54, resistor 56, a second capacitor 58, and resistors 60 and 62, arranged substantially as shown in the drawing. This circuitry is provided as shown to ensure the proper operation of the pulse shaper 64 which comprises a Schmitt trigger. Thus, the output of the pulse shaper 64 is a squared pulse having a frequency of 60 hertz, the power supply frequency, and a reduced voltage magnitude proportional to the secondary voltage of the transformer 46.
The output of the pulse shaper 64 is transmitted ~159~09~
Case 2763 to a frequency divider 66 which divides the frequency of the pulses in such a fashion so that a pulse is provided once every 0.1 seconds and a train of clock pulses is outputed on line 38 to synchronizer 16.
S The second branch circuit 52 includes a diode 68, capacitor 70, a voltage regu]ator 72, and a capacitor 74 arranged substantially as shown which together provide for a direct current high level voltage supply to the electrical elements of the programmable power line interrupter at line 76.
Referring to Figure 3, the starter 14 is shown in more detail. Starter 14 comprises a pushbutton 78 which is manually operated to close switch 80. Once switch 80 is closed, capacitor 82 discharges to ground and a resistor 84 is also provided to complete the circuitry. The discharged pulse provided by capacitor 82 is shaped by pulse shaper 86 which comprises a Schmitt trigger. The output of the starter 14 is a pulse which is outputed on line 36 to synchronizer 16.
Although figure 1 shows line 32 connecting up with line 34, it should be understood that in this one preferred embodiment the control signal transmitted to the gate 18 and switch 20 is one in the same.
However, in another preferred embodiment, lines 32 and 34 are outputed separately from synchronizer 16 such that the control signal is transmitted on line 32 to switch 20 and a complementary version of the control signal is transmitted along line 34 to gate 18.
This latter preferred embodiment is the one shown in Figure 4.
Referring to Figure 4, synchronizer 16 is shown in more detail. Synchronizer 16 is shown to comprise a first D-type flip flop 90, a second D-type flip flop 92, a third D-type flip flop 94, ~L5~104 Case 2763 g and a fourth D-type flip flop 96. Within each of the flip flops 90 through 96, only the inputs which are used have their designations shown. The D designation represents the input value, the CLK
represents the clock, the S represents the set, the R represents the reset, and the Q represents the output and the Q represents the complementary output. The starter signal is fed via line 36 into the clock of the first flip flop 90. The output of the first flip flop 90 is input into the input of the second flip flop 92. In this manner, the first flip flop 90 once clocked by the starting pulse will hold the output high until it is reset. The high output of flip flop 90 is fed into the D-input of flip flop 92. The output of flip flop 92 is fed back into the reset of flip flop 90 and also the clock of flip flop 94. The clock of flip flop 92 is connected to clock 12 via line 38. In this manner, the output of flip flop 92 is provided when both the starting signal is present and a clock pulse is present.
It should also be noted that the reset of flip flop 90 is connected to the output of flip flop 92 so that once flip flop 92 outputs a high logic level this high logic level resets flip flop 90 to have its output 0 which resets the flip flop 92 on the next clock pulse. By this time, however, the output of clock 92 has clocked flip flop 94 which has its D
input connected to a high logic level. Thus, there will be an output present on the output of flip flop 94.
The output of flip flop 94 is transmitted to the input of flip flop 96 and to line 32 of switch 20. As previously noted, in this preferred embodiment the control signal has two versions, its normal version and its complementary version. The output to line 32 is the normal version. The output to gate 18, which ~1591()~
Case 2763 would be similar to line 35, is the complementary version. This is because D-flip flop 96 takes the control signal and inverts it upon reception of a clock pulse at its input. As shown in these figures, flip flops 94 and 96 also have their reset buttons connected to the programmable counter along line 44.
This is to complement or invert the outputs of each of flip flops 94 and 96 upon the completion of a count by the programmable counter. Once the outputs of flip flops 94 and 96 are complemented, the control signal (both versions) acts to inhibit the gate 18 from permitting a signal representative of the clock pulses therethrough and closes the switch 20 providing a flow of AC power through lines 28 and 30.
It should be further understood that alternate embodiments of the present invention may be readily apparent to a man skilled in the art in view of the foregoing description of the invention.
Accordingly, the invention should be limited only to that which is claimed in the accompanying claims.
Claims (15)
1. A programmable power line interrupter for interrupting the flow of electrical current on a power line for a predetermined time duration, said interrupter comprising:
clock means for generating a series of clock pulses of a predetermined frequency and time duration;
starting means for generating a start signal;
synchronous means in response to the generation of said start signal and one of said clock pulses providing a control signal;
programmable counting means which upon generation of said control signal, commences a count of the number of said clock pulses generated by said clock means, and said counting means generating a reset signal when said count reaches a predetermined number; and, switching means for controlling said flow of electrical current on said power line, said switching means being responsive to generation of said control signal to interrupt the flow of electrical current on said power line and being responsive to the generation of said reset signal to permit the flow of electrical current on said power line.
clock means for generating a series of clock pulses of a predetermined frequency and time duration;
starting means for generating a start signal;
synchronous means in response to the generation of said start signal and one of said clock pulses providing a control signal;
programmable counting means which upon generation of said control signal, commences a count of the number of said clock pulses generated by said clock means, and said counting means generating a reset signal when said count reaches a predetermined number; and, switching means for controlling said flow of electrical current on said power line, said switching means being responsive to generation of said control signal to interrupt the flow of electrical current on said power line and being responsive to the generation of said reset signal to permit the flow of electrical current on said power line.
2. The interrupter of claim 1 further comprising gate means providing an output signal representative of the clock pulses to the programmable counting means only when said control signal and said clock signals are each present at a respective input of the gate means.
Case 2763
Case 2763
3. The interrupter of claim 1 wherein said synchronous means further provides said control signal in two versions, a complementary version and a normal version, said switching means being responsive to the normal version.
4. The interrupter of claim 3 further comprising gate means providing an output signal representative of the clock pulses to the programmable counting means only when said complementary version of the control signal and said clock signal are each present at a respective input of the gate means.
5. The interrupter of claim 1 further comprising a visual display means and additional counting means having its count displayed by the visual display means, the additional counting means upon generation of said control signal commencing a second count of the number of clock pulses generated by said clock means, and said additional counting means in response to said reset signal ceasing to count.
6. The interrupter of claim 2 further comprising a visual display means and additional counting means having its count outputed by the visual display means, the additional counting means being responsive to the output of the gate means to commence a second count of the number of clock pulses generated by the clock means upon generation of the control signal, and said additional clock means in response to generation of said reset signal ceasing to count.
7. The interrupter of claim 1, 2 or 6 wherein said reset signal is fed directly back to said synchronous means to inhibit generation of said control signal.
Case 2763
Case 2763
8. The interrupter of claim 3 wherein said synchronous means comprises first, second, third and fourth D-type flip flops, said first flip flop having its clock input connected to said starting means to receive said start signal, its D
input connected to a high logic level supply, and its output connected to the D input of the second flip flop, said second flip flop having its clock input connected to the clock means to receive said clock pulses and having its output connected to the reset input of the first flip flop and the clock input of the third flip flop, the third flip flop having its D input connected to the high logic level supply and its output to the D input of the fourth flip flop, the fourth flip flop having its clock input connected to the clock means to receive said clock signals and its complementary output connected to a gate means, said normal version of said control signal being provided at the output of the third flip flop and the complementary output of the fourth flip flop providing the complementary version of the control signal, and each of said third and fourth flip flops having its reset input connected to the programmable counting means to receive said reset signal therefrom.
input connected to a high logic level supply, and its output connected to the D input of the second flip flop, said second flip flop having its clock input connected to the clock means to receive said clock pulses and having its output connected to the reset input of the first flip flop and the clock input of the third flip flop, the third flip flop having its D input connected to the high logic level supply and its output to the D input of the fourth flip flop, the fourth flip flop having its clock input connected to the clock means to receive said clock signals and its complementary output connected to a gate means, said normal version of said control signal being provided at the output of the third flip flop and the complementary output of the fourth flip flop providing the complementary version of the control signal, and each of said third and fourth flip flops having its reset input connected to the programmable counting means to receive said reset signal therefrom.
9. The interrupter of claim 1 wherein said clock means includes a step down transformer and a pulse shaper, said transformer having a primary winding adapted for connection to an AC power supply and a secondary winding connected to the pulse shaper.
10. The interrupter of claim 9 wherein said power line is a 120 volt 60 hertz power line and said clock means further provides a frequency divider connected to the output of the pulse shaper so as to allow the clock means to provide a clock pulse ever 0.1 seconds.
Case 2763
Case 2763
11. The interrupter of claim 9 wherein said clock means further includes a voltage converter system connected to the secondary winding in parallel with the pulse shaper to provide a direct current high logic level supply for electronic circuitry of the interrupter.
12. The interrupter of claim 1 wherein said starting means includes a manually operated switch.
13. The interrupter of claim 1 further including a reset switch which clears the count in the programmable counting means.
14. The interrupter of claim 5 further including a reset switch which clears the count in the programmable counting means and the additional counting means.
15. The interrupter of claim 1 wherein said switching means comprises a solid state relay.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000372911A CA1159104A (en) | 1981-03-12 | 1981-03-12 | Programmable power line interrupter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000372911A CA1159104A (en) | 1981-03-12 | 1981-03-12 | Programmable power line interrupter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1159104A true CA1159104A (en) | 1983-12-20 |
Family
ID=4119440
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000372911A Expired CA1159104A (en) | 1981-03-12 | 1981-03-12 | Programmable power line interrupter |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1159104A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112130053A (en) * | 2020-08-11 | 2020-12-25 | 上海华虹集成电路有限责任公司 | Method for performing chip function synchronous test on ATE |
-
1981
- 1981-03-12 CA CA000372911A patent/CA1159104A/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112130053A (en) * | 2020-08-11 | 2020-12-25 | 上海华虹集成电路有限责任公司 | Method for performing chip function synchronous test on ATE |
| CN112130053B (en) * | 2020-08-11 | 2024-05-14 | 上海华虹集成电路有限责任公司 | Method for synchronously testing chip functions on ATE |
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