CN113985248B - High-temperature dynamic aging system and method for PCIe (peripheral component interconnect express) switching circuit - Google Patents
High-temperature dynamic aging system and method for PCIe (peripheral component interconnect express) switching circuit Download PDFInfo
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- CN113985248B CN113985248B CN202111250961.4A CN202111250961A CN113985248B CN 113985248 B CN113985248 B CN 113985248B CN 202111250961 A CN202111250961 A CN 202111250961A CN 113985248 B CN113985248 B CN 113985248B
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Abstract
The invention discloses a high-temperature dynamic aging system and method for PCIe (peripheral component interconnect express) switching circuits, belonging to the field of integrated circuit design and test. The system functionally maximized covers the functions of a physical layer, a controller and transaction routing exchange of the circuit, so that each port of the circuit performs transaction transmission and reception during aging, and dynamic aging is performed according to the normal working frequency and bus interface rate of the PCIe exchange circuit; according to the invention, each aging circuit is not required to be externally connected with PCIe root complex equipment and a plurality of PCIe endpoint equipment, so that aging can be performed according to the working frequency of the circuit and the bus interface speed, and the use cost of components on an aging board is greatly saved; meanwhile, the peripheral PCIe equipment on the aging board is reduced, so that more stations are realized on the aging single board, more circuits can be aged in the same aging high-temperature box, and the test cost is saved.
Description
Technical Field
The invention belongs to the field of integrated circuit design and test, and relates to a high-temperature dynamic aging system and method of a PCIe (peripheral component interconnect express) switching circuit.
Background
The integrated circuit with high reliability and high quality level can screen or reject barely qualified devices through burn-in test in the production process, so as to ensure the reliability of the outgoing circuit. These devices either have inherent defects themselves or are improperly manufactured by the process controller, which can cause time and stress dependent failures. If no burn-in test is performed, these defective devices may experience incipient catastrophic or early life failure when in use. Dynamic burn-in tests require that the test circuit apply appropriate excitation and output loads so that the circuit is as close as practical to practical use, burn-in at practical operating frequencies and interface rates.
In a PCIe system, PCIe switching circuitry is used to interconnect and communicate a plurality of electronic components or modules. PCIe switching circuits generally have two or more PCIe ports, any one of which may be configured as a Root Complex (RC) for an Upstream Port, and the remaining ports may be configured as Downstream Port connection Endpoint (Endpoint) devices, and two Downstream ports of the same circuit may not be able to connect and communicate. FIG. 1 is a schematic diagram of a typical application of a PCIe switched circuit having N ports. Because of the stringent electrical characteristics requirements, complex functions, and excessive signal count of PCIe, existing burn-in boxes are unable to provide burn-in excitation signals that can meet PCIe switching circuits. In order to dynamically burn-in the N-port switching circuit shown in fig. 1 at the actual operating frequency and interface rate, it is necessary to provide a root complex device connected to the upstream ports to provide burn-in excitation and output loads and N-1 endpoint devices connected to all downstream ports to provide burn-in excitation and output loads. However, the need for n×m peripheral PCIe devices as stimulus and load in mass production of the circuits brings high hardware costs, and makes the burn-in circuit stations available on the burn-in printed board extremely limited, bringing high and even unacceptable test costs.
Disclosure of Invention
The invention aims to overcome the defects of higher hardware cost and test cost caused by the fact that more peripheral PCIe devices are required to be used as excitation and load for aging of a plurality of circuits in the prior art, and provides a high-temperature dynamic aging system and method of PCIe switching circuits.
In order to achieve the above purpose, the invention is realized by adopting the following technical scheme:
a high-temperature dynamic aging system of PCIe switching circuit comprises an aging port, an internal processing module, an aging enable pin and a transaction processing output pin;
a burn-in port, including a burn-in upstream port and a burn-in downstream port, for receiving, routing, or discarding configuration transactions for a particular ID and memory transactions for a particular address range;
the internal processing module is interacted with the aging port and is used for detecting the transaction receiving state of each port in the circuit, forming a unified transaction processing signal and outputting the unified transaction processing signal to a transaction processing output pin; simultaneously, the received aging transaction is routed to an aging upstream port or an aging downstream port;
the aging enabling pin is respectively interacted with the internal processing module and the aging port and is used for enabling an aging mode of the PCIe switching circuit;
the transaction processing output pin is interacted with the internal processing module and is used for judging whether the circuit is normal or not in the aging period of the circuit;
when the number of PCIe ports in the circuit is odd, the system further includes a last port upstream enable pin for connecting with a particular burn-in port and configuring the particular burn-in port as either a burn-in upstream port or a burn-in downstream port.
Preferably, the structure of the aging upstream port or the aging downstream port is the same;
the burn-in upstream port and the burn-in downstream port are connected to the burn-in downstream port and the burn-in upstream port of the same or different burn-in circuits, respectively, by PCB tracks.
Preferably, when the number of PCIe ports in the circuit is even, half of the ports are fixedly configured as burn-in upstream ports and half of the ports are fixedly configured as burn-in downstream ports;
when the number of PCIe ports in the circuit is odd, the circuit further comprises a specific burn-in port connected with an upstream enabling pin of the last port, and half ports in the rest ports are fixedly configured as burn-in upstream ports, and the other half ports are fixedly configured as burn-in downstream ports except for the specific burn-in port.
Preferably, the aging port comprises a physical layer module, a controller module, an aging transaction sending module, an outlet virtual receiving module and an aging transaction receiving module;
the physical layer module is interacted with the controller module and is used for realizing PCIe protocol physical layer functions;
the controller module is respectively interacted with the internal processing module and the aging transaction sending module and is used for acquiring a data link layer of the PCIe protocol and controlling the sending of the aging transaction;
the aging transaction sending module is interacted with the controller module and is used for periodically sending aging transactions to an opposite end downstream port or an opposite end upstream port connected with the port through the controller module and the physical layer module after the link training is finished and the link is established;
the output end virtual receiving module is interacted with the internal processing module and is used for executing the virtual receiving function of the aging transaction and taking away and discarding the aging transaction in real time;
the aging transaction receiving module is interacted with the controller module and the internal processing module connecting block and is used for submitting the aging transaction received through the controller module to the internal processing module.
Preferably, the links of the burn-in ports are single-path or multi-path.
Preferably, the last port upstream enable pin is multiplexed with the functional mode configuration pin.
Preferably, when the burn-in mode enable pin is valid and the last port upstream enable pin is valid, the particular burn-in port is a burn-in upstream port;
when the burn-in mode enable pin is active and the last port upstream enable pin is inactive, the particular burn-in port is a burn-in downstream port.
A high-temperature dynamic aging method of PCIe switching circuit comprises the following steps:
s1: configuring the port burn-in mode enable pin of each circuit by level;
for circuits with odd port numbers, the last port upstream enabling pin of one circuit on the adjacent aging station is configured to be effective through a level, and the last upstream enabling pin of the other circuit is configured to be ineffective;
for circuits with even numbers of ports, a last port upstream enabling pin is not set;
s2: connecting adjacent aging upstream ports and aging downstream ports on each aging station according to PCB printed lines conforming to PCIe protocol; the method comprises the steps that a transmitting signal of an aging upstream port is connected with a receiving signal of an aging downstream port, and the receiving signal of the aging upstream port is connected with the transmitting signal of the aging downstream port;
s3: powering up the circuit and generating a clock and reset meeting the circuit requirements;
s4: after the reset is finished, the PCIe switching circuit to be aged automatically enters an aging mode, and each aging upstream port and each aging downstream port carry out link training and establishment according to the PCIe protocol;
s5: after the link establishment is completed by the aging upstream port and the aging downstream port, the aging process in the circuit is started, and the aging downstream port periodically and continuously transmits PCIe aging transactions to the aging upstream port or periodically and continuously transmits PCIe aging transactions to the aging downstream port;
s6: the transaction indication of the circuitry at each burn-in station is monitored for periodic changes in the output signal during the burn-in and further a determination is made as to whether the burn-in circuitry is disabled.
Preferably, in S2, for circuits with an odd number of ports, specific burn-in ports of two circuits on adjacent burn-in stations are connected according to PCB tracks conforming to PCIe protocol; the specific burn-in port of one circuit on the adjacent burn-in station is used as a burn-in upstream port, and the specific burn-in port of the other circuit is used as a burn-in downstream port.
Compared with the prior art, the invention has the following beneficial effects:
the invention relates to a high-temperature dynamic aging system of a PCIe switching circuit, which comprises aging ports, an internal processing module, aging enabling pins and transaction processing output pins, wherein the system functionally maximizes the functions of a physical layer, a controller and transaction routing switching of the circuit, so that each port of the circuit performs transaction transmission and reception during aging, and performs dynamic aging according to the normal working frequency and bus interface rate of the PCIe switching circuit; according to the invention, each aging circuit is not required to be externally connected with PCIe root complex equipment and a plurality of PCIe endpoint equipment, aging can be carried out according to the working frequency of the circuit and the bus interface speed, and N multiplied by M peripheral PCIe equipment can be saved in the aging station of the circuit with M N ports, so that the use cost of components on an aging board is greatly saved; meanwhile, the peripheral PCIe equipment on the aging board is reduced, so that more stations are realized on the aging single board, more circuits can be aged in the same aging high-temperature box, and the test cost is saved.
The invention also discloses a high-temperature dynamic aging method of the PCIe switching circuit, which comprises the steps of enabling pins to be effective through level configuration of port aging modes of each circuit, so that the circuit to be aged enters an aging mode; setting the PCIe ports of the circuit to be aged with even number and odd number according to the situation ports, connecting adjacent aging upstream ports and aging downstream ports on each aging station according to PCB printed wiring conforming to PCIe protocol, powering on the circuit and generating clock and reset conforming to circuit requirements, so that the circuit is in designed aging working frequency and aging initial state; after the reset is finished, the PCIe switching circuit to be aged automatically enters an aging mode, and each aging upstream port and each aging downstream port carry out link training and establishment according to the PCIe protocol, so that a reliable link is provided for transmitting and receiving aging transactions in the subsequent steps; after the link establishment of the aging upstream port and the aging downstream port is completed, the aging process in the circuit is started, the aging of the functional logic such as physical layer transmission, controller transmission, transaction transmission and the like is realized through the transmission of aging transactions, and the aging of the functional logic such as physical layer receiving, controller receiving, routing and the like is realized through the receiving of the aging transactions; the transaction processing instruction of the circuit on each aging station is monitored in a polling mode during aging, whether the output signal changes periodically or not is judged, and whether an aging circuit fails or not is further judged, so that the judgment of circuit function failure can be realized in the aging process.
Drawings
FIG. 1 is a schematic diagram of a typical application of a PCIe switched circuit having N ports;
FIG. 2 is a diagram of the external interface connections of the high temperature dynamic burn-in system of the PCIe switch circuit of the present invention;
FIG. 3 is a schematic view of a burn-in upstream port or a burn-in downstream port burn-in mode configuration of the present invention;
FIG. 4 is a schematic diagram of a 7-port PCIe switched circuit structure and burn-in biasing of the present invention.
Detailed Description
The invention is described in further detail below with reference to the attached drawing figures:
example 1
A high-temperature dynamic aging system of PCIe switching circuit comprises an aging port, an internal processing module, an aging enable pin and a transaction processing output pin;
a burn-in port, including a burn-in upstream port and a burn-in downstream port, for receiving, routing, or discarding configuration transactions for a particular ID and memory transactions for a particular address range;
the internal processing module is interacted with the aging port and is used for detecting the transaction receiving state of each port in the circuit, forming a unified transaction processing signal and outputting the unified transaction processing signal to a transaction processing output pin; simultaneously, the received aging transaction is routed to an aging upstream port or an aging downstream port;
the aging enabling pin is respectively interacted with the internal processing module and the aging port and is used for enabling an aging mode of the PCIe switching circuit;
the transaction processing output pin is interacted with the internal processing module and is used for judging whether the circuit is normal or not in the aging period of the circuit;
when the number of PCIe ports in the circuit is odd, the system further includes a last port upstream enable pin for connecting with a particular burn-in port and configuring the particular burn-in port as either a burn-in upstream port or a burn-in downstream port.
Example 2
A dynamic burn-in mode system of a PCIe switching circuit comprises a burn-in upstream port, a burn-in downstream port, an internal processing module, a burn-in mode enabling pin, a last port upstream enabling pin and a transaction processing output pin; one aging upstream port and one aging downstream port can be externally connected; the internal processing module is connected with the aging upstream port; the internal processing module is connected with the aging downstream port; the aging enable pin is connected with an aging upstream port; the aging enable pin is connected with an aging downstream port; the aging enabling pin is connected with the internal processing module; finally, the upstream enabling pin of the port is connected with a specific port; the transaction output pin is connected with the internal processing module; the aging upstream port or aging downstream port comprises a physical layer module, a controller module, an aging transaction sending module, an outlet virtual receiving module and an aging transaction receiving module; the aging transaction sending module is connected with the controller module; the aging transaction receiving module is connected with the controller module and the internal processing module; the output virtual receiving module is connected with the internal processing module. The links of the aging upstream ports are multi-path.
Example 3
A high-temperature dynamic aging system of PCIe switching circuit comprises an aging port, an internal processing module, an aging enable pin and a transaction processing output pin;
the link of the aging upstream port is a single path (Lane); the link of the aging downstream port can be a single path (Lane), and the aging upstream port physical layer module realizes PCIe protocol physical layer functions; the aging upstream port controller realizes the data link layer function and the transaction layer function of the PCIe protocol; the aging downstream port comprises a physical layer module, a controller module, an aging transaction sending module, an outlet virtual receiving module and an aging transaction receiving module; the aging downstream port physical layer module realizes PCIe protocol physical layer functions; the aging downstream port controller realizes the data link layer function and the transaction layer function of the PCIe protocol; the burn-in mode enabling pin is used for enabling a burn-in mode of the PCIe switched circuit, so that part of ports of the circuit are configured as burn-in upstream ports and part of ports are configured as burn-in downstream ports; the last port upstream enabling pin is set only when the number of ports of the PCIe switch is odd; the pin need not be set for PCIe switching circuits for an even number of ports. The last port upstream enabling pin can be independently set or multiplexed with other functional mode configuration pins; when multiplexed with a functional mode configuration pin, the burn-in mode enable pin is interpreted as the last port upstream enable pin when it is active; otherwise the pin is interpreted as a functional mode pin. The configuration of the partial port of the circuit as a burn-in upstream port and the configuration of the partial port as a burn-in downstream port means that: half of the ports of the circuit are fixedly configured as burn-in upstream ports, and half of the ports are fixedly configured as burn-in downstream ports, which means that: one of the two ports adjacent or proximate to the PCIe pin of the port is fixedly configured as a burn-in upstream port and the other is fixedly configured as a burn-in downstream port.
The specific burn-in port connected to the last port upstream enable pin refers to: when the number of ports is odd, a specific port is selected, for example, the port with the largest port number is connected with the last port upstream enabling pin, and the port can be configured as a burn-in upstream port or a burn-in downstream port; when the aging mode enabling pin is valid and the last port upstream enabling pin is valid, the selected specific aging port is used as an aging upstream port; when the aging mode enabling pin is effective and the last port upstream enabling pin is ineffective, the selected specific aging port is used as an aging downstream port;
the aging upstream port is configured as an upstream port in an aging mode, and can receive, route or discard configuration transactions of a specific ID and memory transactions of a specific address range by configuring an original bus number (Primary Bus Number), a secondary bus number (Secondary Bus Number) and a subordinate bus number (Subordinate Bus Number) in the aging upstream port, a memory base point register and a memory limit register to be fixed values or/and configuration routing modes;
the aging downstream port is configured as a downstream port in an aging mode, and can receive, route or discard the configuration transaction of a specific ID and the memory transaction of a specific address range by configuring the primary bus number, the secondary bus number and the subordinate bus number, the memory base point register and the memory limit register in the aging downstream port as fixed values or/and configuration routing; the aging transaction sending module of the aging upstream port or the aging downstream port periodically sends the same transaction or different transactions as aging transactions to the downstream port or the upstream port of the opposite end through the controller module and the physical layer module after a pair of the aging upstream port and the aging downstream port complete link training and establish links; the aging transaction receiving module of the opposite aging downstream port or the aging upstream port submits the aging transaction received via the physical layer and the controller module to the internal processing module.
The internal processing module routes the aging transaction to an outlet virtual receiving module of the aging upstream port or the aging downstream port; the virtual receiving module at the outlet end of the aging upstream port or the aging downstream port executes the virtual receiving function of the aging transaction, and the aging transaction is taken away and discarded in real time; the internal processing module also detects the transaction receiving state of each port of the circuit and forms a unified transaction signal, and outputs the unified transaction signal to the transaction output pin; the transaction output pin can be independently arranged or multiplexed with other functional mode pins; when multiplexed with other functional mode pins, the burn-in mode enable pin is valid and is interpreted as the transaction output pin; the transaction output pin is used to determine whether the circuit is normal during circuit burn-in.
Example 4
Dynamic burn-in mode architecture and burn-in biasing for a 7-port PCIe switch circuit implemented according to the invention. As shown in fig. 4, the circuit is composed of 7 ports and an internal processing module, and a burn-in mode enable pin, a last port upstream enable pin and a transaction output pin are set. Port 0 and port 1 of the circuit are physically adjacent, port 2 and port 3 are physically adjacent, and port 4 and port 5 are physically adjacent.
In the circuit of the embodiment, the ports 0 to 5 are 4-path link ports, and the port 6 is a 2-path link port; each PCIe port of the circuit comprises a physical layer module, a controller module, a burn-in transaction transmitting module, an outlet virtual receiving module and a burn-in transaction receiving module; the IO power supply of the circuit of the embodiment is 2.25V-2.75V.
The circuit fixedly configures a port 0, a port 2 and a port 4 in 7 ports as a aging upstream port, and fixedly configures a port 1, a port 3 and a port 5 as a aging downstream port; port 0 and Port 1 provide stimulus and load to each other through PCB printed wiring connections; similarly, port 2 is connected to port 3, and port 4 is connected to port 5; the remaining ports 6 are selected as special ports and are connected to ports 6 of another burn-in circuit on an adjacent station to provide the stimulus and load to each other.
Example 5
In the present embodiment, the primary bus number inside the burn-in upstream port 0, port 2, port 4 is configured as 1, the secondary bus number is configured as 2, the subordinate bus number is configured as 8, the memory base point register is configured as 0x00000, the memory limit register is configured as 0xFFFFF, and the routing table is configured to route all transactions to the adjacent burn-in downstream port in the burn-in mode; fixedly configuring internal primary bus numbers of a burn-in downstream port 1, a port 3 and a port 5 as 2, configuring secondary bus numbers as 3, configuring subordinate bus numbers as 3, configuring a memory base point register as 0x00000, configuring a memory limit register as 0x0000F, and configuring a routing table to route all transactions to adjacent burn-in upstream ports; the internal primary bus number of special port 6 is fixedly configured to 2, the secondary bus number is configured to 3, the subordinate bus number is configured to 3, the memory base point register is configured to 0x00000, the memory limit register is configured to 0x0000F, and the routing table is configured to discard all transactions.
The aging transaction sending module of the aging upstream port of the embodiment is designed to detect and judge whether link training is completed, and periodically send configuration read transactions and memory write transactions to the aging downstream port according to the sequence of 'configuration read transactions, 1ms waiting interval, 1ms writing transactions waiting interval' after an indication signal linkup of link establishment completion is valid; wherein the read transaction access bus 3 is configured, and the memory write transaction write address is 0x00FFF00000;
as shown in fig. 2 and 3, the aging transaction sending module of the aging downstream port is designed to detect and determine whether link training is completed, and send the configuration read transaction and the memory write transaction to the aging upstream port periodically according to the sequence of "configuration read transaction→interval wait for 1ms→memory write transaction→interval wait for 1ms" after the indication signal linkup of link establishment completion is valid. The aging upstream port 0, the port 2 and the port 4 route the received configuration transaction and the memory write transaction to an outlet virtual receiving module of the aging downstream port; the aging downstream port 1, the port 3 and the port 5 route the received configuration transaction and the memory write transaction to an outlet virtual receiving module of the aging upstream port; port 6 discards the received configuration transaction and memory write transaction.
The virtual receiving module at the output end of the embodiment can read the transaction in the cache; when the outlet virtual receiving module of the aging upstream port or the aging downstream port receives the routed aging transaction, the outlet virtual receiving module immediately takes the transaction away and discards the transaction; 7 ports of the internal processing module detection circuit of the embodiment, when a certain port does not receive a burn-in transaction within 2ms, a transaction output pin is set to be low-level output; when all ports can receive the burn-in transaction within 2ms, a high level pulse is output every 2 ms.
To save circuit pin count, the last port upstream enable pin and transaction output pin are multiplexed with other functional mode pins in this embodiment. The link widths of the upstream and downstream ports are typically uniform.
Example 5
A high-temperature dynamic aging method of a PCIe switching circuit comprises the following steps:
s1: pulling up the burn-in mode enabling pin of each circuit to a 2.75V power supply through a resistor, so that the burn-in mode enabling pin of the circuit is effective;
s2: the last port upstream enabling pin on the circuit with the even station number is pulled up to a 2.75V power supply through a resistor, so that the last port upstream enabling pin is effective; grounding the last port upstream enabling pin on the circuit with the station number being odd, and invalidating the last port upstream enabling pin;
s3: connecting a port 0 and a port 1, a port 2 and a port 3, and a port 4 and a port 5 on each aging station according to PCB printed lines conforming to PCIe protocol; the method comprises the steps that a transmitting signal of an aging upstream port is connected with a receiving signal of an aging downstream port, and the receiving signal of the aging upstream port is connected with the transmitting signal of the aging downstream port;
s4: ports 6 of two circuits on adjacent aging stations (an even numbered station and an odd numbered station) are connected according to PCB printed lines conforming to PCIe protocol; the ports 6 on even stations are used as aging upstream ports, and the ports 6 on odd stations are used as aging downstream ports;
s5: powering on a circuit through power supplies, clocks and reset signals provided by other components and/or a burn-in board and generating a power-on reset with the frequency of 100MHz input clock and 200 us;
s6: after the reset is finished, the PCIe switching circuit to be aged automatically enters an aging mode, and each aging upstream port and each aging downstream port carry out link training and establishment according to the PCIe protocol;
s7: after the link establishment of the aging upstream port and the aging downstream port is completed, the aging process in the circuit is started, wherein the aging downstream port periodically and continuously transmits PCIe aging transactions to the aging upstream port or the aging upstream port to the aging downstream port;
s8: during aging, the transaction processing indication output signals of the circuits on each aging station are monitored through the polling of an oscilloscope carried by aging equipment, and whether positive pulses are output for 2ms periodically or not is judged; if the transaction indicates that the output signal periodically outputs a positive pulse for 2ms, the circuit is normal, otherwise, the circuit aging failure is judged.
According to the high-temperature dynamic aging method for the PCIe switching circuit, the port aging mode enabling pins of each circuit are configured to be effective through the level, so that the circuit to be aged enters an aging mode; when the PCIe port number of the aging circuit is even, enabling half ports of the circuit to enter an aging upstream port mode and half ports to enter an aging downstream port mode; when the PCIe port number of the circuit is odd, the last port upstream enabling pin of one circuit on the adjacent aging station is configured to be valid through the level, so that a specific aging port enters an aging upstream mode; the last upstream enabling pin of the other circuit is invalid, so that a specific burn-in port of the other circuit enters a burn-in downstream mode;
connecting adjacent aging upstream ports and aging downstream ports on each aging station according to PCB printed lines conforming to PCIe protocol; the method comprises the steps that a transmitting signal of an aging upstream port is connected with a receiving signal of an aging downstream port, and the receiving signal of the aging upstream port is connected with the transmitting signal of the aging downstream port; the transmission signals of the upstream port and the downstream port are excited to the reception signals of the downstream port and the upstream port, respectively, and the reception signals of the upstream port and the downstream port are used as the aging load for transmitting the signals of the downstream port and the upstream port, respectively. Powering up the circuit and generating a clock and reset meeting the circuit requirements, so that the circuit is in a designed aging working frequency and aging initial state; after the reset is finished, the PCIe switching circuit to be aged automatically enters an aging mode, and each aging upstream port and each aging downstream port carry out link training and establishment according to the PCIe protocol, so that a reliable link is provided for transmitting and receiving aging transactions in the subsequent steps; after the link establishment is completed by the aging upstream port and the aging downstream port, the aging process in the circuit is started, and the aging downstream port periodically and continuously transmits PCIe aging transactions to the aging upstream port or periodically and continuously transmits PCIe aging transactions to the aging downstream port; the aging of the functional logic such as physical layer transmission, controller transmission, transaction transmission and the like is realized through the transmission of aging transactions, and the aging of the functional logic such as physical layer receiving, controller receiving, routing and the like is realized through the receiving of aging transactions; the transaction processing instruction of the circuit on each aging station is monitored in a polling mode during aging, whether the output signal changes periodically or not is judged, whether the aging circuit fails or not is further judged, and judging of circuit function failure can be achieved in the aging process.
The above is only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited by this, and any modification made on the basis of the technical scheme according to the technical idea of the present invention falls within the protection scope of the claims of the present invention.
Claims (9)
1. A high-temperature dynamic aging system of a PCIe switching circuit is characterized by comprising an aging port, an internal processing module, an aging enabling pin and a transaction processing output pin;
a burn-in port, including a burn-in upstream port and a burn-in downstream port, for receiving, routing, or discarding configuration transactions for a particular ID and memory transactions for a particular address range;
the internal processing module is interacted with the aging port and is used for detecting the transaction receiving state of each port in the circuit, forming a unified transaction processing signal and outputting the unified transaction processing signal to a transaction processing output pin; simultaneously, the received aging transaction is routed to an aging upstream port or an aging downstream port;
the aging enabling pin is respectively interacted with the internal processing module and the aging port and is used for enabling an aging mode of the PCIe switching circuit;
the transaction processing output pin is interacted with the internal processing module and is used for judging whether the circuit is normal or not in the aging period of the circuit;
when the number of PCIe ports in the circuit is odd, the system further includes a last port upstream enable pin for connecting with a particular burn-in port and configuring the particular burn-in port as either a burn-in upstream port or a burn-in downstream port.
2. The high temperature dynamic burn-in system of PCIe switching circuitry of claim 1 wherein,
the structure of the aging upstream port or the aging downstream port is the same;
the burn-in upstream port and the burn-in downstream port are connected to the burn-in downstream port and the burn-in upstream port of the same or different burn-in circuits, respectively, by PCB tracks.
3. The high temperature dynamic burn-in system of PCIe switch circuit of claim 1 wherein when the number of PCIe ports in the circuit is even, half of the ports are fixedly configured as burn-in upstream ports and half of the ports are fixedly configured as burn-in downstream ports;
when the number of PCIe ports in the circuit is odd, the circuit further comprises a specific burn-in port connected with an upstream enabling pin of the last port, and half ports in the rest ports are fixedly configured as burn-in upstream ports, and the other half ports are fixedly configured as burn-in downstream ports except for the specific burn-in port.
4. The PCIe switch circuit high temperature dynamic burn-in system of claim 1 wherein the burn-in port comprises a physical layer module, a controller module, a burn-in transaction transmit module, an out-side virtual receive module, and a burn-in transaction receive module;
the physical layer module is interacted with the controller module and is used for realizing PCIe protocol physical layer functions;
the controller module is respectively interacted with the internal processing module and the aging transaction sending module and is used for acquiring a data link layer of the PCIe protocol and controlling the sending of the aging transaction;
the aging transaction sending module is interacted with the controller module and is used for periodically sending aging transactions to an opposite end downstream port or an opposite end upstream port connected with the port through the controller module and the physical layer module after the link training is finished and the link is established;
the output end virtual receiving module is interacted with the internal processing module and is used for executing the virtual receiving function of the aging transaction and taking away and discarding the aging transaction in real time;
the aging transaction receiving module is interacted with the controller module and the internal processing module connecting block and is used for submitting the aging transaction received through the controller module to the internal processing module.
5. The PCIe switch circuit high temperature dynamic burn-in system of claim 1 wherein the link of the burn-in port is single path or multiple paths.
6. The high temperature dynamic burn-in system of PCIe switching circuitry of claim 1 wherein the last port upstream enable pin is multiplexed with the functional mode configuration pin.
7. The high temperature dynamic burn-in system of PCIe switching circuitry of claim 1 wherein,
when the burn-in mode enabling pin is valid and the last port upstream enabling pin is valid, the specific burn-in port is a burn-in upstream port;
when the burn-in mode enable pin is active and the last port upstream enable pin is inactive, the particular burn-in port is a burn-in downstream port.
8. A high-temperature dynamic aging method of a PCIe switching circuit is characterized by comprising the following steps:
s1: configuring the port burn-in mode enable pin of each circuit by level;
for circuits with odd port numbers, the last port upstream enabling pin of one circuit on the adjacent aging station is configured to be effective through a level, and the last upstream enabling pin of the other circuit is configured to be ineffective;
for circuits with even numbers of ports, a last port upstream enabling pin is not set;
s2: connecting adjacent aging upstream ports and aging downstream ports on each aging station according to PCB printed lines conforming to PCIe protocol; the method comprises the steps that a transmitting signal of an aging upstream port is connected with a receiving signal of an aging downstream port, and the receiving signal of the aging upstream port is connected with the transmitting signal of the aging downstream port;
s3: powering up the circuit and generating a clock and reset meeting the circuit requirements;
s4: after the reset is finished, the PCIe switching circuit to be aged automatically enters an aging mode, and each aging upstream port and each aging downstream port carry out link training and establishment according to the PCIe protocol;
s5: after the link establishment is completed by the aging upstream port and the aging downstream port, the aging process in the circuit is started, and the aging downstream port periodically and continuously transmits PCIe aging transactions to the aging upstream port or periodically and continuously transmits PCIe aging transactions to the aging downstream port;
s6: the transaction indication of the circuitry at each burn-in station is monitored for periodic changes in the output signal during the burn-in and further a determination is made as to whether the burn-in circuitry is disabled.
9. The method of high temperature dynamic burn-in of PCIe switching circuits of claim 8 wherein in S2, for circuits having an odd number of ports, specific burn-in ports of two circuits on adjacent burn-in stations are connected according to PCB tracks conforming to PCIe protocol; the specific burn-in port of one circuit on the adjacent burn-in station is used as a burn-in upstream port, and the specific burn-in port of the other circuit is used as a burn-in downstream port.
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