CN112106191A - 用于晶片级芯片封装的半导体结构和方法 - Google Patents

用于晶片级芯片封装的半导体结构和方法 Download PDF

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CN112106191A
CN112106191A CN201980030172.4A CN201980030172A CN112106191A CN 112106191 A CN112106191 A CN 112106191A CN 201980030172 A CN201980030172 A CN 201980030172A CN 112106191 A CN112106191 A CN 112106191A
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rdl
layer
semiconductor structure
polyimide layer
pillars
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I·W·兰穆图
M·K·贾因
T·S·保尔森
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

实施例半导体结构(100)包含金属层(304)。所述半导体结构(100)还包含重布线层RDL结构(352和354)，所述结构包含RDL平台(352)和设置在所述RDL平台(352)与所述金属层(304)之间的多个RDL柱(354)。另外，所述半导体结构(100)包含设置在所述RDL平台(352)上的凸块下金属UBM层(392)，以及设置在所述UBM层(392)上的焊料凸块(102)，其中所述UBM层(392)、所述RDL平台(352)和所述RDL柱(354)在所述焊料凸块(102)与所述金属层(304)之间形成电连接。

Description

用于晶片级芯片封装的半导体结构和方法
本发明总体涉及半导体电路封装，更具体涉及用于晶片级芯片封装的半导体结构和方法。
背景技术
在晶片级芯片封装(WCSP)中，芯片直接安装在板上。切割单个芯片，并且使用凸块连接将芯片直接安装在板上而不进行封装。
发明内容
实例半导体结构包含金属层。半导体结构还包含重布线层(RDL)结构，所述结构包含RDL平台和设置在RDL平台与金属层之间的多个RDL柱。另外，半导体结构包含设置在RDL平台上的凸块下金属(UBM)层和设置在UBM层上的焊料凸块，其中UBM层、RDL平台和RDL柱形成焊料凸块与金属层之间的电连接。
实例半导体结构包含重布线层(RDL)结构，所述结构包含RDL平台和支撑所述RDL平台的多个RDL柱。半导体结构还包含在多个RDL柱之间并且在RDL平台的第一侧上的第一聚酰亚胺层和在RDL平台的第二侧上的第二聚酰亚胺层，RDL平台的第二侧与RDL平台的第一侧相对。
形成半导体结构的实例方法包含在晶片上沉积金属层和在金属层上形成聚酰亚胺层。所述方法还包含在聚酰亚胺层中形成柱开口，并在柱开口中和聚酰亚胺层的一部分上沉积重布线层(RDL)，其中聚酰亚胺层设置在金属层与RDL之间。
附图说明
图1是实例半导体结构的截面图。
图2A至D是实例半导体结构的顶视图。
图3A至I是半导体结构制造的实例阶段的截面图。
图4是实例晶体管结构。
图5是制造半导体结构的实例方法的流程图。
图6是利用半导体结构的实例方法的流程图。
除非另有说明，不同图中的相应数字和符号通常指相应的部件。绘制附图以清楚地示出说明性实例布置的相关方面，并且不一定按比例绘制。
具体实施方式
在晶片级芯片封装(WCSP)中，管芯直接安装在印刷电路板(PCB)上，而不是经过封装工艺并将封装装置安装在PCP上。由于缺少附加的封装，WCSP结构可能很小。另外，在WCSP中使用直接连接能够实现低电阻和高电流操作。
在实例中，刚性凸块堆叠结构用于WSPC。焊料凸块被放置在凸块下金属(UBM)层上，所述凸块下金属层被耦合在下金属层上。这种刚性结构可能不太适于处理机械应力。在后续处理步骤中的热循环期间，机械应力可能尤其成问题。机械应力可导致断裂并降低。
功率晶体管(例如双极结晶体管(BJT))、晶闸管、绝缘栅双极晶体管(IGBT)或功率金属氧化物半导体场效应晶体管(MOSFET)(例如由德州仪器(Texas Instruments)生产的NexFETsTM装置)可能非常适合于WCSP。功率晶体管可以是大尺寸的并且在WCSP中具有与WCSP环境相关的高应力。而且，功率晶体管可以在高电流下工作，并且可能需要低电阻连接。
在实例中，凸块结构包含重布线层(RDL)。RDL可以包含由RDL柱支撑的RDL平台。在实例中，具有RDL结构的凸块阵列用于功率晶体管。在实例中，RDL减小了凸块结构上的机械应力。在实例中，RDL能够实现具有高电流能力的低电阻连接。例如，实施例凸块结构具有小于2.5mohm的电阻。一个实施例具有用于吸收水平和垂直应力并且减少断裂的两个聚酰亚胺层。一个实施例能够使用WCSP安装大功率晶体管，例如大于1mm×1mm。一个实施例具有良好的电迁移能力。
图1示出半导体结构100的截面图。衬底302包含至少一个晶体管或集成电路，例如一或多个功率晶体管(例如BJT)、晶闸管、IGBT或功率MOSFET(例如由德州仪器生产的NexFETTM装置)。在实例中，衬底302包含模拟电路，例如高功率模拟电路。衬底302可以是具有各种金属、电介质和/或半导体层的半导体衬底，例如硅。在衬底302上设置金属层304。在实例中，金属层304是金属1(MET1)层、金属2(MET2)层、金属3(MET3)层或另一金属层。金属层304可以是铜、铝或其它金属，例如金属合金。在一个实施例中，衬底302和金属层304的厚度在7mm与14mm之间，例如在8mm至9mm之间。背面金属层306位于衬底302的与金属层304相反的一侧上。在一些实施例中，不存在背面金属层306。在一个实例中，背面金属层306由银、镍或金构成。背面金属层306的厚度可以在1μm与5μm之间，例如大约3.4μm厚。钝化层332设置在金属层304上。钝化层332是氧化物层，例如二氧化硅。聚酰亚胺层334设置在钝化层332上。聚酰亚胺层334由酰亚胺单体的聚合物构成。在实例中，聚酰亚胺层334在5μm与10μm之间，例如7.5μm。
焊盘开口104和106延伸穿过钝化层332和聚酰亚胺层334。重布线层(RDL)结构352具有设置在聚酰亚胺层334上的RDL平台356以及RDL柱354，所述RDL柱354在RDL平台356与金属层304之间延伸穿过焊盘开口104和106到达金属层304。RDL由金属(如铜)构成。在实例中，RDL平台356的厚度在3μm与7μm之间，例如5μm。在RDL平台356上是聚酰亚胺层372，即第二聚酰亚胺层。聚酰亚胺层372可以主要包围RDL平台356，覆盖RDL平台356的侧面和RDL平台356的顶部的一部分，并具有开口374。在实施例中，聚酰亚胺层372的厚度在5μm与10μm之间，例如7.5μm厚。在一个实例中，聚酰亚胺层372具有与聚酰亚胺层334相同的厚度。在其它实例中，聚酰亚胺层372比聚酰亚胺层334厚。在另外的实例中，聚酰亚胺层372比聚酰亚胺层334薄。凸块下金属(UBM)层392通过聚酰亚胺层372中的开口374与RDL平台356接触。UBM层392由金属构成，例如Ti、TiW或另一种钛合金。焊料凸块102位于UBM层392上。焊料凸块102提供与PCB的物理和电连接。焊料凸块102可以由铅焊料或无铅焊料构成。
UBM层392、RDL平台356和RDL柱354在焊料凸块102与金属层304之间形成电连接。这种电连接在焊料凸块102与金属层304之间提供低电阻电连接。例如，电连接可以具有小于2.5mohm的电阻。而且，焊料凸块102与金属层304之间的电连接支持高电流，例如10A。焊料凸块102连接到UBM层392，所述UBM层392还连接到RDL结构352。RDL柱354延伸穿过焊盘开口104和106，提供与金属层304的低电阻电连接。RDL柱354被描绘为不在焊料凸块102的正下方但在焊料凸块102的外部，而是全部或部分在凸块102的下面。在实施例中，柱靠近RDL层的周边。在RDL平台356下方并且在RDL柱354之间以及围绕RDL柱354的聚酰亚胺层334提供了横向和竖向挠度。在RDL平台356之上和周围的聚酰亚胺层372提供附加的物理支撑。半导体结构100能够承受高水平的机械应力，同时处理具有低电阻的高电流。
在一个实例中，衬底302和金属层304的厚度大约为8mm。背面金属层306大约3.4μm厚，RDL平台356大约5μm厚，聚酰亚胺层334大约7.5μm厚，并且聚酰亚胺层372大约7.5μm厚。
图2A至D示出几个实例半导体结构的顶视图。每个柱横截面可以与柱的每个数量和分布以及与每个RDL平台几何结构相结合。图2A示出半导体结构200的顶视图，其可展示由图1示出的半导体结构100的顶视图。凸块208处于半导体结构200的中心。在一些实施例中，凸块208偏离半导体结构200的中心。在凸起208下方的RDL平台204是盘状的。在其它实施例中，RDL可以具有其它形状，例如可以是椭圆形或不规则形状。此外，RDL柱206围绕凸块208的中心以环形布置。RDL柱206支撑RDL平台204。RDL柱206被示出为具有圆形横截面，但也可具有其它截面，例如椭圆形或不规则截面形状。示出了八个柱，但是可以存在另外数量的柱。例如，可以有四个柱与十六个柱之间的柱。在一些实例中，存在更多的柱，例如十六个至32个柱。
图2B示出半导体结构210的顶视图。凸块218在半导体结构210中，而RDL平台214在凸块218下方。如图所示，RDL平台214是正方形的，但是RDL平台214可以是另一种形状，例如矩形或具有圆角的正方形。RDL柱216支撑RDL平台214，并且将RDL平台214耦合到下金属层。存在四个RDL柱，但可使用另一数量的柱，例如六个或八个柱。
图2C示出半导体结构230。凸块238在半导体结构230中，而RDL平台234设置在凸块238下方。RDL平台234的形状为八边形，但也可以是其它多边形，例如五边形、六边形、七边形、九边形、十边形、十一边形或十二边形。多边形可以是等边的或者可以具有长度不同的边。RDL柱236支撑RDL平台234并将RDL平台234电连接到下导电层。在实例中，具有与多边形边相同数量的柱。在其它实例中，柱比多边形边的数量多，或者柱比多边形边的数量少。
图2D示出半导体结构240。凸块248在半导体结构240中。RDL 244设置在凸块248下方。RDL柱246支撑RDL 244，并且将RDL 244电耦合到下导电层。RDL柱具有另一形状，例如矩形、另一多边形或不规则形状。
图3A至3J示出图1中所示的半导体结构100的制造。图3A示出了包含衬底302的半导体结构。仍为晶片形式的衬底302可以是包含晶体管和/或集成电路的硅衬底，具有各种半导体、金属和电介质层。衬底302可以包含功率装置，例如一或多个功率晶体管或功率模拟元件。金属层304设置在衬底302上。金属层304可以是MET1层、MET2层、MET3层或另一金属层。与金属层304相比，衬底302可以在衬底302的相对侧上具有背面金属层306。背面金属层306可以由银、镍或金构成。
在图3B中，系统在金属层304上沉积钝化层312。钝化层312可以是氧化物层，例如二氧化硅。钝化层312可以例如通过化学气相沉积(CVD)来沉积。在图3C中，系统在钝化层312上沉积聚酰亚胺层322。聚酰亚胺层可以使用逐步生长聚合或固相合成来形成。在图3D中，系统在钝化层332和聚酰亚胺层334中蚀刻包含衬垫开口104和106的柱图案。为此，系统在聚酰亚胺层322上旋转光致抗蚀剂。然后，系统使用光刻掩模曝光光致抗蚀剂层，光刻掩模可以是正掩模或负掩模。这种曝光将光刻掩模的图案转移到光致抗蚀剂上。然后，蚀刻将图案从光致抗蚀剂层转移到聚酰亚胺层322，以产生聚酰亚胺层334，并转移到钝化层312，以产生钝化层332。在蚀刻之后，系统可以去除剩余的光致抗蚀剂。
在图3E中，系统在聚酰亚胺层334上沉积RDL 342。系统可以使用蒸发、溅射或CVD来沉积RDL 342。RDL 342在沉积时填充焊盘开口104和106并形成RDL柱354。在实施例中，RDL 342由铜构成。在图3F中，系统图案化RDL 342，以产生RDL结构352。系统将光致抗蚀剂施加到RDL 342上。然后，系统使用光刻掩模曝光光致抗蚀剂，光刻掩模可以是正掩模或负掩模。这种曝光将图案从光刻掩模转移到光致抗蚀剂层。然后，系统蚀刻RDL，以将图案从光致抗蚀剂转移到RDL。系统可以去除剩余的光致抗蚀剂。
在图3G中，系统施加聚酰亚胺层362。在一些实例中，聚酰亚胺层362由与聚酰亚胺层334相同的材料构成。在其它实例中，聚酰亚胺层362由与聚酰亚胺层334不同的聚酰亚胺材料构成。在图3H中，系统图案化聚酰亚胺层362，以产生聚酰亚胺层372。系统通过将光致抗蚀剂施加到聚酰亚胺层362来执行光刻。然后，系统蚀刻聚酰亚胺层362，从而在聚酰亚胺层372中形成开口374。系统还可以去除剩余的光致抗蚀剂。
在图3I中，系统经由开口374将UBM 382施加到聚酰亚胺层372和RDL结构352。系统可以使用蒸发、溅射或CVD来施加UBM 382。UBM层392可以是金属，例如Ti、TiW或另一种钛合金。如图1所示，将焊料凸块102施加到UBM层392。焊料凸块102由焊料构成，焊料可以是无铅焊料。可以用湿膜或干膜再钝化来进行凸块形成。在用钝化和湿膜进行凸块形成的情况下，系统施加光致抗蚀剂、曝光光致抗蚀剂，并在UBM层392上显影光致抗蚀剂。然后，系统用铜/焊料或铜/镍/焊料进行电镀。然后系统剥离光致抗蚀剂。然后，系统蚀刻UBM材料。最后，系统通过加热UBM材料进行回流。在用干膜进行凸块形成时，系统进行干膜层压、曝光和显影。然后，系统使用Cu/Ni/焊料镀层镀敷到干膜上。接着，系统剥离干膜，随后蚀刻UBM。最后，系统在UBM层392上进行回流。
图4示出了具有用于WCSP的RDL聚酰亚胺结构的晶体管结构500。晶体管结构500包含结构502、504、506、508、510、512、514和516，其具有凸块结构，例如图1所示的半导体结构100。结构502、504、506、508、510、512、514和516是由德州仪器制造的NexFETTM装置，其中电流垂直流动。结构502、504、506和508是源极，而结构510、512、514和516是漏极。背面金属(未示出)连接源极和漏极。
图5示出了制造半导体结构(例如图1所示的半导体结构100)的实施例方法的流程图600。在框601中，系统获得晶片。晶片可以包含衬底(例如硅)，包含至少一个晶体管或集成电路。晶片可以包含各种金属、半导体和电介质层。晶体管或集成电路可以包含一或多个功率晶体管，例如由德州仪器制造的NexFETTM器件，或模拟功率电子器件。在框602中，系统对晶片进行背面研磨。例如，将晶片背面研磨到在6密耳与14密耳之间，例如在8密耳与9密耳之间。系统清洁晶片的顶表面。而且，系统在晶片的顶表面上施加保护带，以保护晶片免受机械损伤和污染。系统将晶片装载到盒上，所述盒放置在背面研磨机器的盒保持器中。背面研磨机器用机械臂拾取晶片的背面，所述机械臂定位晶片用于背面研磨。砂轮对晶片进行背面研磨。系统可以在背面研磨期间用去离子水连续地洗涤晶片。在背面研磨之后，晶片返回到盒中。例如，系统使用撕带工具从晶片上去除背面研磨带。
在框604中，系统将背面金属沉积到晶片的背面。可以使用射频(RF)或直流(DC)溅射和电子束蒸发来施加金属。背面金属化层可以具有良好的欧姆接触层，例如银、镍或金。
在框606中，系统通过金属化将一或多个金属层沉积到晶片的正面。可以在框602之前、在框602与框604之间或者在框604之后执行框606。可以通过溅射、蒸发或CVD来施加金属层。溅射可以是例如离子束溅射、反应溅射、离子辅助沉积(IAD)、高靶利用率溅射(HiTUS)、高功率脉冲磁控管溅射(HiPIMS)或气流溅射。在实施例中，使用脉冲激光沉积。蒸发的实例包含热蒸发、电子束蒸发、闪蒸或电阻蒸发。可以例如通过进行蚀刻或剥离将图案施加到金属层上。通过蚀刻，沉积金属层，并将光致抗蚀剂层施加到金属层上。通过曝光将图案从光刻掩模转移到光致抗蚀剂。然后，通过蚀刻将图案从光致抗蚀剂转移到金属层。在剥离时，在金属层之前施加光致抗蚀剂层。通过曝光将图案从光刻掩模转移到光致抗蚀剂层。然后，将金属沉积在光致抗蚀剂上，并沉积到光致抗蚀剂中的开口中。接着，去除光致抗蚀剂，留下沉积在开口中的金属，同时去除光致抗蚀剂层上的金属部分。金属层可以是铜、另一种金属(例如铝)，或合金。
在框608中，系统将钝化层沉积到在框606中施加的金属层上。钝化层可以是氧化物，例如二氧化硅。钝化层可以通过CVD沉积。
在框610中，系统形成第一聚酰亚胺层到框608中沉积的钝化层。可以使用逐步生长聚合或固相合成形成第一聚酰亚胺层。
在框612中，系统图案化框608中沉积的钝化层和框610中形成的第一聚酰亚胺层。将光致抗蚀剂层施加到钝化层上。然后，使用光刻掩模图案化光致抗蚀剂层。掩模可以是正掩模或负掩模。然后，蚀刻第一聚酰亚胺层和钝化层。因此，在第一聚酰亚胺层和钝化层中形成开口。接下来，可以去除剩余的光致抗蚀剂。
在框614中，系统将RDL沉积到第一聚酰亚胺层以及第一聚酰亚胺层和钝化层的开口中。RDL可以是铜或其它金属。系统使用溅射、蒸发或CVD沉积RDL。基于第一聚酰亚胺层中的图案将RDL沉积成柱。系统还对RDL进行图案化。在一个实例中，在沉积RDL之前将光致抗蚀剂沉积在聚酰亚胺层上并进行图案化。然后，执行剥离以对RDL进行图案化。在另一实施例中，在RDL上进行光刻和蚀刻。
在框618中，系统形成第二聚酰亚胺层并对其进行图案化。系统可以使用逐步生长聚合或固相合成形成第二聚酰亚胺层。第二聚酰亚胺层可以具有与第一聚酰亚胺层相同的厚度、比第一聚酰亚胺层薄，或者比第一聚酰亚胺层厚。系统使用光刻和蚀刻来图案化第二聚酰亚胺层。将光致抗蚀剂施加到第二聚酰亚胺层。通过光刻掩模对光致抗蚀剂进行曝光。然后，在已经去除光致抗蚀剂的区域中蚀刻第二聚酰亚胺层。可以去除光致抗蚀剂。
在框622中，系统沉积UBM层。UBM可以由钛或钛合金(如TiW)构成。UBM可以通过溅射、蒸发或无电镀沉积。
在框626中，系统形成焊料凸块到框622中沉积的UBM层。焊料凸块可以由Sn/Pb、Pb、Sn/Ag/Cu、Sn/Ag或另一种合金构成，这些合金可以是铅基焊料或无铅焊料。可以用湿膜或干膜再钝化来进行凸块形成。在用钝化和湿膜进行凸起形成的情况下，系统施加、曝光光致抗蚀剂并在UBM上显影光致抗蚀剂。然后，系统进行铜/焊料电镀或铜/镍/焊料电镀。系统剥离光致抗蚀剂，并蚀刻UBM。最后，系统使UBM回流以形成焊球。在用干膜进行凸块形成时，系统进行干膜层压、曝光和显影。然后，系统电镀干膜层压Cu/Ni/焊料镀层。接下来，进行干膜剥离，接着进行UBM蚀刻。最后，系统执行回流以形成焊料凸块。
图6示出在WCSP中利用半导体结构的实施例方法的流程图700。在框702中，系统切割芯片以形成管芯。多个芯片可以各自包含凸块结构，例如图1所示的半导体结构100。晶片切割可以通过划线折断法、例如使用切割锯的机械锯切或激光切割来进行。在切割期间可以将晶片安装在切割带上。
在框704中，管芯分别安装在PCB上。芯片被翻转并定位，其中焊球面向PCB上的适当电路。例如，使用热空气回流使焊球再熔化。所安装的芯片使用电绝缘粘合剂可能填充不足，以提供支撑和保护。
在框706中，PCB上管芯的电路工作。例如，功率晶体管(如由德州仪器制造的NexFETTM装置)可以执行功率切换。功率晶体管可以以低电阻和高电流密度工作。在一个实例中，功率晶体管可以最高5A工作。
尽管已经详细描述了实例说明性布置，但是在不脱离由所附权利要求书限定的本申请的精神和范围的情况下，可以在此进行各种改变、替换和变更。
此外，本申请的范围不限于本说明书中描述的实例。因此，所附权利要求旨在在其范围内包含其它此些过程、机器、制造、物质成分、装置、方法或步骤。

Claims (20)

1.一种半导体结构，其包括：
金属层；
重布线层RDL结构，其包括：
RDL平台；
设置在所述RDL平台与所述金属层之间的多个RDL柱；
设置在所述RDL平台上的凸块下金属UBM层；以及
设置在所述UBM层上的焊料凸块，其中所述UBM层、所述RDL平台和所述RDL柱在所述焊料凸块与所述金属层之间形成电连接。
2.根据权利要求1所述的半导体结构，其中所述多个RDL柱是至少四个柱。
3.根据权利要求2所述的半导体结构，其中所述多个RDL柱是至少八个柱。
4.根据权利要求1所述的半导体结构，其中所述焊料凸块与所述金属层之间的所述电连接具有小于2.5mohm的电阻。
5.根据权利要求1所述的半导体结构，其中所述焊料凸块与所述金属层之间的所述电连接支持10A的电流。
6.根据权利要求1所述的半导体结构，其进一步包括：
与所述金属层相邻的衬底的第一侧。
7.根据权利要求6所述的半导体结构，其中所述衬底包括功率晶体管。
8.根据权利要求1所述的半导体结构，其进一步包括：
设置在所述多个RDL柱之间的第一聚酰亚胺层，所述第一聚酰亚胺层在所述RDL平台与所述金属层之间；以及
所述第一聚酰亚胺层上方的第二聚酰亚胺层。
9.根据权利要求1所述的半导体结构，其中所述RDL平台和所述多个RDL柱包括铜。
10.根据权利要求1所述的半导体结构，其中所述多个RDL柱中的柱具有圆形横截面。
11.根据权利要求1所述的半导体结构，其中所述RDL平台具有圆形横截面。
12.根据权利要求1所述的半导体结构，其中所述多个RDL柱中的第一柱与所述多个RDL柱中的第二柱之间的距离大于所述焊料凸块的宽度。
13.一种半导体结构，其包括：
重布线层RDL结构，其包括：
RDL平台；
支撑所述RDL平台的多个RDL柱；
第一聚酰亚胺层，其位于所述多个RDL柱之间并且在所述RDL平台的第一侧上；以及
所述RDL平台的第二侧上的第二聚酰亚胺层，所述RDL平台的所述第二侧与所述RDL平台的所述第一侧相对。
14.根据权利要求13所述的半导体结构，其中所述第一聚酰亚胺层邻近所述多个RDL柱。
15.根据权利要求13所述的半导体结构，其进一步包括与所述第一聚酰亚胺层相邻的钝化层。
16.根据权利要求13所述的半导体结构，其中所述多个RDL柱是至少四个柱。
17.一种形成半导体结构的方法，所述方法包括：
在晶片上沉积金属层；
在所述金属层上形成聚酰亚胺层；
在所述聚酰亚胺层中形成柱开口；以及
在所述柱开口中和所述聚酰亚胺层的一部分上沉积重布线层RDL，其中所述聚酰亚胺层设置在所述金属层与所述RDL之间。
18.根据权利要求17所述的方法，其中所述聚酰亚胺层是第一聚酰亚胺层，所述方法进一步包括：
在所述RDL上形成第二聚酰亚胺层；
在所述第二聚酰亚胺层中形成开口；
在所述第二聚酰亚胺层的所述开口中和所述第二聚酰亚胺层的一部分上沉积凸块下金属UBM层；以及
在所述UBM上形成焊料凸块。
19.根据权利要求17所述的方法，其进一步包括：
在所述金属层上沉积钝化层，其中形成所述聚酰亚胺层包括在所述钝化层上沉积所述聚酰亚胺层；以及
在所述钝化层中形成柱开口。
20.根据权利要求17所述的方法，其进一步包括：
对所述晶片的背面进行背面研磨，其中沉积所述金属层包括在所述晶片的正面上沉积正面金属层；以及
在所述晶片的所述背面上沉积背面金属层。
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