CN112073065A - Novel millimeter wave sub-sampling DDS (direct digital synthesizer) mixing decimal frequency division phase-locked loop structure - Google Patents

Novel millimeter wave sub-sampling DDS (direct digital synthesizer) mixing decimal frequency division phase-locked loop structure Download PDF

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CN112073065A
CN112073065A CN202010807251.6A CN202010807251A CN112073065A CN 112073065 A CN112073065 A CN 112073065A CN 202010807251 A CN202010807251 A CN 202010807251A CN 112073065 A CN112073065 A CN 112073065A
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CN112073065B (en
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刘马良
肖金海
朱樟明
杨银堂
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Xidian University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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Abstract

The invention discloses a novel millimeter wave sub-sampling DDS (direct digital synthesizer) mixing fractional frequency division phase-locked loop structure, which comprises: the circuit comprises a buffer, a first sub-sampling phase detector PD1, a second sub-sampling phase detector PD2, a DDS, a DAC, a multiplier, a voltage-current conversion circuit, a low-pass filter, a first inverter chain F1, a second inverter chain F2, a frequency divider and a voltage-controlled oscillator. The invention carries out frequency mixing after sampling and outputting, greatly reduces the needed DDS output frequency, reduces the power consumption and simultaneously can achieve good linearity and low power consumption. The invention is characterized in that the high resolution characteristic of the DDS output signal frequency is not influenced by the phase-locked loop, the phase-locked loop enables the frequency synthesizer to jump in a wider frequency range by minimum frequency stepping, and the DDS provides the capability of jumping in a narrower frequency range by very small frequency stepping. Therefore, the broadband frequency conversion speed depends on the loop locking time of the phase-locked loop, and the narrowband frequency conversion speed after the loop locking depends on the frequency conversion time of the DDS.

Description

Novel millimeter wave sub-sampling DDS (direct digital synthesizer) mixing decimal frequency division phase-locked loop structure
Technical Field
The invention belongs to the technical field of analog-digital hybrid integrated circuits, and particularly relates to a novel millimeter wave sub-sampling DDS (direct digital synthesizer) mixing decimal frequency division phase-locked loop structure.
Background
A Phase Locked Loop (PLL) is a Phase Locked Loop (PLL) which is a typical feedback control circuit. It uses the reference signal input from outside to control the frequency and phase of the oscillation signal in the loop. The automatic tracking of the output signal frequency to the input signal frequency is realized, and the automatic tracking method is generally used for a closed-loop tracking circuit. With the development of 5G, the frequency and phase noise requirements of the phase-locked loop become higher and higher. Poor spurs and phase noise can cause spectral aliasing of adjacent channel signals, reducing the signal-to-noise ratio. The spurs in the conventional phase frequency and phase detection charge pump phase locked loop mainly come from the mismatch of charge and discharge currents of the charge pump.
Referring to fig. 1, fig. 1 is a schematic circuit diagram of a typical Phase-locked loop provided in the prior art, and main blocks of the Phase-locked loop of fig. 1 include a Phase Detector (PD), a low-pass filter of a loop, and a Voltage-Controlled Oscillator (VCO). The phase detector has two input signals, a reference signal and an output signal of the voltage controlled oscillator. The phase discriminator converts the phase difference signal of the reference signal and the output signal into a voltage signal, and sends the voltage signal to a low-pass filter, and the low-pass filter filters out high-frequency clutter to obtain a control signal of the voltage-controlled oscillator. Therefore, the output signal of the phase-locked loop is continuously compared with the reference signal after frequency division, and then the oscillation frequency of the voltage-controlled oscillator is changed until the frequencies of the two signals are the same, so that the phase-locked loop enters a locked state. In the locked state, the output of the voltage-controlled oscillator changes due to external interference and the like and is timely fed back to the control voltage of the voltage-controlled oscillator for timely correction, and finally a stable output signal is obtained.
DDS (Direct Digital Synthesis, Direct Digital frequency synthesizer) has many advantages such as high resolution, high speed, fast frequency conversion, continuous phase change, etc. However, the frequency of the synthesized signal is low, the index of the broadband spurious-free dynamic range is not good, and the indirect frequency synthesis technology taking the phase-locked loop circuit as the core has the characteristics of high frequency of the synthesized signal and the characteristic that the signal phase noise is the synthesis of phase noise of a phase-discriminated signal and phase noise of a VCO signal, but is inferior to the DDS in the indexes of frequency resolution, frequency conversion speed and the like. More importantly, the independent use of the indirect frequency synthesis scheme often fails to give consideration to important performance indexes such as high frequency resolution, low phase noise, low spurious, frequency agility and the like. The DDS + PLL scheme combines direct digital frequency synthesis and indirect frequency synthesis, and can achieve the effect which is difficult to achieve by using DDS or phase-locked loop technology alone.
In a conventional phase locked loop, fractional division is performed. There are TDC (time to Digital converter) structures, delta-sigma structures, and the like. The TDC structure utilizes the effect of phase accumulation, so that the sampling clock can realize the phase accumulation to achieve the effect of decimal sampling, but the minimum resolution precision of the structure is influenced by the process, and phase errors are easily introduced in the phase accumulation process. The Delta-sigma structure utilizes the frequency divider to generate the output with different integer frequency division ratios in a certain period to achieve the effect that the average output is fractional frequency division, and the output frequency linearity of the scheme is poor and the frequency precision is low. The traditional mixer scheme mixes at the output of the VCO and requires a very high DDS output frequency with large power consumption.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a novel millimeter wave sub-sampling DDS frequency mixing fractional frequency division phase-locked loop structure. The technical problem to be solved by the invention is realized by the following technical scheme:
a novel millimeter wave sub-sampling DDS mixing fractional frequency division phase-locked loop structure, comprising: a buffer, a first sub-sampling phase detector PD1, a second sub-sampling phase detector PD2, a DDS, a DAC, a multiplier, a voltage-to-current conversion circuit, a low-pass filter, a first inverter chain F1, a second inverter chain F2, a frequency divider, and a voltage-controlled oscillator, wherein,
the first output end and the second output end of the buffer are respectively connected with the first input end and the second input end of the DDS, the first output end and the second output end of the buffer are also respectively connected with the first input end and the second input end of the first sub-sampling phase detector PD1, and the first output end and the second output end of the buffer are also respectively connected with the first input end and the second input end of the second sub-sampling phase detector PD 2;
the first output end and the second output end of the DDS are respectively connected with the first input end and the second input end of the DAC, the first output end, the second output end, the third output end and the fourth output end of the DAC are respectively connected with the multiplier, and the first output end and the second output end of the first sub-sampling phase detector PD1 and the first output end and the second output end of the second sub-sampling phase detector PD2 are respectively connected with the multiplier;
the first output end and the second output end of the multiplier are connected with the voltage-current conversion circuit, the output end of the voltage-current conversion circuit is connected to the voltage-controlled oscillator through the low-pass filter, the first output end of the voltage-controlled oscillator is connected to the first input end of the frequency divider through the first inverter chain F1, the second output end of the voltage-controlled oscillator is connected to the second input end of the frequency divider through the second inverter chain F2, the first output end and the second output end of the frequency divider are both connected to the control end of the first sub-sampling phase discriminator PD1, and the third output end and the fourth output end of the frequency divider are both connected to the control end of the second sub-sampling phase discriminator PD 2.
In one embodiment of the present invention, the first sub-sampling phase detector PD1 includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a capacitor C3, and a capacitor C4, wherein,
a first output terminal of the buffer is connected to the source of the transistor M1 and the source of the transistor M4, a second output terminal of the buffer is connected to the source of the transistor M3 and the source of the transistor M5, a drain of the transistor M1 is connected to the drain of the transistor M3 and the source of the transistor M2, a drain of the transistor M5 is connected to the drain of the transistor M4 and the source of the transistor M6, a drain of the transistor M2 is connected to the first terminal of the capacitor C3 and the multiplier, a second terminal of the capacitor C3 is connected to the ground, a source of the transistor M2 is further connected to the drain of the transistor M2, a gate of the transistor M3 and a gate of the transistor M4 are connected to the ground, a drain of the transistor M6 is connected to the first terminal of the capacitor C4 and the multiplier, and a second terminal of the capacitor C4 is connected to the ground, the source of the transistor M6 is further connected to the drain of the transistor M6, the gate of the transistor M1 and the gate of the transistor M5 are connected to the first output terminal of the frequency divider, and the gate of the transistor M2 and the gate of the transistor M6 are connected to the second output terminal of the frequency divider.
In one embodiment of the present invention, the size of the transistor M2 and the transistor M6 is half of the size of the transistor M1 and the transistor M5, and the size of the transistor M3 and the transistor M4 are the same as the size of the transistor M1 and the transistor M5.
In one embodiment of the present invention, the second sub-sampling phase detector PD2 includes a transistor M7, a transistor M8, a transistor M9, a transistor M10, a transistor M11, a transistor M12, a capacitor C5, and a capacitor C6, wherein,
a first output terminal of the buffer is connected to the source of the transistor M7 and the source of the transistor M10, a second output terminal of the buffer is connected to the source of the transistor M9 and the source of the transistor M11, a drain of the transistor M7 is connected to the drain of the transistor M9 and the source of the transistor M8, a drain of the transistor M11 is connected to the drain of the transistor M10 and the source of the transistor M12, a drain of the transistor M8 is connected to the first terminal of the capacitor C5 and the multiplier, a second terminal of the capacitor C5 is connected to the ground, a source of the transistor M8 is further connected to the drain of the transistor M8, a gate of the transistor M9 and a gate of the transistor M10 are connected to the ground, a drain of the transistor M12 is connected to the first terminal of the capacitor C6 and the multiplier, and a second terminal of the capacitor C6 is connected to the ground, the source of the transistor M12 is further connected to the drain of the transistor M12, the gate of the transistor M7 and the gate of the transistor M11 are connected to the third output terminal of the frequency divider, and the gate of the transistor M8 and the gate of the transistor M12 are connected to the fourth output terminal of the frequency divider.
In one embodiment of the present invention, the size of the transistor M8 and the transistor M12 is half of the size of the transistor M7 and the transistor M11, and the size of the transistor M9 and the transistor M10 are the same as the size of the transistor M7 and the transistor M11.
In one embodiment of the present invention, the multiplier includes a transistor M13, a transistor M14, a transistor M15, a transistor M16, a transistor M17, a transistor M18, a transistor M19, a transistor M20, a transistor M21, a transistor M22, a transistor M23, a transistor M24, a capacitor C7, a capacitor C8, a resistor R2, and a resistor R3, wherein,
the gate of the transistor M13 and the gate of the transistor M17 are connected to the first output terminal of the DAC, the gate of the transistor M14 and the gate of the transistor M16 are connected to the second output terminal of the DAC, the gates of the transistor M15 and the transistor M18 are connected to the first sub-sampling phase detector PD1, the source of the transistor M13 is connected to the source of the transistor M14 and the drain of the transistor M15, the drain of the transistor M13 is connected to the first end of the capacitor C7 and the first end of the resistor R2, the drain of the transistor M14 is connected to the first end of the capacitor C8 and the first end of the resistor R3, the source of the transistor M15 is connected to the ground, the source of the transistor M16 is connected to the source of the transistor M17 and the drain of the transistor M18, the drain of the transistor M16 is connected to the first end of the capacitor C7 and the first end of the resistor R2, the drain of the transistor M17 is connected to the first end of the capacitor C8 and the first end of the resistor R3, and the source of the transistor M18 is grounded;
the gate of the transistor M19 and the gate of the transistor M23 are connected to the third output terminal of the DAC, the gate of the transistor M20 and the gate of the transistor M22 are connected to the fourth output terminal of the DAC, the gates of the transistor M21 and the transistor M24 are connected to the second sub-sampling phase detector PD2, the source of the transistor M19 is connected to the source of the transistor M20 and the drain of the transistor M21, the drain of the transistor M19 is connected to the first end of the capacitor C7 and the first end of the resistor R2, the drain of the transistor M20 is connected to the first end of the capacitor C8 and the first end of the resistor R3, the source of the transistor M21 is connected to the ground, the source of the transistor M22 is connected to the source of the transistor M23 and the drain of the transistor M24, the drain of the transistor M22 is connected to the first end of the capacitor C7 and the first end of the resistor R2, the drain of the transistor M23 is connected to the first end of the capacitor C8 and the first end of the resistor R3, and the source of the transistor M24 is grounded;
the second end of the capacitor C7 and the second end of the capacitor C8 are connected to a ground terminal, the second end of the resistor R2 and the second end of the resistor R3 are connected to a power supply terminal, the first end of the capacitor C7 and the first end of the resistor R2 are further connected to a first input terminal of the voltage-current conversion circuit, and the first end of the capacitor C8 and the first end of the resistor R3 are further connected to a second input terminal of the voltage-current conversion circuit.
In one embodiment of the present invention, the voltage-current conversion circuit includes a transistor M25, a transistor M26, a transistor M27, a transistor M28, a transistor M29, a transistor M30, a transistor M31, a transistor M32, and a transistor M33, wherein,
a first output terminal of the multiplier is connected to the gate of the transistor M25, a second output terminal of the multiplier is connected to the gate of the transistor M26, a source of the transistor M25 is connected to the source of the transistor M26 and the drain of the transistor M27, a drain of the transistor M25 is connected to the drain of the transistor M28, the gate of the transistor M28, and the gate of the transistor M31, a drain of the transistor M26 is connected to the drain of the transistor M29, the gate of the transistor M29, and the gate of the transistor M30, a gate of the transistor M27 is connected to a bias voltage terminal, a source of the transistor M27 is connected to a ground terminal, a drain of the transistor M30 is connected to the drain of the transistor M32, the gate of the transistor M32, and the gate of the transistor M33, a drain of the transistor M31 is connected to the drain of the transistor M33 and the low pass filter, the source of the transistor M32 and the source of the transistor M33 are connected to a ground terminal, and the transistor M28, the transistor M29, the transistor M30, and the transistor M31 are connected to a power supply terminal.
In one embodiment of the invention, the low pass filter comprises a resistor R1, a capacitor C1, and a capacitor C2, wherein,
the first end of the resistor R1 and the first end of the capacitor C2 are connected to the output end of the voltage-current conversion circuit and the input end of the voltage-controlled oscillator, the second end of the resistor R1 is connected to the first end of the capacitor C1, and the second end of the capacitor C1 and the second end of the capacitor C2 are connected to the ground.
In one embodiment of the invention, the voltage-controlled oscillator comprises a transistor M33, a transistor M34, a transistor M35, a transistor M36, an inductor L and an adjustable capacitor CA1An adjustable capacitor CA2And a capacitor array, wherein,
the output end of the voltage-current conversion circuit is connected with the adjustable capacitor CA1First terminal of, said adjustable capacitance CA2The first terminal of (1), the adjustable capacitor CA1Is connected to the drain of the transistor M33, the first terminal of the inductor L, the gate of the transistor M34, the first terminal of the capacitor array, the drain of the transistor M35, the gate of the transistor M36, the first inverter chain F1, the adjustable capacitor CA2The second terminal of the second inverter chain F2 is connected to the drain of the transistor M34, the second terminal of the inductor L, the gate of the transistor M33, the second terminal of the capacitor array, the drain of the transistor M36, the gate of the transistor M35, and the source of the transistor M33 and the source of the transistor M34 are connected to a power supply terminal through a constant current source, and the source of the transistor M35 and the source of the transistor M36 are connected to a ground terminal.
The invention has the beneficial effects that:
the invention carries out frequency mixing after sampling and outputting, greatly reduces the needed DDS output frequency, reduces the power consumption and simultaneously can achieve good linearity and low power consumption. The invention is characterized in that the high resolution characteristic of the DDS output signal frequency is not influenced by the phase-locked loop, the phase-locked loop enables the frequency synthesizer to jump in a wider frequency range by minimum frequency stepping, and the DDS provides the capability of jumping in a narrower frequency range by very small frequency stepping. Therefore, the broadband frequency conversion speed depends on the loop locking time of the phase-locked loop, and the narrowband frequency conversion speed after the loop locking depends on the frequency conversion time of the DDS. The difficulty of the invention lies in the filtering processing of the output signal of the in-loop mixer, so in order to achieve better filtering effect, the invention utilizes the IQ modulation mode to greatly filter the high frequency component in the frequency component output by the multiplier.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic circuit diagram of a typical phase-locked loop provided in the prior art;
fig. 2 is a schematic circuit structure diagram of a novel millimeter wave sub-sampling DDS mixing fractional-n phase-locked loop structure according to an embodiment of the present invention;
fig. 3 is a schematic circuit structure diagram of a first sub-sampling phase detector according to an embodiment of the present invention;
fig. 4 is a schematic circuit structure diagram of a second sub-sampling phase detector according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a DAC circuit according to an embodiment of the present invention;
fig. 6 is a schematic circuit diagram of a multiplier according to an embodiment of the present invention;
fig. 7 is a schematic circuit diagram of a voltage-to-current conversion circuit according to an embodiment of the present invention;
fig. 8 is a schematic circuit diagram of a low-pass filter according to an embodiment of the present invention;
fig. 9 is a schematic circuit diagram of a voltage controlled oscillator according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 2, fig. 2 is a schematic circuit structure diagram of a novel millimeter wave sub-sampling DDS mixing fractional-n phase-locked loop structure according to an embodiment of the present invention. This embodiment provides a novel millimeter wave sub-sampling DDS mixing decimal frequency division phase-locked loop structure, and this phase-locked loop structure includes: a buffer (i.e., buffer), a first sub-sampling phase detector PD1, a second sub-sampling phase detector PD2, a DDS (direct digital synthesizer), a DAC (digital to analog converter), a multiplier (i.e., MIX), a voltage-to-current conversion circuit (i.e., V/I), a low pass filter, a first inverter chain F1, a second inverter chain F2, a frequency divider (i.e.,/N), and a voltage controlled oscillator (i.e., VCO), wherein,
the first output end and the second output end of the buffer are respectively connected with the first input end and the second input end of the DDS, the first output end and the second output end of the buffer are also respectively connected with the first input end and the second input end of the first sub-sampling phase discriminator PD1, and the first output end and the second output end of the buffer are also respectively connected with the first input end and the second input end of the second sub-sampling phase discriminator PD 2; the first output end and the second output end of the DDS are respectively connected with the first input end and the second input end of the DAC, the first output end, the second output end, the third output end and the fourth output end of the DAC are respectively connected with the multiplier, and the first output end and the second output end of the first sub-sampling phase discriminator PD1 and the first output end and the second output end of the second sub-sampling phase discriminator PD2 are respectively connected with the multiplier; the first output end and the second output end of the multiplier are connected with a voltage-current conversion circuit, the output end of the voltage-current conversion circuit is connected to a voltage-controlled oscillator through a low-pass filter, the first output end of the voltage-controlled oscillator is connected to the first input end of the frequency divider through a first inverter chain F1, the second output end of the voltage-controlled oscillator is connected to the second input end of the frequency divider through a second inverter chain F2, the first output end and the second output end of the frequency divider are both connected to the control end of the first sub-sampling phase detector PD1, and the third output end and the fourth output end of the frequency divider are both connected to the control end of the second sub-sampling phase detector PD 2.
According to the novel phase-locked loop structure provided by the embodiment, an output signal of the voltage-controlled oscillator outputs IQ two-path differential sampling clock signals after frequency division, then samples a reference signal, outputs two paths of IQ differential difference frequency output signals, mixes the two paths of IQ difference frequency signals with IQ differential signals generated by a DDS, and finally controls the voltage-controlled oscillator through a charge pump (namely, a voltage-current conversion circuit) and a low-pass filter to form a phase-locked loop. For example, when the output frequency of the voltage-controlled oscillator is 18GHz, two IQ signals with 140.625MHz frequency are generated by the difference after frequency division by 128, a reference signal with 150MHz is sampled, and a difference frequency signal with 9.375MHz is output. The DDS/DAC generates a signal with the frequency of 9.375MHz through a reference signal of 150MHz to be mixed with the sampling output signal, and finally the voltage-controlled oscillator is controlled through a charge pump and a low-pass filter. Therefore, the whole phase-locked loop outputs an 18GHz output signal by using a 150MHz reference clock, and the effect of fractional frequency division is achieved.
In an embodiment, referring to fig. 3, fig. 3 is a schematic circuit structure diagram of a first sub-sampling phase detector according to an embodiment of the present invention, as can be seen from fig. 3, the first sub-sampling phase detector PD1 includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a capacitor C3, and a capacitor C4, wherein a first output terminal of a buffer is connected to a source of the transistor M1 and a source of the transistor M4, a second output terminal of the buffer is connected to a source of the transistor M3 and a source of the transistor M5, a drain of the transistor M1 is connected to a drain of the transistor M3 and a source of the transistor M2, a drain of the transistor M5 is connected to a drain of the transistor M4 and a source of the transistor M6, a drain of the transistor M2 is connected to a first terminal of the capacitor C3 and a multiplier, a second terminal of the capacitor C3 is connected to a ground, a source of the transistor M8653, the gate of the transistor M3 and the gate of the transistor M4 are connected to a ground terminal, the drain of the transistor M6 is connected to the first terminal of the capacitor C4 and the multiplier, the second terminal of the capacitor C4 is connected to the ground terminal, the source of the transistor M6 is also connected to the drain of the transistor M6, the gate of the transistor M1 and the gate of the transistor M5 are connected to the first output terminal of the frequency divider, and the gate of the transistor M2 and the gate of the transistor M6 are connected to the second output terminal of the frequency divider.
Further, the transistor M1, the transistor M2, the transistor M3, the transistor M4, the transistor M5, and the transistor M6 are all NMOS.
Further, the sizes of the transistor M2 and the transistor M6 are half of the sizes of the transistor M1 and the transistor M5, and the sizes of the transistor M3 and the transistor M4 are the same as the sizes of the transistor M1 and the transistor M5.
In this embodiment, CLK _ NI and CLK _ PI are a pair of differential signals, and when CLK _ NI is low, the first sub-sampling phase detector PD1 enters the sampling phase. When CLK NI is high, the first sub-sampling phase detector PD1 enters the hold phase. All transistors in the first sub-sampling phase detector PD1 are N-type. The transistor M1 and the transistor M5 are a pair of switching tubes, and are connected to the VIN _ PI and VIN _ NI ports, respectively. When the switching tube is switched from an on state to an off state, inversion layer charges flow out through the source and the drain, which is called channel charge injection. In order to prevent the direct injection of charges onto the sampling capacitor from further changing the voltage value on the sampling capacitor, the present embodiment introduces the transistor M2 and the transistor M6 as the channel charge collection. The transistor M2 and the transistor M6 are half the size of the transistor M1 and the transistor M5, the control signal is complementary to the transistor M1 and the transistor M5, and the source and the drain of the transistor M2 and the transistor M6 are both shorted. Thus, when the transistor M1 and the transistor M5 are turned off, the transistor M2 and the transistor M6 are turned on, and inversion layers formed in the transistor M2 and the transistor M6 can accommodate the channel charge flowing out. Transistor M2 and transistor M6 may also suppress clock feedthrough. When the transistors M1 and M5 are turned off, VIN _ NI and VIN _ PI may be coupled to the sampling capacitor through the source-drain capacitance, which causes the sampling value to be unstable, so that the transistors M3 and M4 are introduced, the gates of the transistors M3 and M4 are grounded, the sizes of the transistors M3 and M4 are the same as the sizes of the transistors M1 and M5, and therefore the source-drain capacitance is also the same as the switch transistor. Therefore, when the first sub-sampling phase detector PD1 enters the hold phase, the two differential signals are coupled to the sources of the transistor M2 and the transistor M6 through the source-drain capacitances with the same size, so that the equivalent capacitances of the drains of the transistor M1 and the transistor M3 are close to 0, and the influences cancel each other out.
In an embodiment, referring to fig. 4, fig. 4 is a schematic circuit structure diagram of a second sub-sampling phase detector according to an embodiment of the present invention, as can be seen from fig. 4, the second sub-sampling phase detector PD2 includes a transistor M7, a transistor M8, a transistor M9, a transistor M10, a transistor M11, a transistor M12, a capacitor C5, and a capacitor C6, wherein a first output terminal of a buffer is connected to a source of the transistor M7 and a source of the transistor M10, a second output terminal of the buffer is connected to a source of the transistor M9 and a source of the transistor M11, a drain of the transistor M7 is connected to a drain of the transistor M9 and a source of the transistor M8, a drain of the transistor M11 is connected to a drain of the transistor M10 and a source of the transistor M12, a drain of the transistor M8 is connected to a first terminal of the capacitor C5 and a multiplier, a second terminal of the capacitor C5 is connected to a ground, a source of the transistor M8653, the gate of the transistor M9 and the gate of the transistor M10 are connected to a ground terminal, the drain of the transistor M12 is connected to the first terminal of the capacitor C6 and the multiplier, the second terminal of the capacitor C6 is connected to the ground terminal, the source of the transistor M12 is also connected to the drain of the transistor M12, the gate of the transistor M7 and the gate of the transistor M11 are connected to the third output terminal of the frequency divider, and the gate of the transistor M8 and the gate of the transistor M12 are connected to the fourth output terminal of the frequency divider.
Further, the transistor M7, the transistor M8, the transistor M9, the transistor M10, the transistor M11, and the transistor M12 are all NMOS.
Further, the sizes of the transistor M8 and the transistor M12 are half of the sizes of the transistor M7 and the transistor M11, and the sizes of the transistor M9 and the transistor M10 are the same as the sizes of the transistor M7 and the transistor M11.
In this embodiment, CLK _ NQ and CLK _ PQ are a pair of differential signals, and the second sub-sampling phase detector PD2 enters the sampling phase when CLK _ NQ is low. When CLK _ NQ is high, the second sub-sampling phase detector PD2 enters the hold phase. All transistors in the second sub-sampling phase detector PD2 are N-type. The transistor M7 and the transistor M11 are a pair of switching tubes, and are connected to the VIN _ PQ and VIN _ NQ ports, respectively. When the switching tube is switched from an on state to an off state, inversion layer charges flow out through the source and the drain, which is called channel charge injection. In order to prevent the direct injection of charges onto the sampling capacitor from further changing the voltage value on the sampling capacitor, the present embodiment introduces the transistor M8 and the transistor M12 as the channel charge collection. The transistor M8 and the transistor M12 are half the size of the transistor M7 and the transistor M11, the control signal is complementary to the transistor M7 and the transistor M11, and the source and the drain of the transistor M8 and the transistor M12 are both shorted. Thus, when the transistor M7 and the transistor M11 are turned off, the transistor M8 and the transistor M12 are turned on, and inversion layers formed in the transistor M8 and the transistor M12 can accommodate the channel charge flowing out. Transistor M8 and transistor M12 may also suppress clock feedthrough. When the transistor M7 and the transistor M11 are turned off, VIN _ NQ and VIN _ PQ may be coupled to the sampling capacitor through source-drain capacitance to cause unstable sampling values, so that the transistor M9 and the transistor M10 are introduced, the gates of the transistor M9 and the transistor M10 are grounded, the sizes of the transistor M9 and the transistor M10 are the same as those of the transistor M7 and the transistor M11, and therefore the source-drain capacitance is also the same as that of the switch tube. Therefore, when the second sub-sampling phase detector PD2 enters the hold phase, the two differential signals are coupled to the sources of the transistor M8 and the transistor M12 through the source-drain capacitances with the same size, so that the equivalent capacitances of the drains of the transistor M7 and the transistor M9 are close to 0, and the influences are cancelled out.
Please refer to fig. 5, fig. 5 is a schematic diagram of a DAC circuit according to an embodiment of the present invention, fig. 5 is a 10-bit SAR DAC, the DDS generates IQ differential digital control signals DDS _ NI [0:9], DDS _ NQ [0:9], DDS _ PI [0:9] and DDS _ PQ [0:9], and controls the reference voltage value of the capacitor array in the DAC to be grounded or Vref (reference voltage), so that the DAC outputs two IQ differential sine wave signals, and the SAR DAC has better power consumption performance compared to a current-type DAC.
In a specific embodiment, referring to fig. 6, fig. 6 is a schematic circuit structure diagram of a multiplier according to an embodiment of the present invention, as can be seen from fig. 6, the multiplier includes a transistor M13, a transistor M14, a transistor M15, a transistor M16, a transistor M17, a transistor M18, a transistor M19, a transistor M20, a transistor M21, a transistor M22, a capacitor C22, a capacitor R22, and a resistor R22, where a gate of the transistor M22 and a gate of the transistor M22 are connected to a first end of a capacitor C22 of a first sub-sampling phase detector PD 22, a source of the transistor M22 is connected to the source of the transistor M22 and the drain of the transistor M22, and a drain of the capacitor C22 is connected to a first end of the transistor M22 and a drain of the transistor M22 are connected to a first end of the capacitor C22 of the transistor M22, A first end of the resistor R2, a drain of the transistor M14 is connected with a first end of the capacitor C8 and a first end of the resistor R3, a source of the transistor M15 is connected with a ground terminal, a source of the transistor M16 is connected with a source of the transistor M17 and a drain of the transistor M18, a drain of the transistor M16 is connected with a first end of the capacitor C7 and a first end of the resistor R2, a drain of the transistor M17 is connected with a first end of the capacitor C8 and a first end of the resistor R3, and a source of the transistor M18 is grounded; the gate of the transistor M19 and the gate of the transistor M23 are connected to the third output terminal of the DAC, the gate of the transistor M20 and the gate of the transistor M22 are connected to the fourth output terminal of the DAC, the gate of the transistor M21 and the gate of the transistor M24 are connected to the first terminal of the capacitor C5 and the first terminal of the capacitor C6 of the second sub-sampling phase detector PD2, the source of the transistor M19 is connected to the source of the transistor M20 and the drain of the transistor M21, the drain of the transistor M19 is connected to the first terminal of the capacitor C7 and the first terminal of the resistor R2, the drain of the transistor M20 is connected to the first terminal of the capacitor C8, a first end of the resistor R3, a source of the transistor M21 is connected with a ground terminal, a source of the transistor M22 is connected with a source of the transistor M23 and a drain of the transistor M24, a drain of the transistor M22 is connected with a first end of the capacitor C7 and a first end of the resistor R2, a drain of the transistor M23 is connected with a first end of the capacitor C8 and a first end of the resistor R3, and a source of the transistor M24 is grounded; the second end of the capacitor C7 and the second end of the capacitor C8 are connected to a ground terminal, the second end of the resistor R2 and the second end of the resistor R3 are connected to a power supply terminal, the first end of the capacitor C7 and the first end of the resistor R2 are further connected to a first input terminal of the voltage-current conversion circuit, and the first end of the capacitor C8 and the first end of the resistor R3 are further connected to a second input terminal of the voltage-current conversion circuit.
Further, the transistor M13, the transistor M14, the transistor M15, the transistor M16, the transistor M17, the transistor M18, the transistor M19, the transistor M20, the transistor M21, the transistor M22, the transistor M23, and the transistor M24 are all NMOS.
In this embodiment, the IQ differential pair signal generated by the DDS is multiplied by the difference IQ signal output by the sampling circuit, and a frequency difference signal between the IQ differential signal of the DDS and the difference IQ signal output by the sampling circuit is output. Due to the IQ structure, the frequency component of the output signal of the multiplier only contains the frequency difference signal of the IQ differential signal generated by the DDS and the difference frequency IQ signal output by the sampling circuit, and other harmonic components are suppressed. For better harmonic rejection, the frequency difference between the output of the divider and the reference frequency should be increased appropriately. In order to obtain a purer difference frequency signal, output resistors R2 and R3 of the multiplier, C7 and C8 form a low-pass filter to further filter high-frequency noise.
In an embodiment, referring to fig. 7, fig. 7 is a schematic circuit structure diagram of a voltage-to-current conversion circuit according to an embodiment of the present invention, as can be seen from fig. 7, the voltage-to-current conversion circuit includes a transistor M25, a transistor M26, a transistor M27, a transistor M28, a transistor M29, a transistor M30, a transistor M31, a transistor M32, and a transistor M33, wherein a first output terminal of a multiplier is connected to a gate of a transistor M25, that is, a first terminal of a capacitor C7 and a first terminal of a resistor R2 are connected to a gate of a transistor M25, a second output terminal of the multiplier is connected to a gate of a transistor M26, that is, a first terminal of a capacitor C8 and a first terminal of a resistor R3 are connected to a gate of a transistor M26, a source of a transistor M25 is connected to a source of a transistor M26 and a drain of a transistor M9, a drain of a transistor M25 is connected to a drain of a transistor M82, the drain of the transistor M26 is connected to the drain of the transistor M29, the gate of the transistor M29 and the gate of the transistor M30, and the gate of the transistor M27 is connected to the bias voltage terminal VBIASThe source of the transistor M27 is connected to the ground, the drain of the transistor M30 is connected to the drain of the transistor M32, the gate of the transistor M32, and the gate of the transistor M33, the drain of the transistor M31 is connected to the drain of the transistor M33 and the low-pass filter, the source of the transistor M32 and the source of the transistor M33 are connected to the ground, and the transistors M28, M29, M30, and M31 are connected to the power supply terminals.
Further, the transistor M25, the transistor M26, the transistor M27, the transistor M32, and the transistor M33 are NMOS, and the transistor M28, the transistor M29, the transistor M30, and the transistor M31 are PMOS.
In an embodiment, referring to fig. 8, fig. 8 is a schematic circuit structure diagram of a low-pass filter according to an embodiment of the present invention, where the low-pass filter includes a resistor R1, a capacitor C1, and a capacitor C2, where a first end of the resistor R1 and a first end of the capacitor C2 are connected to an output terminal of the voltage-to-current conversion circuit and an input terminal of the voltage-controlled oscillator, that is, a first end of the resistor R1 and a first end of the capacitor C2 are connected to the drains of the transistor M31 and the transistor M33, a first end of the resistor R1 and a first end of the capacitor C2 are further connected to an input terminal of the voltage-controlled oscillator, a second end of the resistor R1 is connected to a first end of the capacitor C1, and a second end of the capacitor C1 and.
In this embodiment, a folding operational amplifier is used as the voltage-current conversion circuit, and in order to achieve higher gain and reduce phase noise, the phase detectors (i.e., the first sub-sampling phase detector PD1 and the second sub-sampling phase detector PD2) introduce a pre-amplification part, which amplifies the input signal and converts the amplified signal into a current signal through the voltage-current conversion circuit. In order to achieve better output swing, only one PMOS and one NMOS (i.e. transistor M31, transistor M33) are used to form the output of the voltage-current conversion circuit. The pull-up current and the pull-down current of a voltage current conversion circuit of the sub-sampling phase-locked loop are determined by the amplitude of the sampling voltage, so the currents are equal to each other, and the problem of current mismatching existing in the phase frequency and phase detection phase-locked loop does not exist.
The sampled signal contains the phase information of the output signal, and the capacitor is charged after the phase information is processed by the voltage-current conversion circuit. The load of the voltage-to-current conversion circuit is equivalent to a low-pass filter. In order to filter the spurious, a low-pass filter is introduced, and due to the introduction of the low-pass filter, a pole is introduced into the system, which easily causes the phase margin of the phase-locked loop to be insufficient, thereby causing the system to be unstable. So in order to increase the phase margin of the phase locked loop a resistor R1 is introduced, thereby introducing a zero. In order to avoid the jump of the output voltage, a capacitor C2 is introduced to filter out the interference generated by the voltage jump.
In an embodiment, referring to fig. 9, fig. 9 is a schematic circuit structure diagram of a voltage controlled oscillator according to an embodiment of the present invention, where the voltage controlled oscillator includes a transistor M33, a transistor M34, a transistor M35, a transistor M36, an inductor L, and an adjustable capacitor CA1An adjustable capacitor CA2A capacitor array, wherein the output end of the voltage-current conversion circuit is connected with an adjustable capacitor CA1First terminal of (1), adjustable capacitance CA2First terminal of (1), i.e. adjustable capacitor CA1First terminal of (1), adjustable capacitance CA2Is connected to the drain of the transistor M31, the drain of the transistor M33, the first terminal of the resistor R1, the first terminal of the capacitor C2, the adjustable capacitor CA1Is connected to the drain of the transistor M33, the first terminal of the inductor L, the gate of the transistor M34, the first terminal of the capacitor array, the drain of the transistor M35, the gate of the transistor M36, the first inverter chain F1, the adjustable capacitor CA2The second terminal of the transistor M34 is connected to the drain of the transistor M34, the second terminal of the inductor L, the gate of the transistor M33, the second terminal of the capacitor array, the drain of the transistor M36, the gate of the transistor M35, and the second inverter chain F2, the source of the transistor M33 and the source of the transistor M34 are connected to a power supply terminal through a constant current source, and the source of the transistor M35 and the source of the transistor M36 are connected to the ground terminal.
Further, the transistors M33 and M34 are PMOS, and the transistors M35 and M36 are NMOS.
In the embodiment, the voltage-controlled oscillator adopts an LC oscillator with complementary NMOS and PMOS, and the structure can provide lower phase noise. The LC oscillator can obtain a very high oscillation frequency range by changing the capacitance value of the capacitor. According to the formula of the oscillation frequency:
Figure BDA0002629587010000171
LC oscillator by regulating voltage VtuneThe adjustable capacitance C can be changedA1And an adjustable capacitor CA2Thereby changing the output frequency of the LC oscillator. In order to obtain a sufficiently wide output frequency range, the LC oscillator uses four capacitor module groups of different sizesA capacitor array formed by four capacitor modules with different sizes, namely CDIG[0:3]Wherein the ratio of the capacitance values of the four capacitance modules is 1: 2: 4: each capacitor module consists of two capacitors and a switch between the two capacitors, and the four switches of the four capacitor modules are respectively T0、T1、T2、T3Thus by controlling the switch T0-T3Controlling the oscillation frequency, T, of the LC oscillator by switching in or out0、T1、T2、T3When the capacitance is high, the capacitance is connected into a loop, the capacitance value of the LC oscillator is increased, and the oscillation frequency is reduced; t is0、T1、T2、T3When the voltage is low, the capacitor is disconnected from the loop, the capacitance value of the circuit is increased, and the frequency is increased. The combination of four different capacitive modules can produce a superposition, resulting in 24And (4) frequency bands.
In order to stably and normally work at the frequency of more than ten GHz and achieve the effect of fractional frequency division, the invention samples a reference signal by using a feedback signal to output a difference frequency signal, and then mixes the sampled signal with a low-frequency signal generated by a DDS (direct digital synthesizer), and finally achieves the effect of fractional frequency division.
Compared with the traditional scheme of mixing on the VCO output, the phase-locked loop structure has the advantages that the frequency of the DDS/DAC output is low, the required reference frequency is low, and the SAR type DAC used can save most of the power consumption of the DAC.
The sampling circuit and the DAC circuit of the invention adopt IQ output, thereby greatly reducing the stray of the frequency mixer and leading the whole phase-locked loop to have lower stray performance.
In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description of the specification, reference to the description of the term "one embodiment", "some embodiments", "an example", "a specific example", or "some examples", etc., means that a particular feature or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (9)

1. The utility model provides a novel millimeter wave sub-sampling DDS mixing decimal frequency division phase-locked loop structure which characterized in that includes: a buffer, a first sub-sampling phase detector PD1, a second sub-sampling phase detector PD2, a DDS, a DAC, a multiplier, a voltage-to-current conversion circuit, a low-pass filter, a first inverter chain F1, a second inverter chain F2, a frequency divider, and a voltage-controlled oscillator, wherein,
the first output end and the second output end of the buffer are respectively connected with the first input end and the second input end of the DDS, the first output end and the second output end of the buffer are also respectively connected with the first input end and the second input end of the first sub-sampling phase detector PD1, and the first output end and the second output end of the buffer are also respectively connected with the first input end and the second input end of the second sub-sampling phase detector PD 2;
the first output end and the second output end of the DDS are respectively connected with the first input end and the second input end of the DAC, the first output end, the second output end, the third output end and the fourth output end of the DAC are respectively connected with the multiplier, and the first output end and the second output end of the first sub-sampling phase detector PD1 and the first output end and the second output end of the second sub-sampling phase detector PD2 are respectively connected with the multiplier;
the first output end and the second output end of the multiplier are connected with the voltage-current conversion circuit, the output end of the voltage-current conversion circuit is connected to the voltage-controlled oscillator through the low-pass filter, the first output end of the voltage-controlled oscillator is connected to the first input end of the frequency divider through the first inverter chain F1, the second output end of the voltage-controlled oscillator is connected to the second input end of the frequency divider through the second inverter chain F2, the first output end and the second output end of the frequency divider are both connected to the control end of the first sub-sampling phase discriminator PD1, and the third output end and the fourth output end of the frequency divider are both connected to the control end of the second sub-sampling phase discriminator PD 2.
2. The phase-locked loop structure of claim 1, wherein the first sub-sampling phase detector PD1 comprises a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a capacitor C3, and a capacitor C4, wherein,
a first output terminal of the buffer is connected to the source of the transistor M1 and the source of the transistor M4, a second output terminal of the buffer is connected to the source of the transistor M3 and the source of the transistor M5, a drain of the transistor M1 is connected to the drain of the transistor M3 and the source of the transistor M2, a drain of the transistor M5 is connected to the drain of the transistor M4 and the source of the transistor M6, a drain of the transistor M2 is connected to the first terminal of the capacitor C3 and the multiplier, a second terminal of the capacitor C3 is connected to the ground, a source of the transistor M2 is further connected to the drain of the transistor M2, a gate of the transistor M3 and a gate of the transistor M4 are connected to the ground, a drain of the transistor M6 is connected to the first terminal of the capacitor C4 and the multiplier, and a second terminal of the capacitor C4 is connected to the ground, the source of the transistor M6 is further connected to the drain of the transistor M6, the gate of the transistor M1 and the gate of the transistor M5 are connected to the first output terminal of the frequency divider, and the gate of the transistor M2 and the gate of the transistor M6 are connected to the second output terminal of the frequency divider.
3. The phase-locked loop structure of claim 2, wherein the transistor M2 and the transistor M6 are half the size of the transistor M1 and the transistor M5, and the transistor M3 and the transistor M4 are the same size as the transistor M1 and the transistor M5.
4. The phase-locked loop structure of claim 1, wherein the second sub-sampling phase detector PD2 comprises a transistor M7, a transistor M8, a transistor M9, a transistor M10, a transistor M11, a transistor M12, a capacitor C5, and a capacitor C6, wherein,
a first output terminal of the buffer is connected to the source of the transistor M7 and the source of the transistor M10, a second output terminal of the buffer is connected to the source of the transistor M9 and the source of the transistor M11, a drain of the transistor M7 is connected to the drain of the transistor M9 and the source of the transistor M8, a drain of the transistor M11 is connected to the drain of the transistor M10 and the source of the transistor M12, a drain of the transistor M8 is connected to the first terminal of the capacitor C5 and the multiplier, a second terminal of the capacitor C5 is connected to the ground, a source of the transistor M8 is further connected to the drain of the transistor M8, a gate of the transistor M9 and a gate of the transistor M10 are connected to the ground, a drain of the transistor M12 is connected to the first terminal of the capacitor C6 and the multiplier, and a second terminal of the capacitor C6 is connected to the ground, the source of the transistor M12 is further connected to the drain of the transistor M12, the gate of the transistor M7 and the gate of the transistor M11 are connected to the third output terminal of the frequency divider, and the gate of the transistor M8 and the gate of the transistor M12 are connected to the fourth output terminal of the frequency divider.
5. The phase-locked loop structure of claim 4 wherein the size of the transistor M8 and the transistor M12 is half that of the transistor M7 and the transistor M11, and the size of the transistor M9 and the transistor M10 are the same as the size of the transistor M7 and the transistor M11.
6. The phase-locked loop structure of claim 1, wherein the multiplier comprises a transistor M13, a transistor M14, a transistor M15, a transistor M16, a transistor M17, a transistor M18, a transistor M19, a transistor M20, a transistor M21, a transistor M22, a transistor M23, a transistor M24, a capacitor C7, a capacitor C8, a resistor R2, and a resistor R3, wherein,
the gate of the transistor M13 and the gate of the transistor M17 are connected to the first output terminal of the DAC, the gate of the transistor M14 and the gate of the transistor M16 are connected to the second output terminal of the DAC, the gates of the transistor M15 and the transistor M18 are connected to the first sub-sampling phase detector PD1, the source of the transistor M13 is connected to the source of the transistor M14 and the drain of the transistor M15, the drain of the transistor M13 is connected to the first end of the capacitor C7 and the first end of the resistor R2, the drain of the transistor M14 is connected to the first end of the capacitor C8 and the first end of the resistor R3, the source of the transistor M15 is connected to the ground, the source of the transistor M16 is connected to the source of the transistor M17 and the drain of the transistor M18, the drain of the transistor M16 is connected to the first end of the capacitor C7 and the first end of the resistor R2, the drain of the transistor M17 is connected to the first end of the capacitor C8 and the first end of the resistor R3, and the source of the transistor M18 is grounded;
the gate of the transistor M19 and the gate of the transistor M23 are connected to the third output terminal of the DAC, the gate of the transistor M20 and the gate of the transistor M22 are connected to the fourth output terminal of the DAC, the gates of the transistor M21 and the transistor M24 are connected to the second sub-sampling phase detector PD2, the source of the transistor M19 is connected to the source of the transistor M20 and the drain of the transistor M21, the drain of the transistor M19 is connected to the first end of the capacitor C7 and the first end of the resistor R2, the drain of the transistor M20 is connected to the first end of the capacitor C8 and the first end of the resistor R3, the source of the transistor M21 is connected to the ground, the source of the transistor M22 is connected to the source of the transistor M23 and the drain of the transistor M24, the drain of the transistor M22 is connected to the first end of the capacitor C7 and the first end of the resistor R2, the drain of the transistor M23 is connected to the first end of the capacitor C8 and the first end of the resistor R3, and the source of the transistor M24 is grounded;
the second end of the capacitor C7 and the second end of the capacitor C8 are connected to a ground terminal, the second end of the resistor R2 and the second end of the resistor R3 are connected to a power supply terminal, the first end of the capacitor C7 and the first end of the resistor R2 are further connected to a first input terminal of the voltage-current conversion circuit, and the first end of the capacitor C8 and the first end of the resistor R3 are further connected to a second input terminal of the voltage-current conversion circuit.
7. The phase-locked loop structure of claim 1, wherein the voltage-to-current conversion circuit comprises a transistor M25, a transistor M26, a transistor M27, a transistor M28, a transistor M29, a transistor M30, a transistor M31, a transistor M32, and a transistor M33, wherein,
a first output terminal of the multiplier is connected to the gate of the transistor M25, a second output terminal of the multiplier is connected to the gate of the transistor M26, a source of the transistor M25 is connected to the source of the transistor M26 and the drain of the transistor M27, a drain of the transistor M25 is connected to the drain of the transistor M28, the gate of the transistor M28, and the gate of the transistor M31, a drain of the transistor M26 is connected to the drain of the transistor M29, the gate of the transistor M29, and the gate of the transistor M30, a gate of the transistor M27 is connected to a bias voltage terminal, a source of the transistor M27 is connected to a ground terminal, a drain of the transistor M30 is connected to the drain of the transistor M32, the gate of the transistor M32, and the gate of the transistor M33, a drain of the transistor M31 is connected to the drain of the transistor M33 and the low pass filter, the source of the transistor M32 and the source of the transistor M33 are connected to a ground terminal, and the transistor M28, the transistor M29, the transistor M30, and the transistor M31 are connected to a power supply terminal.
8. The phase-locked loop structure of claim 1, wherein the low-pass filter comprises a resistor R1, a capacitor C1, and a capacitor C2, wherein,
the first end of the resistor R1 and the first end of the capacitor C2 are connected to the output end of the voltage-current conversion circuit and the input end of the voltage-controlled oscillator, the second end of the resistor R1 is connected to the first end of the capacitor C1, and the second end of the capacitor C1 and the second end of the capacitor C2 are connected to the ground.
9. The phase-locked loop structure of claim 1, wherein the voltage-controlled oscillator comprises a transistor M33, a transistor M34, a transistor M35, a transistor M36, an inductor L, and an adjustable capacitor CA1An adjustable capacitor CA2And a capacitor array, wherein,
the output end of the voltage-current conversion circuit is connected with the adjustable capacitor CA1First terminal of, said adjustable capacitance CA2The first terminal of (1), the adjustable capacitor CA1Is connected to the drain of the transistor M33, the first terminal of the inductor L, the gate of the transistor M34, the first terminal of the capacitor array, the drain of the transistor M35, the gate of the transistor M36, the first inverter chain F1, the adjustable capacitor CA2The second terminal of the second inverter chain F2 is connected to the drain of the transistor M34, the second terminal of the inductor L, the gate of the transistor M33, the second terminal of the capacitor array, the drain of the transistor M36, the gate of the transistor M35, and the source of the transistor M33 and the source of the transistor M34 are connected to a power supply terminal through a constant current source, and the source of the transistor M35 and the source of the transistor M36 are connected to a ground terminal.
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