CN212435673U - Phase-locked loop circuit and calibration circuit and chip thereof - Google Patents
Phase-locked loop circuit and calibration circuit and chip thereof Download PDFInfo
- Publication number
- CN212435673U CN212435673U CN202021260515.2U CN202021260515U CN212435673U CN 212435673 U CN212435673 U CN 212435673U CN 202021260515 U CN202021260515 U CN 202021260515U CN 212435673 U CN212435673 U CN 212435673U
- Authority
- CN
- China
- Prior art keywords
- circuit
- filter
- band
- phase
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000003379 elimination reaction Methods 0.000 claims abstract description 38
- 230000008030 elimination Effects 0.000 claims abstract description 37
- 230000005669 field effect Effects 0.000 claims description 24
- 238000001914 filtration Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 15
- 230000010355 oscillation Effects 0.000 description 10
- 238000012546 transfer Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000003786 synthesis reaction Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The utility model provides a phase-locked loop circuit and calibration circuit and chip thereof, phase-locked loop circuit includes phase frequency detector, charge pump, filter circuit, voltage controlled oscillator and loop frequency divider that the head and the tail links to each other in proper order, wherein, filter circuit includes interconnect's low pass filter and band elimination filter. Which can reduce the reference spurs of the phase locked loop.
Description
Technical Field
The utility model relates to a phase-locked loop technique relevant with integrated circuit, concretely relates to phase-locked loop circuit and calibration circuit and chip thereof.
Background
The English full name of PLL is Phase Locked Loop, Chinese name "Phase Locked Loop". The phase-locked loop has wide application in clock recovery, frequency synthesis and other aspects. There are many structures of PLL, one of the widely used architectures in integrated circuits is CCPLL (Charge-Pump PLL), and as shown in fig. 1, the basic function of CPPLL is frequency multiplication (or called frequency synthesis): the input signal is a clock signal with fixed frequency, called reference clock; the output of which is another clock signal, the output clock frequency and the input frequency being satisfied
Where N is a division factor determined by the loop divider.
The CPPLL comprises the components: PFD (phase-frequency-detector), CP (charge-pump), LPF (low-pass-filter), VCO (voltage-controlled-oscillator), Loop Divider, each of which functions as follows:
the PFD is responsible for comparing the phase/frequency difference of the input clock and the feedback clock and outputting a series of pulses which are in linear relation with the phase/frequency error;
the CP receives the pulse trains output by the PFD, converts the pulse trains into corresponding current pulse signals according to the 'lead-lag' relation of the pulse trains, and sends the corresponding current pulse signals to a rear LPF module;
the LPF is used for filtering high-frequency components in the current pulse transmitted by the CP and only keeping low-frequency information;
the VCO takes the voltage filtered by the LPF as a control signal to control the VCO to output a clock with corresponding frequency;
the Loop Divider is responsible for dividing the frequency of the clock output by the VCO by a factor N, where N may be an integer or a fraction.
In brief, the CPPLL is a feedback system for "phase", and converts the change of input phase to output according to a set parameter, and the differential of phase to time is frequency, so that the frequency multiplication function is finally realized.
One of the problems with CPPLLs is the so-called "reference spurs", fig. 2 shows a simplified version of the circuit schematic and operating waveform of "PFD + CP + LPF": a is a reference clock, B is a feedback clock, and is a pulse signal output by the PFD, and the pulse signal acts on the switch S1,S2Controlling the current I1And source current I2On or off, current flowing to capacitor CPAbove, the control voltage of the VCO is formed. As can be seen from this process, the phase comparison of the PFD is performed according to the period of the reference clock, which causes a periodic ripple in the control voltage of the VCO, especially considering the mismatch of these components of the PFD/CP, the non-ideal (e.g., leakage) of the LPF capacitance, and so on, which further aggravates the ripple characteristic of the VCO voltage.
The VCO is a voltage controlled oscillator, and the change of the control voltage is reflected on the oscillation frequency, so that the frequency of the output clock changes periodically, which is called a reference spur, and a glitch appears at the frequency offset of the reference clock from the phase power spectral density of the output clock. This glitch results in a poor purity of the output clock, for example in radio frequency communication applications, the glitch of the LO-PLL may cause reciprocal mixing, affecting the reception quality of the RX.
SUMMERY OF THE UTILITY MODEL
In view of the above-mentioned reference spur problem, an object of the present invention is to provide a pll circuit and its calibration circuit and chip, which can reduce the reference spur of the pll.
The above purpose is achieved by the following scheme:
in a first aspect, the utility model provides a phase-locked loop circuit, phase-locked loop circuit includes phase frequency detector, charge pump, filter circuit, voltage controlled oscillator and loop frequency divider that the head and the tail links to each other in proper order, wherein, filter circuit includes interconnect's low pass filter and band elimination filter.
Specifically, the low-pass filter is a second-order RC filter.
Specifically, the band-stop filter is a double-T type filter.
Specifically, the band-stop filter is embedded in the low-pass filter.
The second aspect, the utility model provides an above-mentioned filter circuit's calibration circuit, including the amplifier subassembly and the microprocessor that connect gradually, wherein, RC oscillating circuit is constituteed with band elimination filter to the amplifier subassembly, and microprocessor gathers the frequency signal of RC oscillating circuit output, and the contrast with reference frequency, and calibrates according to the contrast result band elimination filter.
Specifically, the amplifier assembly comprises a first voltage-dividing resistor, a second voltage-dividing resistor, an amplifier and a feedback resistor, wherein,
one end of the first voltage-dividing resistor is connected with the bias voltage, and the other end of the first voltage-dividing resistor is respectively connected with the non-inverting input end of the amplifier and the second voltage-dividing resistor;
the inverting input end of the amplifier is connected with the input end of the band elimination filter, and the output end of the amplifier is connected with the output end of the band elimination filter and is connected to the non-inverting input end through the feedback resistor.
Specifically, the amplifier comprises an operational amplifier circuit and an AGC circuit, wherein the operational amplifier circuit comprises a first-stage operational amplifier circuit and a second-stage operational amplifier circuit which are connected with each other, and the AGC circuit is coupled to the second-stage operational amplifier circuit.
Specifically, the AGC circuit includes a first field effect transistor and a second field effect transistor, wherein,
the grid electrode of the first field effect transistor is connected with the output end of the second-stage operational amplifier circuit, the source electrode of the first field effect transistor is connected with the input end of the second-stage operational amplifier circuit, and the drain electrode of the first field effect transistor is connected with bias voltage;
the grid electrode of the second field effect transistor is connected with the output end of the second-stage operational amplifier circuit, the source electrode of the second field effect transistor is connected with the input end of the second-stage operational amplifier circuit, and the drain electrode of the second field effect transistor is grounded.
Specifically, the calibrating the band elimination filter according to the comparison result specifically includes adjusting a resistance value of the band elimination filter according to the comparison result.
Specifically, the calibration circuit further comprises a comparator, the amplifier assembly is connected with the microprocessor through the comparator, the input end of the comparator is connected with the output end of the amplifier assembly, and the output end of the comparator is connected with the microprocessor.
Specifically, the input end and the output end of the band elimination filter are respectively connected with the calibration circuit through switches.
Specifically, the input end and the output end of the band elimination filter are respectively connected with the charge pump and the voltage-controlled oscillator through the switch.
In a third aspect, the present invention provides an integrated circuit chip including the above-mentioned phase-locked loop circuit and calibration circuit.
The utility model discloses the phase-locked loop circuit that the first aspect provided has added band elimination filter in traditional LPF, has changed original LPF transfer function, and then has changed PLL loop characteristic, under the prerequisite that keeps output frequency stability, has attenuated the periodic oscillation of CP electric current, has reduced the PLL and has consulted spuriously.
Additionally the utility model discloses the calibration circuit that the second aspect provided, circuit implementation means is simple and convenient, based on two T shape band elimination filter's original structure, combine to constitute RC oscillating circuit with the amplifier subassembly, gather the oscillation frequency of comparator output through microprocessor, contrast reference frequency calibrates with adjustment band elimination filter resistance element resistance to automatic gain control has been introduced at amplifier subassembly inside, phase-locked loop oscillation frequency's accurate calibration has been realized.
Drawings
Fig. 1 is a schematic diagram of a CCPLL circuit architecture in the prior art.
FIG. 2 is a schematic circuit diagram of a PFD + CP + LPF in a prior art CCPLL.
Fig. 3 is a schematic diagram of a phase-locked loop circuit architecture according to the present invention.
Fig. 4 is a specific circuit diagram of the low-pass filter provided by the present invention.
Fig. 5 is a specific circuit diagram of the band-stop filter provided by the present invention.
Fig. 6 is a schematic diagram of a position relationship between the low-pass filter and the band-stop filter provided by the present invention.
Fig. 7A is a schematic diagram showing another positional relationship between the low-pass filter and the band-stop filter.
Fig. 7B is a schematic diagram showing another positional relationship between the low-pass filter and the band-stop filter.
Fig. 8 is a schematic diagram of a calibration circuit architecture provided by the present invention.
Fig. 9 is a specific circuit diagram of the calibration circuit provided by the present invention.
Fig. 10 is a further detailed circuit diagram of the calibration circuit provided by the present invention.
Fig. 11 is a specific circuit diagram of an amplifier in the calibration circuit according to the present invention.
Fig. 12 is a schematic diagram of a connection relationship between the calibration circuit and the pll filter circuit provided in the present invention.
Detailed Description
The technical solutions of the present invention will be described in detail and fully with reference to the accompanying drawings, in which, obviously, the described embodiments are only a part, not all, of the present invention. Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the utility model discloses, all other implementation means that technical personnel obtained under the prerequisite of not making creative work in the field all belong to the scope of the utility model protection.
The spurious problem of reference to current phase-locked loop exists, the utility model provides a reduce phase-locked loop and refer to spurious filter circuit, it is shown with reference to figure 3, phase-locked loop circuit includes phase frequency detector, charge pump, filter circuit, voltage controlled oscillator and loop frequency divider that the head and the tail links to each other in proper order, wherein, filter circuit includes interconnect's low pass filter and band elimination filter.
In an alternative embodiment, the low-pass filter is a second-order RC filter, in particular a second-order passive RC filter, as shown in fig. 4, the low-pass filter includes RZ、CZ、CP、RP3、CP3Wherein R isZAnd CZForm a first-order RC filter, RP3And CP3Constituting a second order RC filter.
In an alternative embodiment, the band-stop filter is a double-T type filter, as shown in FIG. 5, the band-stop filter includes R1、R2、R3、C1、C2、C3The double-T filter is formed by connecting an RC low-pass filter and an RC high-pass filter in parallel, the double-T filter is a common filter for filtering specific frequency signals in the field of electronic circuits, and a person skilled in the art can easily obtain the double-T filter from the prior art, and the utility model discloses do not specifically introduce here in addition.
In an alternative embodiment, the band-stop filter is embedded in the low-pass filter, and as shown in fig. 6, the band-stop filter is disposed between the first-order RC filter and the second-order RC filter of the low-pass filter. The utility model discloses at the inside band elimination filter that has added of current low pass filter, aim at according to band elimination filter's specific frequency attenuation characteristic, to consulting spurious problem, band elimination filter in filter circuit and low pass filter between the position relation do not influence the utility model discloses the mesh, the utility model discloses do not limit to this, can have multiple similar means of realizing on this basis, arrange in before the band elimination filter shown in fig. 7A low pass filter, or arrange in behind the band elimination filter shown in fig. 7B low pass filter, so on.
In the above embodiment, the values of the devices of the low-pass filter and the band-stop filter need to satisfy the following relationship:
on the premise that the above relationship is satisfied, the transfer function of the band-stop filter itself can be expressed as:
wherein,
Vinis the output signal amplitude of the band elimination filter;
Voutis the input signal amplitude of the band-stop filter;
j is a twiddle factor;
omega is the angular frequency of the band-stop filter;
Q＝1/4＝0.25。
from the above transfer function, the resistance-capacitance network with the double-T structure has the band-stop characteristic and can be regarded as a band-stop filter.
Under different values of omega, the amplitude-frequency characteristic of the band-elimination filter is as follows:
as can be seen from the above formula, let ω ben＝refWherein ω isref＝2πfref，ωrefFor the angular frequency of the phase-locked loop reference clock, frefThe frequency of the clock is referenced so that the band-stop filter can attenuate the cycle jitter of the previous charge pump current.
After the band-stop filter is added into the low-pass filter, the original filter transfer function can be changed, and then the loop characteristics of the phase-locked loop are changed.
Regarding the values of the components of the filter circuit, as an optional specific implementation means, the R of the original low-pass filter is keptZ、CZ、CP、RP3、CP3The value is unchanged, so that the R of the band elimination filter is ensured1＝R2＝R3、C1＝C2＝C32, and R1+R2+RP3,new＝RP3、
After the value-taking constraint condition is met, although the transfer function of the filter circuit is changed, the influence of the frequency band below the loop bandwidth frequency of the phase-locked loop is small and acceptable, and the phase-locked loop can still ensure the original stability.
In another aspect of the present invention, in the integrated circuit, the resistor and the capacitor may deviate from the design value due to the process fluctuation, and then the center frequency ω of the band elimination filter is causednThe offset occurs, affecting the filtering effect. Therefore, to this problem, the utility model provides a calibration circuit based on above-mentioned filter circuit, it is shown with reference to fig. 8, this calibration circuit is including the amplifier subassembly and the microprocessor that connect gradually, wherein, the RC oscillating circuit is constituteed with band elimination filter to the amplifier subassembly, and microprocessor gathers that RC oscillating circuit is defeatedAnd comparing the output frequency signal with a reference frequency, and calibrating the band elimination filter according to a comparison result.
The reference frequency is a known accurate oscillation frequency and is provided by a clock source of the microprocessor.
In an optional embodiment, the amplifier component includes a first voltage-dividing resistor, a second voltage-dividing resistor, an amplifier, and a feedback resistor, where one end of the first voltage-dividing resistor is connected to the bias voltage, and the other end of the first voltage-dividing resistor is connected to the non-inverting input terminal of the amplifier and the second voltage-dividing resistor, respectively; the inverting input end of the amplifier is connected with the input end of the band elimination filter, and the output end of the amplifier is connected with the output end of the band elimination filter and is connected to the non-inverting input end through the feedback resistor.
Referring to fig. 9, which shows a specific circuit diagram of the above embodiment, the calibration circuit includes a band-stop filter indicated by a dotted box at the upper part of the diagram and an amplifier component indicated by a dotted box at the lower part, the amplifier component and the band-stop filter form an oscillator, and the theoretical oscillation frequency is
The amplifier output is collected by a microprocessor (not shown), the oscillation frequency is identified and compared to a reference frequency, and the filter circuit is calibrated based on the comparison.
In the calibration circuit shown in fig. 9, the first divider resistor Rdiv1, the second divider resistor Rdiv2 and the feedback resistor Rfb form positive feedback of the amplifier amp, the band elimination filter forms negative feedback of the amplifier amp, the negative feedback is stronger than the positive feedback at low frequency and high frequency, the positive feedback is stronger than the negative feedback at the band elimination frequency of the band elimination filter, the phase shift of the feedback network crosses to 0 °, the barkhausen criterion is satisfied, and the circuit starts to vibrate.
Further, as an example, the resistor R of the band elimination filter in the filter circuit described above1、R2、R3The utility model discloses in preferably adjustable resistor to and, the aforesaid is specifically do according to the comparison result calibration filter circuit, according to the comparison result, adjusts band elimination filter's resistance value.
Further, as another oneExample, the capacitor C of the band-stop filter in the filter circuit1、C2、C3The utility model discloses in preferably adjustable electric capacity to and, the aforesaid is specifically do according to the comparison result calibration filter circuit, according to the comparison result, adjusts band elimination filter's electric capacity appearance value.
As a further optional implementation means of the foregoing embodiment, referring to fig. 10, the calibration circuit further includes a comparator, the amplifier module is connected to the microprocessor through the comparator, an input terminal of the comparator is connected to an output terminal of the amplifier module, and an output terminal of the comparator is connected to the microprocessor. The output waveform of the amplifier is shaped by the comparator, so that the microprocessor can conveniently identify and calculate.
The utility model discloses the practical application of the above-mentioned calibration circuit finds that the oscillator composed of the amplifier assembly and the band elimination filter has the actual frequency and the theoretical frequency
There is a certain difference, and the source of this difference lies in the non-linearity of the circuit. Therefore, in the present invention, AGC (automatic Gain Control) is further introduced into the amplifier module. In an alternative embodiment, the amplifier comprises an operational amplifier circuit and an AGC circuit, the operational amplifier circuit is a conventional general-purpose two-stage operational amplifier circuit and comprises a first-stage operational amplifier circuit and a second-stage operational amplifier circuit which are connected with each other, and the AGC circuit is coupled to the second-stage operational amplifier circuit.
In the above alternative embodiment, referring to fig. 11, the AGC circuit includes a first field effect transistor and a second field effect transistor, wherein a gate of the first field effect transistor is connected to an output terminal of the second stage operational amplifier circuit, a source of the first field effect transistor is connected to an input terminal of the second stage operational amplifier circuit, and a drain of the first field effect transistor is connected to the bias voltage; the grid electrode of the second field effect transistor is connected with the output end of the second-stage operational amplifier circuit, the source electrode of the second field effect transistor is connected with the input end of the second-stage operational amplifier circuit, and the drain electrode of the second field effect transistor is grounded.
The amplifier circuit described above is at the quiescent operating point, pg node and V shown in FIG. 11outThe voltages of the nodes are relatively close, M1And M2Are all not conductive, amp isThe common operational amplifier has very high gain, the circuit starts oscillation, and the pg node and the V node are connected at the momentoutThe node changes inversely. When V isoutIncrease and decrease pg, and when reaching a certain degree, M1Turn on, pull up the pg node, thereby enabling VoutChanging from the high point downward; when V isoutDecrease, increase of pg, to a certain extent, M2Turning on and pulling down the pg node, thereby enabling VoutChanging from a low point upwards. Thus, the AGC function is completed.
In an optional embodiment, the input end and the output end of the band-stop filter are respectively connected with the calibration circuit through switches; similarly, the input end and the output end of the band-stop filter are respectively connected with the charge pump and the voltage-controlled oscillator through the switch. Referring to fig. 12, the band-stop filters are respectively passed through switches Sw1And Sw2Connected to charge pump and voltage-controlled oscillator, and via switch Sw3And Sw4Connected with the calibration circuit.
In the above-described embodiment, the switch Sw performs calibration of the band-stop filter1And Sw2Open, switch Sw3And Sw4When the band elimination filter is closed, the band elimination filter is connected into the calibration circuit, and after the oscillation frequency output by the calibration circuit is identified by the microprocessor, the resistor R is adjusted1、R2、R3The oscillation frequency is made to approach the reference frequency.
Furthermore, the utility model also provides an integrated circuit chip, this integrated circuit chip has integrateed above-mentioned filter circuit and calibration circuit thereof.
While there have been shown and described and pointed out fundamental novel features of the invention as applied to a preferred embodiment thereof, it will be understood that various omissions and substitutions and changes in the form and details of the devices and methods described may be made by those skilled in the art without departing from the spirit of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A phase-locked loop circuit is characterized by comprising a phase frequency detector, a charge pump, a filter circuit, a voltage-controlled oscillator and a loop frequency divider which are sequentially connected end to end, wherein the filter circuit comprises a low-pass filter and a band-stop filter which are mutually connected.
2. The phase-locked loop circuit of claim 1, wherein the low-pass filter is a second-order RC filter and the band-stop filter is a double-T filter.
3. The phase-locked loop circuit of claim 2, wherein the band-reject filter is disposed between first-order and second-order RC filtering of the low-pass filter.
4. A calibration circuit for calibrating a phase-locked loop circuit according to any one of claims 1 to 3, comprising an amplifier module and a microprocessor connected in series, wherein the amplifier module and the band-stop filter form an RC oscillating circuit, and the microprocessor acquires a frequency signal output from the RC oscillating circuit, compares the frequency signal with a reference frequency, and calibrates the band-stop filter according to the comparison result.
5. The calibration circuit of claim 4, wherein the amplifier component comprises a first voltage-dividing resistor, a second voltage-dividing resistor, an amplifier, and a feedback resistor, wherein,
one end of the first voltage-dividing resistor is connected with the bias voltage, and the other end of the first voltage-dividing resistor is respectively connected with the non-inverting input end of the amplifier and the second voltage-dividing resistor;
the inverting input end of the amplifier is connected with the input end of the band elimination filter, and the output end of the amplifier is connected with the output end of the band elimination filter and is connected to the non-inverting input end through the feedback resistor.
6. The calibration circuit of claim 5, wherein the amplifier comprises an operational amplifier circuit comprising a first stage operational amplifier circuit and a second stage operational amplifier circuit connected to one another, and an AGC circuit coupled to the second stage operational amplifier circuit.
7. The calibration circuit of claim 6, wherein the AGC circuit includes a first field effect transistor and a second field effect transistor, wherein,
the grid electrode of the first field effect transistor is connected with the output end of the second-stage operational amplifier circuit, the source electrode of the first field effect transistor is connected with the input end of the second-stage operational amplifier circuit, and the drain electrode of the first field effect transistor is connected with bias voltage;
the grid electrode of the second field effect transistor is connected with the output end of the second-stage operational amplifier circuit, the source electrode of the second field effect transistor is connected with the input end of the second-stage operational amplifier circuit, and the drain electrode of the second field effect transistor is grounded.
8. Calibration circuit according to any of claims 4 to 7, wherein the calibration of the band-stop filter according to the comparison result is performed by adjusting a resistance value or/and a capacitance value of the band-stop filter according to the comparison result.
9. The calibration circuit of any of claims 4-7, wherein the input and output of the band-stop filter are connected to the calibration circuit by a switch, respectively, and the input and output of the band-stop filter are connected to a charge pump, a voltage controlled oscillator, respectively, by a switch.
10. A chip comprising a phase locked loop circuit as claimed in any one of claims 1 to 3 and a calibration circuit as claimed in any one of claims 4 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021260515.2U CN212435673U (en) | 2020-07-01 | 2020-07-01 | Phase-locked loop circuit and calibration circuit and chip thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021260515.2U CN212435673U (en) | 2020-07-01 | 2020-07-01 | Phase-locked loop circuit and calibration circuit and chip thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212435673U true CN212435673U (en) | 2021-01-29 |
Family
ID=74278047
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021260515.2U Active CN212435673U (en) | 2020-07-01 | 2020-07-01 | Phase-locked loop circuit and calibration circuit and chip thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN212435673U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113726332A (en) * | 2021-08-18 | 2021-11-30 | 上海聆芯科技有限公司 | Phase-locked loop circuit reference spurious elimination method, phase-locked loop circuit reference spurious elimination device and phase-locked loop system |
| CN114006603A (en) * | 2021-11-02 | 2022-02-01 | 哈尔滨工业大学 | Reconfigurable N-path type filter |
| CN118590059A (en) * | 2024-08-02 | 2024-09-03 | 厦门意行半导体科技有限公司 | PLL frequency synthesizer |
-
2020
- 2020-07-01 CN CN202021260515.2U patent/CN212435673U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113726332A (en) * | 2021-08-18 | 2021-11-30 | 上海聆芯科技有限公司 | Phase-locked loop circuit reference spurious elimination method, phase-locked loop circuit reference spurious elimination device and phase-locked loop system |
| CN113726332B (en) * | 2021-08-18 | 2023-07-07 | 上海聆芯科技有限公司 | Phase-locked loop circuit reference spurious elimination method, elimination device and phase-locked loop system |
| CN114006603A (en) * | 2021-11-02 | 2022-02-01 | 哈尔滨工业大学 | Reconfigurable N-path type filter |
| CN114006603B (en) * | 2021-11-02 | 2022-05-03 | 哈尔滨工业大学 | Reconfigurable N-path type filter |
| CN118590059A (en) * | 2024-08-02 | 2024-09-03 | 厦门意行半导体科技有限公司 | PLL frequency synthesizer |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN212435673U (en) | Phase-locked loop circuit and calibration circuit and chip thereof | |
| US7298221B2 (en) | Phase-locked loop circuits with current mode loop filters | |
| US11201625B2 (en) | Phase locked loop | |
| US7180364B2 (en) | Filter apparatus including slave gm-C filter with frequency characteristics automatically tuned by master circuit | |
| US7420427B2 (en) | Phase-locked loop with a digital calibration loop and an analog calibration loop | |
| US7863972B2 (en) | Self-calibration of continuous-time filters and systems comprising such filters | |
| US7719365B2 (en) | Method and apparatus for reducing silicon area of a phase lock loop (PLL) filter without a noise penalty | |
| US20060267698A1 (en) | Filter calibration | |
| US20240146311A1 (en) | High Gain Detector Techniques for Low Bandwidth Low Noise Phase-Locked Loops | |
| EP2425533A1 (en) | Supply-regulated phase-locked loop (pll) and method of using | |
| WO2001026230A1 (en) | Pll loop filter with switched-capacitor resistor | |
| CN110572150B (en) | Clock generation circuit and clock generation method | |
| US20060139109A1 (en) | PLL-based frequency synthesizer | |
| CN101414784A (en) | Charge pump | |
| US20050046487A1 (en) | Calibrating a loop-filter of a phase locked loop | |
| WO2006128075A1 (en) | Filter calibration | |
| CN114499512A (en) | Double-loop phase-locked loop | |
| WO2023184575A1 (en) | Loop filter for phase-locked loop and phase-locked loop | |
| CN201550100U (en) | Frequency synthesis system based on varactor diode | |
| CN101917176B (en) | Cut-off frequency self-tuning method and circuit for filter | |
| US6919759B2 (en) | Digitally controlled tuner circuit | |
| CN101557208B (en) | Adjusting circuit, integrated circuit applying the same and signal filtering method | |
| CN112073065B (en) | Millimeter wave sub-sampling DDS (direct digital synthesizer) mixing decimal frequency division phase-locked loop structure | |
| CN221886459U (en) | Passive loop filter and phase-locked loop circuit | |
| DiClemente et al. | An area-efficient CMOS current-mode phase-locked loop |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |