CN112071256B - Grid scanning driving circuit - Google Patents
Grid scanning driving circuit Download PDFInfo
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- CN112071256B CN112071256B CN202011047052.6A CN202011047052A CN112071256B CN 112071256 B CN112071256 B CN 112071256B CN 202011047052 A CN202011047052 A CN 202011047052A CN 112071256 B CN112071256 B CN 112071256B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention provides a grid scanning driving circuit, which comprises an N-level grid driving circuit unit; the nth stage gate driving circuit unit comprises a pull-up control module, a pull-down maintaining module, a pull-up module, an emptying reset module and a bootstrap capacitor, wherein the pull-up control module, the pull-down maintaining module, the pull-up module and the bootstrap capacitor are connected to a pull-up control node of the present stage, the pull-down maintaining module and the emptying reset module are connected to the control node of the present stage, and the pull-down maintaining module, the pull-up module and the touch maintaining module output a gate scanning signal of the present stage. According to the grid scanning driving circuit, the fifth thin film transistor and the sixth thin film transistor are additionally arranged, so that the panel can be reduced in a high-temperature high-humidity deterioration environment, the risk that the fourth thin film transistor generates drift is solved, the influence of a limited manufacturing process of the circuit can be reduced, the manufacturing process difficulty of a factory is reduced, and the competitiveness of the panel in the market is improved.
Description
Technical Field
The invention belongs to the technical field of display panels, and particularly relates to a grid scanning driving circuit.
Background
In recent years, the gate scan driving circuit has become a common integrated circuit design in the panel display technology, which can effectively reduce the manufacturing cost, and also can effectively reduce the size of the left and right frames in the panel specification size, but because the gate scan driving circuit mainly replaces the functional circuit of the original driving IC, it has raised higher requirements on the manufacturing process of the thin film transistor and the characteristics of the thin film transistor, but because the characteristics of the thin film transistor cannot meet the requirements of the same capability as the IC, the circuit design is more important, and especially in the reliability of the panel, the related design of the circuit in the reliability aspect needs to be more emphasized.
The patent publication CN108399899A discloses a bidirectional scanning gate driving circuit, in which the gate of the ninth tft M9 is connected with the second clock signal CKm +2, so that the ninth tft M9 is in a positive-voltage PBT state for a long time within one frame, and thus in a high-temperature and high-humidity environment, the ninth tft M9 is prone to drift forward, so that the ninth tft M9 cannot empty the charge of the pull-up control node netAn at this stage at one time, and the scanning signal Gn is also periodically started until the charge of the pull-up control node netAn at this stage is empty, and therefore, the problem of horizontal line and ghost image of the panel is solved.
In addition, the control terminals of the eleventh thin film transistor (M8A), the fourteenth thin film transistor (M8B), the twelfth thin film transistor (M11A) and the thirteenth thin film transistor (M11B) are all connected to the pull-down maintaining control node and are in a positive-voltage PBT state within one for a long time, so that the eleventh thin film transistor (M8A), the fourteenth thin film transistor (M8B), the twelfth thin film transistor (M11A) and the thirteenth thin film transistor (M11B) are prone to drift under a high-temperature and high-humidity environment, and simulation verification shows that the potential of the pull-up control node netAn at the current stage periodically generates ripple, which affects the stability of the circuit and causes a problem of panel failure.
Disclosure of Invention
The invention aims to provide a grid scanning driving circuit which reduces the positive drift risk of a thin film transistor and reduces the difficulty of the manufacturing process.
The invention provides a grid scanning driving circuit, which comprises an N-level grid driving circuit unit; the nth stage gate driving circuit unit comprises a pull-up control module, a pull-down maintaining module, a pull-up module, an emptying reset module and a bootstrap capacitor, wherein the pull-up control module, the pull-down maintaining module, the pull-up module and the bootstrap capacitor are connected to a pull-up control node of the present stage, the pull-down maintaining module and the emptying reset module are connected to the maintaining control node of the present stage, and the pull-down maintaining module, the pull-up module and the touch maintaining module output a gate scanning signal of the present stage; wherein N and N are both positive integers, 1 ≦ N ≦ N; the pull-down module includes a fourth thin film transistor (M9), a fifth thin film transistor (M9A), and a sixth thin film transistor (M9B); the control end of the fourth thin film transistor (M9) is connected with a third clock signal, the first pass end of the fourth thin film transistor (M9), the first pass end of the fifth thin film transistor (M9A) and the first pass end of the sixth thin film transistor (M9B) are all connected with the pull-up control node of the current stage, and the second pass end of the fourth thin film transistor (M9), the second pass end of the fifth thin film transistor (M9A) and the second pass end of the sixth thin film transistor (M9B) are all connected with a low level; when N is 1 or 2, or N-1, the control terminal of the fifth thin film transistor (M9A) and the control terminal of the sixth thin film transistor (M9B) both input an enable signal; when N is more than 2 and less than N-1, the control end of the fifth thin film transistor (M9A) is connected with the (N-4) th-level gate scanning driving signal, and the control end of the sixth thin film transistor (M9B) is connected with the (N +4) th-level gate scanning driving signal.
Further, the pull-down module further comprises a third thin film transistor (M4A), when N is 1, 2 and 3 or N is N, N-1 and N-3, the control terminal of the third thin film transistor (M4A) inputs a low level, the first pass terminal of the third thin film transistor (M4A) is connected to the pull-up control node of the current stage, and the second pass terminal of the third thin film transistor (M4A) is connected to the low level; when the N is more than 3 and less than the N-3, the control end of the third thin film transistor (M4A) inputs a starting signal, the first path end of the third thin film transistor (M4A) is connected with the pull-up control node of the current stage, and the second path end of the third thin film transistor (M4A) is connected with the low level.
Further, the pull-up control module comprises a first thin film transistor (M1A) and a second thin film transistor (M1B), when n is 1, a control terminal and a first path terminal of the first thin film transistor (M1A) are connected and both input a start signal, and a second path terminal of the first thin film transistor (M1A) is connected to the pull-up control node of the current stage; when N is equal to N, the control terminal and the first path terminal of the second thin film transistor (M1B) are connected and input with the start signal, and the second path terminal of the second thin film transistor (M1B) is connected with the pull-up control node of the current stage; when N is more than 1 and less than N, the control end of the first thin film transistor (M1A) is connected with the first path end and inputs the grid driving signals of the first two stages, the second path end of the first thin film transistor (M1A) is connected with the pull-up control node of the current stage, the control end of the second thin film transistor (M1B) is connected with the first path end and connected with the grid driving signals of the second two stages, and the second path end of the second thin film transistor M1B is connected with the pull-up control node of the current stage.
Further, the pull-down sustain module includes a tenth thin film transistor (M13A), an eleventh thin film transistor (M8A), a twelfth thin film transistor (M11A), a thirteenth thin film transistor (M11B), a fourteenth thin film transistor (M8B), and a fifteenth thin film transistor (M13B); wherein a first path terminal of the eleventh thin film transistor (M8A) and a first path terminal of the fourteenth thin film transistor (M8B) are connected to the present-stage pull-up control node, a second path terminal of the tenth thin film transistor (M13A) and a second path terminal of the fifteenth thin film transistor (M13B) are connected to a low level, and a first path terminal of the twelfth thin film transistor (M11A) and a first path terminal of the thirteenth thin film transistor (M11B) output the present-stage gate scan signal.
Further, when 1 < N, the control terminal of the tenth thin film transistor (M13A), the control terminal of the eleventh thin film transistor (M8A), the control terminal of the twelfth thin film transistor (M11A), the second pass terminal of the thirteenth thin film transistor (M11B), the second pass terminal of the fourteenth thin film transistor (M8B), and the first pass terminal of the fifteenth thin film transistor (M13B) are all connected to the nth-2 stage sustain control node, the first pass terminal of the tenth thin film transistor (M13A), the second pass terminal of the eleventh thin film transistor (M8A), the second pass terminal of the twelfth thin film transistor (M11A), the control terminal of the thirteenth thin film transistor (M11B), the control terminal of the fourteenth thin film transistor (M8B), and the control terminal of the fifteenth thin film transistor (M13B) are all connected to the nth +2 stage sustain control node; when n is equal to 1, the control terminal of the tenth thin film transistor (M13A), the control terminal of the eleventh thin film transistor (M8A), the control terminal of the twelfth thin film transistor (M11A), the second path terminal of the thirteenth thin film transistor (M11B), the second path terminal of the fourteenth thin film transistor (M8B) and the first path terminal of the fifteenth thin film transistor (M13B) are all connected to the first sustain control node generating signal; when N is equal to N, the first path terminal of the tenth thin film transistor (M13A), the second path terminal of the eleventh thin film transistor (M8A), the second path terminal of the twelfth thin film transistor (M11A), the control terminal of the thirteenth thin film transistor (M11B), the control terminal of the fourteenth thin film transistor (M8B), and the control terminal of the fifteenth thin film transistor (M13B) are all connected to the second sustain control node to generate signals; the first stage sustain control node generates a signal for generating a first stage sustain control node, and the second stage sustain control node generates a signal for generating an nth stage sustain control node.
Further, the pull-down maintaining module further includes a seventh thin film transistor (M5), an eighth thin film transistor (M6) and a ninth thin film transistor (M7), a control terminal and a first pass terminal of the seventh thin film transistor (M5) are connected and are all connected to the first clock signal, a control terminal of the eighth thin film transistor (M6) is connected to the pull-up control node of the present stage, a control terminal of the ninth thin film transistor (M7) is connected to the third clock signal, a second pass terminal of the seventh thin film transistor (M5), a first pass terminal of the eighth thin film transistor (M6) and a first pass terminal of the ninth thin film transistor (M7) are all connected to the present stage maintaining control node, and a second pass terminal of the eighth thin film transistor (M6) and a second pass terminal of the ninth thin film transistor (M7) are all connected to a low level.
Further, the pull-up module includes a sixteenth thin film transistor (M10), a control terminal of the sixteenth thin film transistor (M10) is connected to the pull-up control node of the present stage, a first path terminal of the sixteenth thin film transistor (M10) is connected to the first clock signal, and a second path terminal of the sixteenth thin film transistor (M10) outputs the gate scan driving signal of the present stage.
Furthermore, a first plate of the bootstrap capacitor is connected to the pull-up control node of the current stage, and a second plate of the bootstrap capacitor outputs a gate scanning driving signal of the current stage.
Further, the empty reset module comprises a seventeenth thin film transistor (M3) and an eighteenth thin film transistor (M2), a control terminal of the seventeenth thin film transistor (M3) and a control terminal of the eighteenth thin film transistor (M2) are both connected to the empty reset signal, a first pass terminal of the seventeenth thin film transistor (M3) is connected to the current-stage sustain control node, a first pass terminal of the eighteenth thin film transistor (M2) is connected to the current-stage pull-up control node, and a second pass terminal of the seventeenth thin film transistor (M3) and a second pass terminal of the eighteenth thin film transistor (M2) are both connected to the low level.
The touch control maintaining module comprises a nineteenth thin film transistor (M12), a path end of the nineteenth thin film transistor (M12) is connected with the touch control emptying signal, a first path end of the nineteenth thin film transistor (M12) outputs the gate scanning driving signal of the current stage, and a second path end of the nineteenth thin film transistor (M12) is connected with the low level.
According to the gate scanning driving circuit, the fifth thin film transistor M9A and the sixth thin film transistor M9B are added, so that the panel can be reduced in a high-temperature high-humidity deterioration environment, the risk that the fourth thin film transistor M9 is drifting is solved, the tenth thin film transistor (M13A) and the fifteenth thin film transistor (M13B) are newly added to generate the eleventh thin film transistor M8A and the fourteenth thin film transistor M8B and the twelfth thin film transistor M11A and the thirteenth thin film transistor M11B in a negative-pressure NBT state, and the risk that the eleventh thin film transistor M8A and the fourteenth thin film transistor M8B and the twelfth thin film transistor M11A and the thirteenth thin film transistor M11B are drifting is weakened. Therefore, the influence of the limited process of the circuit can be reduced, the process difficulty of the factory can be reduced, and the market competitiveness of the panel can be increased.
Drawings
FIG. 1 is a schematic diagram of a gate scan driving circuit according to the present invention;
fig. 2 is a timing control diagram of the gate scan driving circuit shown in fig. 1.
Gn, nth stage gate scanning drive signal; netAn, pull-up control node; netBn, maintenance control node; VGH, high level; VSS, low level; CKm, a first clock signal; CKm +2, a third clock signal; CKm +4, a fifth clock signal; CLR1, clear reset signal; GSP1, start signal; and TC, touch control of the clear signal.
Detailed Description
The present invention is further illustrated by the following figures and specific examples, which are to be understood as illustrative only and not as limiting the scope of the invention, which is to be given the full breadth of the appended claims and any and all equivalent modifications thereof which may occur to those skilled in the art upon reading the present specification.
For the sake of simplicity, the drawings only schematically show the parts relevant to the present invention, and they do not represent the actual structure as a product. In addition, in order to make the drawings concise and understandable, components having the same structure or function in some of the drawings are only schematically illustrated or only labeled. In this document, "one" means not only "only one" but also a case of "more than one".
The gate scan driving circuit of the present invention, as shown in fig. 1, includes N (N is a positive integer greater than 2) stages of gate driving circuit units; the grid scanning driving circuit is in a single-side driving mode, namely, grid driving circuit units are arranged on the left side and the right side of the display panel. If the (N-1) th stage gate driving circuit unit is positioned at the left side of the display panel and the nth stage gate driving circuit unit is positioned at the right side of the display panel, the (N-1) th stage gate driving circuit unit and the nth stage gate driving circuit unit respectively output the present stage gate scanning signal Gn and the (N-1) th stage gate scanning signal Gn-1 to two adjacent rows of scanning lines, and the number of the scanning lines is N.
Wherein n represents the number of stages of the gate driving circuit unit, the previous stage is represented by n-1, the next stage is represented by n +1, and so on. For convenience of description, some key nodes on the circuit are also denoted by netAn, netBn and Gn, i.e., netAn represents a pull-up control node at the current level, and netBn represents a maintenance control node at the current level.
In this embodiment, the gate scan driving circuit needs eight clock control signals, which are sequentially separated by 1/8 cycles, where the previous stage clock signal is represented by CKm-1, CKm represents the current stage clock signal, and the next stage clock signal is represented by CKm +1, i.e., Ckm +4 is the m +1 th stage clock signal, where m is greater than or equal to 1 and less than or equal to 7.
The first clock signal CK1 or CKm, the third clock signal CK3 or CKm +2, the fifth clock signal CK5 or CKm +5 and the seventh clock signal CK7 or CKm +7 are respectively connected to 4 consecutive gate driving circuit units on the left side, the second clock signal CK2 or CKm +1, the fourth clock signal CK4 or CKm +3, the sixth clock signal CK6 or CKm +5 and the eighth clock signal CK8 or CKm +7 are respectively connected to 4 consecutive gate driving circuit units on the right side, wherein m is the number of groups of gate driving circuit units, and m is 1 if the gate driving units from the 1 st stage to the 8 th stage are in a group; the 9 th to 17 th stages are 2 nd group gate driving units, and m is 2; in this way, if the adjacent 8-level gate driving units are grouped into one group and the corresponding group is m groups, CKm is the first clock signal, which can also be said to be the first clock signal of the m-th group.
The nth (1 ≦ N) gate driving circuit unit includes a pull-up control module 01, a pull-down module 02, a pull-down maintaining module 03, a pull-up module 04, a clear reset module 05, a touch maintaining module 06, and a bootstrap capacitor 07, where the pull-up control module 01, the pull-down module 02, the pull-down maintaining module 03, the pull-up module 04, and the bootstrap capacitor 07 are connected to the pull-up control node netAn at this level, the pull-down maintaining module 03 and the clear reset module 05 are connected to the maintenance control node netBn at this level, the bootstrap capacitor 07 is connected between the pull-down maintaining module 03 and the pull-up module 04, and the pull-down maintaining module 03, the pull-up module 04, and the touch maintaining module 06 output the gate scan signal Gn at this level.
The pull-up control module 01 includes a first thin film transistor M1A and a second thin film transistor M1B.
When n is equal to 1, the control terminal and the first path terminal of the first thin film transistor M1A are connected and both input the start signal GSP1, and the second path terminal of the first thin film transistor M1A is connected to the pull-up control node netAn at this stage; when N is equal to N, the control terminal and the first path terminal of the second thin film transistor M1B are connected and both input the start signal GSP1, and the second path terminal of the second thin film transistor M1B is connected to the pull-up control node netAn at this stage. When N is greater than 1 and less than N, the control terminal of the first thin film transistor M1A is connected to the first path terminal and both inputs the first two-stage gate driving signal Gn-2, the second path terminal of the first thin film transistor M1A is connected to the pull-up control node netAn at the present stage, the control terminal of the second thin film transistor M1B is connected to the first path terminal and both connects the second two-stage gate driving signal Gn +2, and the second path terminal of the second thin film transistor M1B is connected to the pull-up control node netAn at the present stage. The pull-down module 02 includes a third thin film transistor M4A, a fourth thin film transistor M9, a fifth thin film transistor M9A, and a sixth thin film transistor M9B.
When N is 1, 2, and 3 or N is N, N-1 and N-3, the control terminal of the third tft M4A inputs the low level VSS, the first path terminal of the third tft M4A is connected to the pull-up control node netAn of the current stage, and the second path terminal of the third tft M4A is connected to the low level VSS; when N is greater than 3 and less than N-3, the control terminal of the third tft M4A receives the start signal GSP1, the first path terminal of the third tft M4A is connected to the pull-up control node netAn, and the second path terminal of the third tft M4A is connected to the low level VSS.
A control terminal of the fourth thin film transistor M9 is connected to the fifth clock signal Ckm +4, a first path terminal of the fourth thin film transistor M9 is connected to the pull-up control node netAn at this stage, and a second path terminal of the fourth thin film transistor M9 is connected to the low level VSS; a first path terminal of the fifth tft M9A is connected to the pull-up control node netAn at this stage, and a second path terminal of the fifth tft M9A is connected to the low level VSS; a first path terminal of the sixth tft M9B is connected to the pull-up control node netAn of the present stage, and a second path terminal of the sixth tft M9B is connected to the low level VSS.
When N is 1 or 2 or N-1, the control terminal of the fifth thin film transistor M9A and the control terminal of the sixth thin film transistor M9B are both input with the start signal GSP 1; when N is more than 2 and less than N-1, the control terminal of the fifth thin film transistor M9A is connected to the (N-4) th stage gate scan driving signal, and the control terminal of the sixth thin film transistor M9B is connected to the (N +4) th stage gate scan driving signal. The gate of the fifth thin film transistor M9A and the gate of the sixth thin film transistor M9B are respectively input with the (n-4) th gate scanning driving signal Gn-4 (i.e. the first 4 gate scanning driving signal Gn-4) and the (n +4) th gate scanning driving signal Gn +4 (i.e. the last 4 gate scanning driving signal Gn +4), so that the problem that the panel is drawn differently due to the fact that the fourth thin film transistor M9 is in the PTB state for a long time under a high-temperature and high-humidity environment, the threshold voltage Vth of the fourth thin film transistor M9 is floating (the floating means exceeds a predetermined voltage), and the voltage of the pull-up control node netAn at the current level cannot clear charges in a non-scanning stage is solved.
The fifth thin film transistor M9A and the sixth thin film transistor M9B reduce the time period in which the voltage Vgs between the source and the drain is high, and only maintain the positive voltage PBT state for several high-level times within one frame, and the fifth thin film transistor M9A and the sixth thin film transistor M9B do not generate positive drift, so that the potential of the pull-up control node netAn at this stage can reduce the risk caused by the positive drift of the threshold voltage Vth of the fourth thin film transistor M9 through the clear charge circuit of the fifth thin film transistor M9A and the sixth thin film transistor M9B in the non-scanning stage, thereby maintaining the basic functionality of the circuit.
The pull-down sustain module 03 includes a seventh thin film transistor M5, an eighth thin film transistor M6, a ninth thin film transistor M7, a tenth thin film transistor M13A, an eleventh thin film transistor M8A, a twelfth thin film transistor M11A, a thirteenth thin film transistor M11B, a fourteenth thin film transistor M8B, and a fifteenth thin film transistor M13B.
The control terminal of the seventh thin film transistor M5 and the first path terminal are connected to each other and are both connected to the first clock signal Ckm, and the second path terminal of the seventh thin film transistor M5 is connected to the current-stage maintenance control node netBn.
The control terminal of the eighth tft M6 is connected to the pull-up control node netAn at this level, the second via terminal of the eighth tft M6 is connected to the sustain control node netBn at this level, and the second via terminal of the eighth tft M6 is connected to the low level VSS.
A control terminal of the ninth tft M7 is connected to the fifth clock signal Ckm +4, a second path terminal of the ninth tft M7 is connected to the current-stage sustain control node netBn, and a second path terminal of the ninth tft M7 is connected to the low level VSS.
When 1 < N, the control terminal of the tenth thin film transistor M13A, the control terminal of the eleventh thin film transistor M8A, the control terminal of the twelfth thin film transistor M11A, the second pass terminal of the thirteenth thin film transistor M11B, the second pass terminal of the fourteenth thin film transistor M8B, and the first pass terminal of the fifteenth thin film transistor M13B are all connected to the nth-2 stage sustain control node, and the first pass terminal of the tenth thin film transistor M13A, the second pass terminal of the eleventh thin film transistor (M8A), the second pass terminal of the twelfth thin film transistor M11A, the control terminal of the thirteenth thin film transistor M11B, the control terminal of the fourteenth thin film transistor (M8B), and the control terminal of the fifteenth thin film transistor (M13B) are all connected to the (N + 2) stage sustain control node; when n is equal to 1, the control terminal of the tenth thin film transistor (M13A), the control terminal of the eleventh thin film transistor M8A, the control terminal of the twelfth thin film transistor M11A, the second path terminal of the thirteenth thin film transistor M11B, the second path terminal of the fourteenth thin film transistor (M8B) and the first path terminal of the fifteenth thin film transistor M13B are all connected to the first maintenance control node generating signal; when N is equal to N, the first path terminal of the tenth thin film transistor M13A, the second path terminal of the eleventh thin film transistor M8A, the second path terminal of the twelfth thin film transistor M11A, the control terminal of the thirteenth thin film transistor M11B, the control terminal of the fourteenth thin film transistor M8B, and the control terminal of the fifteenth thin film transistor M13B are all connected to the second sustain control node generating signal; the first stage sustain control node generates a signal for generating a first stage sustain control node, and the second stage sustain control node generates a signal for generating an nth stage sustain control node.
When 1 < N, the control terminal of the tenth tft M13A, the control terminal of the eleventh tft M8A, and the control terminal of the twelfth tft M11A are all connected to the nth-2-stage sustain control node netBn-2, the first pass terminal of the tenth tft M13A, the second pass terminal of the eleventh tft M8A, and the second pass terminal of the twelfth tft M11A are connected to the (N + 2) -th-stage sustain control node netBn +2, the second pass terminal of the tenth tft M13A is connected to the low-level VSS, the first pass terminal of the eleventh tft M8A is connected to the local pull-up control node an, and the first pass terminal of the twelfth tft M11A outputs the local-stage gate scan driving signal.
When n is equal to 1, the control terminal of the tenth thin film transistor M13A, the control terminal of the eleventh thin film transistor M8A and the control terminal of the twelfth thin film transistor M11A are all connected to the first sustain control node generating signal; when N is equal to N, the first pass terminal of the tenth tft M13A, the second pass terminal of the eleventh tft M8A, and the second pass terminal of the twelfth tft M11A are connected to the second sustain control node generating signal, the first sustain control node generating signal is used to generate the first-stage sustain control node netB1, and the second sustain control node generating signal is used to generate the nth-stage sustain control node netBN.
When 1 < N, the control terminal of the thirteenth thin film transistor M11B, the control terminal of the fourteenth thin film transistor M8B, and the control terminal of the fifteenth thin film transistor M13B are all connected to the (N + 2) th sustain control node netBn +2, the first path terminal of the thirteenth thin film transistor M11B outputs the gate scan driving signal Gn of the present stage, the first path terminal of the fourteenth thin film transistor M8B is connected to the pull-up control node netAn of the present stage, the second path terminal of the thirteenth thin film transistor M11B, the second path terminal of the fourteenth thin film transistor M8B, and the first path terminal of the fifteenth thin film transistor M13B are all connected to the (N-2) th sustain control node bn-2, and the second path terminal of the fifteenth thin film transistor M13B is connected to the low-level VSS.
When N is equal to N, the control terminal of the thirteenth thin film transistor M11B, the control terminal of the fourteenth thin film transistor M8B and the control terminal of the fifteenth thin film transistor M13B are all connected to the second sustain control node generating signal, and the second pass terminal of the thirteenth thin film transistor M11B, the second pass terminal of the fourteenth thin film transistor M8B and the first pass terminal of the fifteenth thin film transistor M13B are all connected to the first sustain control node generating signal; when n is equal to 1, the first path terminal of the tenth thin film transistor M13B, the second path terminal of the eleventh thin film transistor M8A, and the second path terminal of the twelfth thin film transistor M11A are connected to the second sustain control node generating signal. The first maintenance control node generates a signal for generating a first level maintenance control node netB1 and the second maintenance control node generates a signal for generating an nth level maintenance control node netBN.
The pull-up module 04 includes a sixteenth tft M10, a control terminal of the sixteenth tft M10 is connected to the pull-up control node netAn of the present stage, a first path terminal of the sixteenth tft M10 is connected to the first clock signal Ckm, and a second path terminal of the sixteenth tft M10 outputs the gate scan driving signal Gn of the present stage.
A first plate of the bootstrap capacitor C107 is connected to the pull-up control node netAn of the current stage, and a second plate of the bootstrap capacitor C107 outputs the gate scan driving signal Gn of the current stage.
In order to prevent the eleventh and fourteenth tfts M8A and M8B and the twelfth and thirteenth tfts M11A and M11B from being in a positive voltage PBT state for a long time, the threshold voltage Vth is further decreased, the voltage of the non-cleared present-stage pull-up control node netAn loses the function of maintaining a low voltage, the sixteenth tft M10 is turned on after the present-stage gate scan driving signal Gn is output, the present-stage gate scan driving signal Gn and the present-stage pull-up control node netAn have an excessive pulse, so the tenth and fifteenth tfts M13A and M13B cause the eleventh and fourteenth tfts M8A and M8B and the twelfth and thirteenth tfts M11A and M11B to be in a negative voltage (PBT) discharge state when the first path of the tenth and fifteenth tfts M13A and M13B is turned on, when the tft is turned off, the positive voltage (in the negative voltage NBT state) is connected, so that the eleventh tft M8A and the fourteenth tft M8B and the twelfth tft M11A and the thirteenth tft M11B are in the positive voltage PBT and the negative voltage NBT for the same time, thereby reducing the possibility of the positive voltage NBT.
The empty reset module 05 includes a seventeenth thin film transistor M3 and an eighteenth thin film transistor M2, a control terminal of the seventeenth thin film transistor M3 and a control terminal of the eighteenth thin film transistor M2 are both connected to the empty reset signal CLR1, a first path terminal of the seventeenth thin film transistor M3 is connected to the current-stage sustain control node netBn, a first path terminal of the eighteenth thin film transistor M2 is connected to the current-stage pull-up control node netAn, and a second path terminal of the seventeenth thin film transistor M3 and a second path terminal of the eighteenth thin film transistor M2 are both connected to the low-level VSS.
The touch maintaining module 06 includes a nineteenth thin film transistor M12, a path terminal of the nineteenth thin film transistor M12 is connected to the touch clear signal TC, a first path terminal of the nineteenth thin film transistor M12 outputs the present-level gate scan driving signal Gn, and a second path terminal of the nineteenth thin film transistor M12 is connected to the low level VSS.
Fig. 2 is a signal timing diagram, and it can be seen from the waveform diagram that the other ends of the tenth thin film transistor M13A and the fifteenth thin film transistor M13B are respectively connected to the nth + 2-stage sustain control node netBn +2 and the nth-2-stage sustain control node netBn-2, so that when the eleventh thin film transistor M8A and the fourteenth thin film transistor M8B, the twelfth thin film transistor M11A and the thirteenth thin film transistor M11B are turned off, the tenth thin film transistor M13A and the fifteenth thin film transistor M13B are also turned off, and at this time, the eleventh thin film transistor M8A and the fourteenth thin film transistor M8B, and the twelfth thin film transistor M11A and the thirteenth thin film transistor M11B are in the negative pressure NBT stage; M8A/B and the twelfth and thirteenth thin film transistors M11A and M11B are turned on, the tenth and fifteenth thin film transistors M13A and M13B are also turned on, when the eleventh and fourteenth thin film transistors M8A and M11A and the twelfth and thirteenth thin film transistors M11A and M11B are in the positive voltage PBT stage, it can be seen from fig. 2 that the time for the n +2 th stage sustain control node netBn +2 and the n-2 th stage sustain control node netBn-2 to maintain the positive and negative voltages is the same, so that the time for the positive voltage PBT and the negative voltage NBT of the eleventh and fourteenth thin film transistors M8A and M8B and the twelfth and twelfth thin film transistors M11A and M11B are the same, which can reduce the possibility of the positive voltage NBT of the eleventh and fourteenth thin film transistors M8 and M11A and M11B, therefore, the fluctuation of the signal of the pull-up control node netAn at the current stage and the fluctuation of the gate scanning driving signal Gn at the current stage can be reduced, and the circuit stability can be maintained.
According to the gate scanning driving circuit, the fifth thin film transistor M9A and the sixth thin film transistor M9B are added, so that the panel can be reduced in a high-temperature high-humidity deterioration environment, the risk that the fourth thin film transistor M9, the eleventh thin film transistor M8A, the fourteenth thin film transistor M8B, the twelfth thin film transistor M11A and the thirteenth thin film transistor M11B are in drift is solved, meanwhile, the influence of limited manufacturing process of the circuit can be reduced, the difficulty of factory manufacturing is reduced, and the competitiveness of the panel in the market is increased.
Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the details of the foregoing embodiments, and various equivalent changes (such as number, shape, position, etc.) may be made to the technical solution of the present invention within the technical spirit of the present invention, and these equivalent changes are all within the protection scope of the present invention.
Claims (10)
1. A gate scanning drive circuit comprises N stages of gate drive circuit units; the nth stage gate driving circuit unit comprises a pull-up control module, a pull-down maintaining module, a pull-up module, an emptying reset module and a bootstrap capacitor, wherein the pull-up control module, the pull-down maintaining module, the pull-up module and the bootstrap capacitor are connected to a pull-up control node of the present stage, the pull-down maintaining module and the emptying reset module are connected to the maintaining control node of the present stage, and the pull-down maintaining module, the pull-up module and the touch maintaining module output a gate scanning signal of the present stage; wherein N and N are both positive integers, 1 ≦ N ≦ N; wherein the pull-down module comprises a fourth thin film transistor (M9), a fifth thin film transistor (M9A), and a sixth thin film transistor (M9B); the control end of the fourth thin film transistor (M9) is connected with a third clock signal, the first pass end of the fourth thin film transistor (M9), the first pass end of the fifth thin film transistor (M9A) and the first pass end of the sixth thin film transistor (M9B) are all connected with the pull-up control node of the current stage, and the second pass end of the fourth thin film transistor (M9), the second pass end of the fifth thin film transistor (M9A) and the second pass end of the sixth thin film transistor (M9B) are all connected with a low level; when N is 1 or 2 or N-1, the control terminal of the fifth thin film transistor (M9A) and the control terminal of the sixth thin film transistor (M9B) both input a start signal; when N is more than 2 and less than N-1, the control end of the fifth thin film transistor (M9A) is connected with the (N-4) th-level gate scanning driving signal, and the control end of the sixth thin film transistor (M9B) is connected with the (N +4) th-level gate scanning driving signal.
2. The gate scan driving circuit according to claim 1, wherein: the pull-down module further comprises a third thin film transistor (M4A), when N is 1, 2 and 3 or N is N, N-1 and N-3, the control terminal of the third thin film transistor (M4A) inputs a low level, the first pass terminal of the third thin film transistor (M4A) is connected to the pull-up control node of the current stage, and the second pass terminal of the third thin film transistor (M4A) is connected to the low level; when the N is more than 3 and less than the N-3, the control end of the third thin film transistor (M4A) inputs a starting signal, the first path end of the third thin film transistor (M4A) is connected with the pull-up control node of the current stage, and the second path end of the third thin film transistor (M4A) is connected with the low level.
3. The gate scan driving circuit according to claim 1, wherein: the pull-up control module comprises a first thin film transistor (M1A) and a second thin film transistor (M1B), when n is 1, a control end of the first thin film transistor (M1A) is connected with a first path end and both inputs a starting signal, and a second path end of the first thin film transistor (M1A) is connected with a pull-up control node of the current stage; when N is equal to N, the control terminal and the first path terminal of the second thin film transistor (M1B) are connected and input with the start signal, and the second path terminal of the second thin film transistor (M1B) is connected with the pull-up control node of the current stage; when N is more than 1 and less than N, the control end of the first thin film transistor (M1A) is connected with the first path end and inputs the grid driving signals of the first two stages, the second path end of the first thin film transistor (M1A) is connected with the pull-up control node of the current stage, the control end of the second thin film transistor (M1B) is connected with the first path end and connected with the grid driving signals of the second two stages, and the second path end of the second thin film transistor M1B is connected with the pull-up control node of the current stage.
4. The gate scan driving circuit according to claim 1, wherein: the pull-down maintaining module includes a tenth thin film transistor (M13A), an eleventh thin film transistor (M8A), a twelfth thin film transistor (M11A), a thirteenth thin film transistor (M11B), a fourteenth thin film transistor (M8B), and a fifteenth thin film transistor (M13B); wherein a first path terminal of the eleventh thin film transistor (M8A) and a first path terminal of the fourteenth thin film transistor (M8B) are connected to the present-stage pull-up control node, a second path terminal of the tenth thin film transistor (M13A) and a second path terminal of the fifteenth thin film transistor (M13B) are connected to a low level, and a first path terminal of the twelfth thin film transistor (M11A) and a first path terminal of the thirteenth thin film transistor (M11B) output the present-stage gate scan signal.
5. The gate scan driving circuit according to claim 4, wherein: when 1 < N, the control terminal of the tenth thin film transistor (M13A), the control terminal of the eleventh thin film transistor (M8A), the control terminal of the twelfth thin film transistor (M11A), the second pass terminal of the thirteenth thin film transistor (M11B), the second pass terminal of the fourteenth thin film transistor (M8B), and the first pass terminal of the fifteenth thin film transistor (M13B) are all connected to the nth-2 stage sustain control node, and the first pass terminal of the tenth thin film transistor (M13A), the second pass terminal of the eleventh thin film transistor (M8A), the second pass terminal of the twelfth thin film transistor (M11A), the control terminal of the thirteenth thin film transistor (M11B), the control terminal of the fourteenth thin film transistor (M8B), and the control terminal of the fifteenth thin film transistor (M13B) are all connected to the nth +2 stage sustain control node; when n is equal to 1, the control terminal of the tenth thin film transistor (M13A), the control terminal of the eleventh thin film transistor (M8A), the control terminal of the twelfth thin film transistor (M11A), the second path terminal of the thirteenth thin film transistor (M11B), the second path terminal of the fourteenth thin film transistor (M8B) and the first path terminal of the fifteenth thin film transistor (M13B) are all connected to the first sustain control node generating signal; when N is equal to N, the first path terminal of the tenth thin film transistor (M13A), the second path terminal of the eleventh thin film transistor (M8A), the second path terminal of the twelfth thin film transistor (M11A), the control terminal of the thirteenth thin film transistor (M11B), the control terminal of the fourteenth thin film transistor (M8B), and the control terminal of the fifteenth thin film transistor (M13B) are all connected to the second sustain control node generating signal; the first stage sustain control node generates a signal for generating a first stage sustain control node, and the second stage sustain control node generates a signal for generating an nth stage sustain control node.
6. The gate scan driving circuit according to claim 4, wherein: the pull-down maintaining module further comprises a seventh thin film transistor (M5), an eighth thin film transistor (M6) and a ninth thin film transistor (M7), wherein a control end and a first pass end of the seventh thin film transistor (M5) are connected and are all connected with the first clock signal, a control end of the eighth thin film transistor (M6) is connected with the pull-up control node of the current stage, a control end of the ninth thin film transistor (M7) is connected with the third clock signal, a second pass end of the seventh thin film transistor (M5), a first pass end of the eighth thin film transistor (M6) and a first pass end of the ninth thin film transistor (M7) are all connected with the maintaining control node of the current stage, and a second pass end of the eighth thin film transistor (M6) and a second pass end of the ninth thin film transistor (M7) are all connected with a low level.
7. The gate scan driving circuit according to claim 1, wherein: the pull-up module comprises a sixteenth thin film transistor (M10), wherein a control terminal of the sixteenth thin film transistor (M10) is connected with the pull-up control node of the current stage, a first path terminal of the sixteenth thin film transistor (M10) is connected with the first clock signal, and a second path terminal of the sixteenth thin film transistor (M10) outputs the gate scanning driving signal of the current stage.
8. The gate scan driving circuit according to claim 1, wherein: and a first pole plate of the bootstrap capacitor is connected with the pull-up control node of the current stage, and a second pole plate of the bootstrap capacitor outputs a grid scanning driving signal of the current stage.
9. The gate scan driving circuit according to claim 1, wherein: the emptying reset module comprises a seventeenth thin film transistor (M3) and an eighteenth thin film transistor (M2), wherein a control end of the seventeenth thin film transistor (M3) and a control end of the eighteenth thin film transistor (M2) are both connected with an emptying reset signal, a first pass end of the seventeenth thin film transistor (M3) is connected with a current-stage maintaining control node, a first pass end of the eighteenth thin film transistor (M2) is connected with a current-stage pull-up control node, and a second pass end of the seventeenth thin film transistor (M3) and a second pass end of the eighteenth thin film transistor (M2) are both connected with a low level.
10. The gate scan driving circuit according to claim 1, wherein: the touch control maintaining module comprises a nineteenth thin film transistor (M12), a path end of the nineteenth thin film transistor (M12) is connected with a touch control emptying signal, a first path end of the nineteenth thin film transistor (M12) outputs a current-level grid scanning driving signal, and a second path end of the nineteenth thin film transistor (M12) is connected with a low level.
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| TWI465039B (en) * | 2009-10-15 | 2014-12-11 | Au Optronics Corp | Shift register circuit |
| CN103489484B (en) * | 2013-09-22 | 2015-03-25 | 京东方科技集团股份有限公司 | Shifting register unit and gate drive circuit |
| CN106448599B (en) * | 2016-10-25 | 2019-11-19 | 南京华东电子信息科技股份有限公司 | Forward and reverse scanning gate driving circuit |
| CN108399899A (en) * | 2018-01-29 | 2018-08-14 | 南京中电熊猫平板显示科技有限公司 | A kind of bilateral scanning gate driving circuit |
| CN108538268B (en) * | 2018-04-20 | 2020-08-04 | 南京中电熊猫液晶显示科技有限公司 | Bidirectional scanning grid driving circuit |
| WO2020140195A1 (en) * | 2019-01-02 | 2020-07-09 | 京东方科技集团股份有限公司 | Shift register and driving method therefor, gate driving circuit, and display device |
| CN115064127A (en) * | 2019-01-09 | 2022-09-16 | 京东方科技集团股份有限公司 | Shift register and driving method thereof, grid driving circuit and display device |
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