WO2020140195A1

WO2020140195A1 - Shift register and driving method therefor, gate driving circuit, and display device

Info

Publication number: WO2020140195A1
Application number: PCT/CN2019/070064
Authority: WO
Inventors: 冯雪欢; 李永谦
Original assignee: 京东方科技集团股份有限公司; 合肥鑫晟光电科技有限公司
Priority date: 2019-01-02
Filing date: 2019-01-02
Publication date: 2020-07-09
Also published as: US20210217349A1; JP2022523280A; US20220059013A9; EP3907730A1; JP2024016235A; JP7438130B2; EP3907730A4; CN111937066B; US11568790B2; CN111937066A

Abstract

A shift register and a driving method therefor, a gate driving circuit, and a display device. The shift register (10) can comprise a compensation selection circuit (100), a holding circuit (200) and N shift register circuits (300). The holding circuit can hold a blanking input signal. Each of the shift register circuits can comprise a blanking input circuit (310) and an output circuit (330). The blanking input circuit can provide a blanking pull-down signal to a first node (Q) according to the blanking input signal and a blanking control signal (CLKA). The output circuit can output a shift signal from a shift signal output end (CR) according to the voltage of the first node, and output a first driving signal from a first driving signal output end (OUT). The compensation selection circuit can provide the blanking input signal to the holding circuit and the N shift register circuits according to a compensation selection control signal (OE) and the shift signal outputted by one of the N shift register circuits.

Description

Shift register and its driving method, grid driving circuit and display device

Technical field

The present disclosure relates to the field of display technology, and in particular, to a shift register and its driving method, a gate driving circuit, an array substrate, and a display device.

Background technique

Array substrate row drive (Gate Driver on Array, GOA for short) technology makes the gate drive circuit on the array substrate to realize the function of scanning the pixel circuit line by line. The gate driving circuit may include a plurality of cascaded shift registers. The scan signal is output from the output terminal of the shift register to drive the pixel circuit and the cascade signal is simultaneously output to drive the shift register of the next stage.

In the display field, especially in Organic Light-Emitting Diode (OLED for short) display devices, the gate drive circuit is currently integrated in the gate drive chip. In chip design, the area of the chip is the main factor affecting the cost of the chip. Generally, the gate drive circuit includes a sensing circuit, a scanning circuit, and a connection circuit (for example, an OR gate circuit) that connects the outputs of the sensing circuit and the scanning circuit. The structure of such a gate drive circuit is very complicated, and it is difficult to meet the requirements of high resolution and narrow border.

Summary of the invention

The embodiments of the present disclosure provide a shift register and a driving method thereof, a gate driving circuit, an array substrate, and a display device.

According to a first aspect of the present disclosure, a shift register is provided. The shift register may include a compensation selection circuit, a holding circuit, and N shift register circuits. The holding circuit is configured to hold the blanking input signal. Each of the N shift register circuits includes a blanking input circuit configured to provide a blanking pull-down signal to the first node according to the blanking input signal and the blanking control signal; the output circuit is configured to The voltage of a node outputs the shift signal from the shift signal output terminal, and outputs the first drive signal from the first drive signal output terminal. The compensation selection circuit is configured to provide a blanking input to the holding circuit and the N shift registration circuits via the first control node according to the compensation selection control signal and the shift signal output from one of the N shift registration circuits signal. N is a natural number greater than 1.

In an embodiment of the present disclosure, the holding circuit includes the first capacitor. The first terminal of the first capacitor is coupled to the first control node, and the other terminal is coupled to the second voltage terminal to receive the second voltage.

In the embodiment of the present disclosure, the compensation selection circuit includes a first transistor. The control electrode of the first transistor and the compensation selection control signal terminal are coupled to receive the compensation selection control signal, and the first electrode of the first transistor is coupled to the shift signal output terminal of one of the N shift register circuits , The second electrode of the first transistor is coupled to the first control node.

In an embodiment of the present disclosure, the blanking input circuit includes a second transistor and a third transistor. The control electrode of the second transistor is coupled to the first control node, the first electrode of the second transistor is coupled to the first voltage terminal to receive the first voltage as a blanking pull-down signal, and the second electrode of the second transistor and the third transistor Is coupled to the first pole. The control electrode of the third transistor is coupled to the first clock signal terminal to receive the first clock signal as a blanking control signal, and the second electrode of the third transistor is coupled to the first node.

In an embodiment of the present disclosure, the output circuit includes: a nineteenth transistor, a twenty-second transistor, and a second capacitor. The control electrode of the nineteenth transistor is coupled to the first node, the first electrode of the nineteenth transistor and the fourth clock signal terminal are coupled to receive the fourth clock signal, and the second electrode of the nineteenth transistor and the shift signal output端coupled. The control electrode of the twenty-second transistor is coupled to the first node. The first electrode of the twenty-second transistor is coupled to the fourth clock signal terminal to receive the fourth clock signal. The second electrode of the twenty-second transistor is coupled to the first node. A driving signal output terminal is coupled. The second capacitor is coupled between the first node and the shift signal output terminal.

In the embodiment of the present disclosure, each shift register circuit further includes a display input circuit. The display input circuit is configured to provide a display pull-down signal to the first node according to the display input signal.

In an embodiment of the present disclosure, the display input circuit includes a fourth transistor. The control electrode of the fourth transistor is coupled to the display input signal terminal to receive the display input signal, the first electrode of the fourth transistor and the first voltage terminal are coupled to receive the first voltage as the display pull-down signal, and the second electrode of the fourth transistor Coupling with the first node.

In the embodiment of the present disclosure, each shift register circuit further includes a first control circuit, a pull-up circuit, and a second control circuit. The first control circuit is configured to control the voltage of the pull-up node according to the voltage of the first node. The pull-up circuit is configured to provide the second voltage from the second voltage terminal to the first node, the shift signal output terminal, and the first drive signal output terminal according to the voltage of the pull-up node. The second control circuit is configured to control the voltage of the pull-up node according to the blanking control signal and the voltage of the first control node, and to control the voltage of the pull-up node according to the display input signal.

In an embodiment of the present disclosure, the pull-up node may include a first pull-up node. The first control circuit may include a seventh transistor and an eighth transistor. The control electrode of the seventh transistor is coupled to the first electrode and the third voltage terminal, and the second electrode of the seventh transistor is coupled to the first pull-up node. The control electrode of the eighth transistor is coupled to the first node, the first electrode of the eighth transistor is coupled to the first pull-up node, and the second electrode of the eighth transistor is coupled to the second voltage terminal. The pull-up circuit may include a ninth transistor, a twentieth transistor, and a twenty-third transistor. The control electrode of the ninth transistor is coupled to the first pull-up node, the first electrode of the ninth transistor is coupled to the first node, and the second electrode of the ninth transistor is coupled to the second voltage terminal. The control electrode of the twentieth transistor is coupled to the first pull-up node, the first electrode of the twentieth transistor is coupled to the shift signal output terminal, and the second electrode of the twentieth transistor is coupled to the second voltage terminal. The control electrode of the twenty-third transistor is coupled to the first pull-up node, the first electrode of the twenty-third transistor is coupled to the first drive signal output terminal, and the second electrode and the second voltage terminal of the twenty-third transistor Coupling. The second control circuit may include a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor. The control electrode of the thirteenth transistor is coupled to the first clock signal terminal to receive the first clock signal as a blanking control signal, and the first electrode of the thirteenth transistor is coupled to the first pull-up node. The control electrode of the fourteenth transistor is coupled to the first control node, the first electrode of the fourteenth transistor is coupled to the second electrode of the thirteenth transistor, and the second electrode of the fourteenth transistor is coupled to the second voltage terminal . The control electrode of the fifteenth transistor is coupled to the display input signal terminal to receive the display input signal, the first electrode of the fifteenth transistor is coupled to the first pull-up node, and the second electrode and the second voltage terminal of the fifteenth transistor Coupling.

In an embodiment of the present disclosure, the pull-up node may further include a second pull-up node. The first control circuit also includes a tenth transistor and an eleventh transistor. The control electrode of the tenth transistor is coupled to the first electrode and the fourth voltage terminal, and the second electrode of the tenth transistor is coupled to the second pull-up node. The control electrode of the eleventh transistor is coupled to the first node, the first electrode of the eleventh transistor is coupled to the second pull-up node, and the second electrode of the eleventh transistor is coupled to the second voltage terminal. The pull-up circuit may further include a twelfth transistor, a twenty-first transistor, and a twenty-fourth transistor. The control electrode of the twelfth transistor is coupled to the second pull-up node, the first electrode of the twelfth transistor is coupled to the first node, and the second electrode of the twelfth transistor is coupled to the second voltage terminal. The control electrode of the twenty-first transistor is coupled to the second pull-up node, the first electrode of the twenty-first transistor is coupled to the output terminal of the shift signal, and the second electrode of the twenty-first transistor is coupled to the second voltage terminal . The control pole of the twenty-fourth transistor is coupled to the second pull-up node, the first pole of the twenty-fourth transistor is coupled to the first drive signal output terminal, and the second pole of the twenty-fourth transistor is coupled to the second voltage terminal Coupling. The second control circuit may further include a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor. The control electrode of the sixteenth transistor is coupled to the first clock signal terminal to receive the first clock signal as a blanking control signal, and the first electrode of the sixteenth transistor is coupled to the second pull-up node. The control electrode of the seventeenth transistor is coupled to the first control node, the first electrode of the seventeenth transistor is coupled to the second electrode of the sixteenth transistor, and the second electrode of the seventeenth transistor is coupled to the second voltage terminal . The control electrode of the eighteenth transistor is coupled to the display input signal terminal to receive the display input signal, the first electrode of the eighteenth transistor is coupled to the second pull-up node, and the second electrode and the second voltage terminal of the eighteenth transistor Coupling.

In the embodiment of the present disclosure, each shift register circuit further includes a reset circuit. The reset circuit is configured to reset the first node according to the blanking reset signal from the blanking reset signal terminal, and reset the first node according to the display reset signal from the display reset signal terminal.

In an embodiment of the present disclosure, the reset circuit may include a fifth transistor and a sixth transistor. The control electrode of the fifth transistor is coupled to the blanking reset signal terminal, the first electrode of the fifth transistor is coupled to the first node, and the second electrode of the fifth transistor is coupled to the second voltage terminal. The control electrode of the sixth transistor is coupled to the display reset signal terminal, the first electrode of the sixth transistor is coupled to the first node, and the second electrode of the sixth transistor is coupled to the second voltage terminal.

In an embodiment of the present disclosure, the output circuit may further include a twenty-fifth transistor and a third capacitor. The control electrode of the twenty-fifth transistor is coupled to the first node. The first electrode of the twenty-fifth transistor is coupled to the fifth clock signal terminal to receive the fifth clock signal. The second electrode of the twenty-fifth transistor is coupled to the first node. The two driving signal output terminals are coupled. The third capacitor is coupled between the first node and the second driving signal output terminal.

In an embodiment of the present disclosure, the pull-up circuit may further include a twenty-sixth transistor and a twenty-seventh transistor. The control electrode of the twenty-sixth transistor is coupled to the first pull-up node, the first electrode of the twenty-sixth transistor is coupled to the second drive signal output terminal, and the second electrode and the second voltage terminal of the twenty-sixth transistor Coupling. The control pole of the twenty-seventh transistor is coupled to the second pull-up node, the first pole of the twenty-seventh transistor is coupled to the second drive signal output terminal, and the second pole of the twenty-seventh transistor is coupled to the second voltage terminal Coupling.

In the embodiment of the present disclosure, the shift register includes a compensation selection circuit and a holding circuit.

According to a second aspect of the present disclosure, a gate driving circuit is provided. The gate driving circuit may include M shift registers according to any one of claims 1 to 13 and a first sub-clock signal line. The first sub-clock signal line provides a compensation selection control signal to each shift register.

In the embodiment of the present disclosure, the gate driving circuit may further include a second sub-clock signal line and a blanking reset signal line. The shift signal output by the i-th shift register circuit is supplied to the i+2th shift register circuit as a display input signal. The second sub-clock signal line provides a first clock signal to each shift register circuit. The blanking reset signal line provides a blanking reset signal to each shift register circuit. The shift signal output from the i+3th shift register circuit is supplied to the i th shift register circuit as a display reset signal.

In the embodiment of the present disclosure, the gate driving circuit may further include a third sub-clock signal line, a fourth sub-clock signal line, a fifth sub-clock signal line, and a sixth sub-clock signal line. The third sub-clock signal line supplies the fourth clock signal to the 4i-3th shift register circuit. The fourth sub-clock signal line provides a fourth clock signal to the 4i-2th shift register circuit. The fifth sub-clock signal line supplies the fourth clock signal to the 4i-1th shift register circuit. The sixth sub-clock signal line provides a fourth clock signal to the 4ith shift register circuit.

In the embodiment of the present disclosure, the gate driving circuit may further include a seventh sub-clock signal line, an eighth sub-clock signal line, a ninth sub-clock signal line, and a tenth sub-clock signal line. The seventh sub-clock signal line supplies the fifth clock signal to the 4i-3th shift register circuit. The eighth sub-clock signal line supplies the fifth clock signal to the 4i-2th shift register circuit. The ninth sub-clock signal line supplies the fifth clock signal to the 4i-1th shift register circuit. The tenth sub-clock signal line provides the fifth clock signal to the 4ith shift register circuit.

According to a third aspect of the present disclosure, an array substrate is provided. The array substrate includes the gate driving circuit provided according to the second aspect of the present disclosure.

According to a fourth aspect of the present disclosure, a display device is provided. The display device includes the array substrate provided according to the third aspect of the present disclosure.

According to a fifth aspect of the present disclosure, a method for driving the shift register provided by the first aspect of the present disclosure is provided. In the method, the blanking input signal is provided according to the compensation selection control signal and one of the N shift signals; the blanking input signal is maintained. The blanking pull-down signal is provided to the first node according to the blanking input signal and the blanking control signal; and N shift signals are output from the N shift signal outputs according to the voltage of the first node, and from the N first The driving signal output terminal outputs N first driving signals.

BRIEF DESCRIPTION

In order to more clearly explain the technical solutions of the present disclosure, the drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of the present disclosure, rather than limiting the present disclosure. In the drawings:

FIG. 1 shows a schematic block diagram of a shift register according to an embodiment of the present disclosure;

2 shows a schematic block diagram of a shift register according to an embodiment of the present disclosure;

FIG. 3 shows an exemplary circuit diagram of a shift register according to an embodiment of the present disclosure;

4(1), (2), (3), (4) and (5) respectively show exemplary circuit diagrams of a blanking input circuit according to an embodiment of the present disclosure;

5(1), (2) and (3) respectively show exemplary circuit diagrams of a display input circuit according to an embodiment of the present disclosure;

6 (1) and (2) respectively show exemplary circuit diagrams of a second control circuit according to an embodiment of the present disclosure;

7 shows an exemplary circuit diagram of a shift register according to another embodiment of the present disclosure;

8 shows a schematic diagram of a gate driving circuit according to an embodiment of the present disclosure;

9 shows a timing diagram of signals during operation of the gate driving circuit according to an embodiment of the present disclosure; and

FIG. 10 shows a schematic flowchart of a method for driving a shift register according to an embodiment of the present disclosure.

detailed description

In order to make the technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described clearly and completely in conjunction with the drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, but not all the embodiments. Based on the described embodiments, all other embodiments obtained by a person of ordinary skill in the art without creative work are also within the scope of the present disclosure.

Unless otherwise defined, the technical or scientific terms used in the present disclosure shall have the usual meanings understood by those of ordinary skill in the art to which this disclosure belongs. The terms “first”, “second” and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words like "a", "a" or "the" do not mean a quantity limit, but mean that there is at least one. Similar words such as "include" or "include" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, but do not exclude other elements or objects. Similar terms such as "connect" or "couple" are not limited to physical or mechanical connections, but may include electrical connections, and may be direct connections or indirect connections through intermediate media. "Up", "down", "left", "right", etc. are only used to indicate the relative positional relationship. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

When compensating for the sub-pixels in the OLED display panel, in addition to providing a pixel compensation circuit for internal compensation in the sub-pixels, external compensation can also be performed by providing a sensing transistor. When performing external compensation, the gate drive circuit needs to provide drive signals for the scan transistor and the sense transistor to the sub-pixels in the display panel, respectively. As described above, the sensing circuit in the gate driving circuit may provide a driving signal for sensing the transistor, and the scanning circuit may provide a driving signal for scanning the transistor to cause the sub-pixel to display. For example, the display stage (Display) of one frame provides a driving signal for scanning the transistor to display the sub-pixels. The blanking stage (Blank) of one frame provides a driving signal for the sensing transistor to externally compensate the sub-pixels. During the blanking phase, the display panel is not displayed. In the embodiments of the present disclosure, "one frame", "every frame", or "a certain frame" includes a display phase and a blanking phase that are sequentially performed.

In an external compensation method, the sensing drive signal output by the gate drive circuit is sequentially scanned line by line, for example, the drive signal for the sub-pixels of the first line in the display panel is output during the blanking phase of the first frame , During the blanking phase of the second frame, the driving signals for the sub-pixels of the second row in the display panel are output, and so on, and the frequency of the driving signals corresponding to the sub-pixels of one row is output in sequence for each frame, that is, the display is completed Line-by-line sequential compensation of the panel.

However, when using the above progressive compensation method, it may cause display problems: first, there is a scanning line that moves row by row during the multi-frame scanning display; second, because of the time point of external compensation The difference will cause the brightness difference in different areas of the display panel to be relatively large. For example, when externally compensating the sub-pixels in the 100th row of the display panel, the sub-pixels in the 10th, 11th, and 12th rows of the display panel have been externally compensated. However, at this time, the luminous brightness of the sub-pixels in the 10th, 11th, and 12th rows may have changed. For example, the luminous brightness is reduced, which may cause uneven brightness in different areas of the display panel. This problem occurs in large-size display panels. Will be more obvious.

In response to the above problems, the shift register unit provided by the embodiments of the present disclosure can achieve random compensation of one or more rows of sub-pixels, thereby avoiding display defects such as scan lines and uneven display brightness due to row-by-row sequential compensation, and simplify Circuit configuration.

The embodiments of the present disclosure provide a shift register and a driving method thereof, a gate driving circuit, an array substrate, and a display device. The embodiments and examples of the present disclosure will be described in detail below with reference to the drawings.

FIG. 1 shows a schematic block diagram of a shift register according to an embodiment of the present disclosure. As shown in FIG. 1, the shift register 10 may include a compensation selection circuit 100, a holding circuit 200, and N shift register circuits (300_1...300_N, hereinafter may be collectively referred to as 300). N is a natural number greater than 1.

In an embodiment of the present disclosure, the holding circuit 200 may hold the blanking input signal. For example, the holding circuit 200 may be coupled between the first control node H and the second voltage terminal V2. The holding circuit 200 may receive the blanking input signal via the first control node H, and hold the blanking input signal. In an embodiment, the second voltage terminal may provide a DC high-level signal, that is, the second voltage V2 is a high level.

Each shift register circuit 300 may include a blanking input circuit (310_1...310_N, hereinafter may be collectively referred to as 310) and an output circuit (330_1...330_N, hereinafter may be collectively referred to as 330).

The blanking input circuit 310 may provide the blanking pull-down signal to the first node (which may also be called a pull-down node) according to the blanking input signal and the blanking control signal (Q_1...Q_N, hereinafter may be collectively referred to as Q), to Control the voltage of the first node Q. For example, the blanking input circuit 310 may be coupled to the first control node H to receive the blanking input signal, to the first clock signal terminal to receive the first clock signal CLKA as the blanking control signal, and to the first voltage terminal Connected to receive the first voltage V1 as a blanking pull-down signal. In an embodiment, the first voltage terminal may provide a DC low-level signal, that is, the first voltage V1 is a low level.

The output circuit 330 may output a shift signal from the shift signal output terminal (CR_1...CR_N, hereinafter may be collectively referred to as CR) according to the voltage of the first node Q, and output from the first drive signal output terminal (OUT1_1...OUT1_N, hereinafter It may be collectively referred to as OUT1) to output the first driving signal. For example, the output circuit 330 may be coupled to the fourth clock signal terminal to receive the fourth clock signal CLKD. The output circuit 330 may provide the fourth clock signal CLKD to the shift signal output terminal CR and the first drive signal output terminal OUT1 according to the voltage of the first node Q.

In an embodiment, during the display phase of one frame, the shift signal may be used to control the shift of the upper and lower shift register circuits, for example, and the first drive signal may be used to drive the scan transistor in the display panel, thereby driving the display panel to perform display. In the blanking phase of a frame, the first driving signal may be used to drive a sensing transistor in a row of sub-pixels in the display panel to sense the driving current of the row of sub-pixels, so as to compensate based on the sensed driving current.

The compensation selection circuit 100 may, according to the compensation selection control signal OE from the compensation selection control signal terminal and the shift signal CR output from one of the N shift register circuits 300, pass the first control node H to the holding circuit 200 and N shift register circuits 300 provide blanking input signals.

In an embodiment, in the display phase of one frame, the timing of the compensation selection control signal OE may be set to be the same as the timing of the shift signal CR provided to the compensation selection circuit 100. For example, as shown in FIG. 1, the shift signal CR_1 output from the first shift register circuit 300_1 among the N shift register circuits 300 is supplied to the compensation selection circuit 100, and the compensation selection control signal OE is displayed during the display phase The timing is set to be the same as the shift signal CR_1.

In an embodiment, one compensation selection circuit 100 and one holding circuit 200 may provide blanking pull-down signals to N first nodes Q of N shift register circuits to output N driving signals from N driving signal output terminals . Compared with the case where one compensation selection circuit 100 and one holding circuit 200 can only provide a blanking pull-down signal to one first node Q, the embodiments of the present disclosure can save the compensation selection circuit 100 and the holding circuit 200 in the gate driving circuit. Quantity.

FIG. 2 shows a schematic block diagram of a shift register according to another embodiment of the present disclosure. As shown in FIG. 2, the shift register 20 may include a compensation selection circuit 100, a holding circuit 200 and N shift register circuits 300. The number of shift register circuits 300 in the shift register 20 is two or more, but for ease of description, only one shift register circuit 300_1 is schematically shown in FIG. 2 and the other shift register circuits (300_2... The circuit structure of 300_N) can refer to the description of the shift register circuit 300_1.

As shown in FIG. 2, the shift register circuit 300_1 may include a blanking input circuit 310, a display input circuit 320, an output circuit 330, a first control circuit 340, a pull-up circuit 350, a second control circuit 360, and a reset circuit 370. Among them, the circuit structures of the compensation selection circuit 100, the holding circuit 200, and the blanking input circuit 310 are the same as those of the compensation selection circuit 100, the holding circuit 200, and the blanking input circuit 310_1 in FIG. 1, which have been described above. This will not be repeated here.

In an embodiment, the display input circuit 320 may provide a display pull-down signal to the first node Q according to the display input signal to control the voltage of the first node Q. For example, the display input circuit 320 may be coupled to a display input signal terminal (STU_1...STU_N, hereinafter may be collectively referred to as STU) to receive a display input signal, and coupled to a first voltage terminal to receive a first voltage V1 as a display pull-down signal .

In an embodiment, the output circuit 330 may include a second driving signal output terminal in addition to the first driving signal output terminal. The output circuit 330 may output the second driving signal from the second driving signal output terminal OUT2 according to the voltage of the first node Q. For example, the output circuit 330 may be coupled to the fifth clock signal terminal to receive the fifth clock signal CLKE. In an embodiment, the output circuit 330 may also provide the fifth clock signal CLKE to the second driving signal output terminal OUT2 according to the voltage of the first node Q. In addition, the other structures and functions of the output circuit 510 are the same as those of the output circuit 330_1 in FIG. 1 and will not be repeated here. It can be understood by those skilled in the art that the number of driving signal output terminals is not limited to two, and may be more than two. The output circuit may output a corresponding driving signal according to the voltage of the first node Q and the corresponding clock signal.

The first control circuit 340 may control the voltage of the pull-up node QB according to the voltage of the first node Q. For example, the first control circuit 340 may be coupled to the second voltage terminal to receive the second voltage V2 and coupled to the third voltage terminal to receive the third voltage V3. In an embodiment, the second voltage terminal may provide a DC high-level signal, that is, the second voltage V2 is a high level. The first control circuit 600 may control the voltage of the pull-up node QB according to the second voltage V2 and the third voltage V3 under the control of the voltage of the first node Q.

Further, the first control circuit 340 may also be coupled to the fourth voltage terminal to receive the fourth voltage V4. The third voltage terminal and the fourth voltage terminal may alternately provide a DC low-level signal, for example, one of the third voltage V3 and the fourth voltage V4 is a low level, and the other is a high level. In an embodiment, the first control circuit 340 may control the voltage of the pull-up node QB according to the second voltage V2 and the third voltage V3 (or the fourth voltage V4) under the control of the voltage of the first node Q.

The pull-up circuit 350 may provide the second voltage V2 from the second voltage terminal to the first node Q, the shift signal output terminal CR, the first drive signal output terminal OUT1, and the second drive signal output according to the voltage of the pull-up node QB Terminal OUT2. For example, the pull-up circuit 350 may be coupled to the second voltage terminal to receive the second voltage V2. Thus, the pull-up circuit 350 can reduce the noise at each terminal by pulling up the first node Q, the shift signal output terminal CR, and the corresponding drive signal output terminal.

The second control circuit 360 may control the voltage of the pull-up node QB according to the blanking control signal and the voltage of the first control node H. For example, the second control circuit 360 may be coupled to the first clock signal terminal to receive the first clock signal CLKA as a blanking control signal, and coupled to the second voltage terminal to receive the second voltage. In an embodiment, the second control circuit 360 may provide the second voltage to the pull-up node QB under the control of the first clock signal CLKA and the voltage of the first control node H. In addition, the second control circuit 360 can also control the voltage of the pull-up node QB according to the display input signal STU. For example, the second control circuit 360 may be coupled to the display input signal terminal to receive the display input signal STU2. In an embodiment, the second control circuit 360 may provide the second voltage to the pull-up node QB under the control of the display input signal STU. Thus, the second control circuit 360 can pull up the pull-up node QB

In addition, the reset circuit 370 may reset the first node Q according to the blanking reset signal TRST from the blanking reset signal terminal, and reset the first node Q according to the display reset signal STD from the display reset signal terminal. For example, the reset circuit 370 may be coupled to the blanking reset signal terminal to receive the blanking reset signal TRST, coupled to the display reset signal terminal to receive the display reset signal STD, and coupled to the second voltage terminal to receive the second voltage V2 . In an embodiment, the reset circuit 370 may provide the second voltage V2 to the first node Q according to the blanking reset signal TRST and the second voltage V2 to the first node Q according to the display reset signal STD.

Those skilled in the art can understand that although the shift register 20 in FIG. 2 shows the first control circuit 340, the pull-up circuit 350, the second control circuit 360, and the reset circuit 370, the above example does not limit the protection of the present disclosure range. In actual applications, technicians can choose to use or not use one or more of the above circuits according to the situation. Various combinations and modifications based on the foregoing circuits do not deviate from the principles of the present disclosure and will not be repeated here.

The following describes the shift register provided by the present disclosure through an exemplary circuit structure. FIG. 3 shows an exemplary circuit diagram of a shift register according to an embodiment of the present disclosure. The shift register is, for example, the shift register 20 shown in FIG. 2. For ease of description, the circuit structure of only one shift register circuit 300_1 is shown in FIG. 3, and the circuit structure of other shift register circuits (300_2...300_N) can refer to the description of the shift register circuit 300_1. As shown in FIG. 3, the shift register may include a first transistor M1 to a twenty-seventh transistor M27, and a first capacitor C1 to a third capacitor C3.

It should be noted that all the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics. In the embodiments of the present disclosure, thin film transistors are used as examples. The source and drain of the transistor used here may be symmetrical in structure, so the source and drain may be indistinguishable in structure. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one pole of the first pole and the other pole of the second pole are directly described. The gate of the transistor can be referred to as the gate. In addition, the transistors can be divided into N-type and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the on-voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltage), and the off-voltage is a high-level voltage (for example, 5V, 10V or other suitable voltage) Voltage). When the transistor is an N-type transistor, the on-voltage is a high-level voltage (for example, 5V, 10V or other suitable voltage), and the off-voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable Voltage).

In addition, it should be noted that the transistors used in the shift register provided in the embodiments of the present disclosure are all described using P-type transistors as an example. Embodiments of the present disclosure include, but are not limited to, for example, at least part of the transistors in the shift register may also use N-type transistors.

In an embodiment of the present disclosure, the pull-up node QB may include at least one of a first pull-up node QB_A and a second pull-up node QB_B. FIG. 3 shows a case where the pull-up node QB includes both the first pull-up node QB_A and the second pull-up node QB_B. It can be understood that the pull-up node QB may also include only one of the first pull-up node QB_A and the second pull-up node QB_B, and the associated circuit only needs to be adjusted accordingly.

As shown in FIG. 3, the compensation selection circuit 100 includes a first transistor M1. The control electrode of the first transistor M1 and the compensation selection control signal terminal are coupled to receive the compensation selection control signal OE, the first electrode of the first transistor M1 and the shift signal of one of the N shift register circuits 300_1 The output terminal CR_1 is coupled, and the second electrode of the first transistor M1 is coupled to the first control node H. In the embodiment, when the compensation selection control signal OE is at a low level, the first transistor M1 is turned on, so that the shift signal CR_1 can be provided to the first control node H to provide the holding circuit 200 and N shift register circuits 300 provides blanking input signal.

The holding circuit 200 includes a first capacitor C1. The first terminal of the first capacitor is coupled to the first control node H, and the other terminal is coupled to the second voltage terminal to receive the second voltage V2.

The blanking input circuit 310 includes a second transistor M2 and a third transistor M3. The control electrode of the second transistor M2 is coupled to the first control node H, the first electrode of the second transistor M2 and the first voltage terminal are coupled to receive the first voltage V1 as a blanking pull-down signal, and the second of the second transistor M2 The electrode is coupled to the first electrode of the third transistor. The control electrode of the third transistor M3 is coupled to the first clock signal terminal to receive the first clock signal CLKA as a blanking control signal. The first electrode of the third transistor M3 is coupled to the second electrode of the second transistor M2. The second electrode of the transistor M3 is coupled to the first node Q. In an embodiment, when the voltage of the first control node H and the first clock signal CLKA are both low, the second transistor M2 and the third transistor M3 are turned on to provide the first voltage V1 to the first node Q, Pull the first node Q low.

The display input circuit 320 includes a fourth transistor M4. The control electrode of the fourth transistor M4 is coupled to the display input signal terminal to receive the display input signal STU, the first electrode of the fourth transistor M4 and the first voltage terminal are coupled to receive the first voltage V1 as the display pull-down signal, and the fourth transistor The second pole of M4 is coupled to the first node Q. In the embodiment, when the display input signal STU is at a low level, the fourth transistor M4 is turned on to provide the first voltage V1 to the first node Q, so that the voltage of the first node Q is at a low level.

The output circuit 330 includes a nineteenth transistor M19, a twenty-second transistor M22, a twenty-fifth transistor M25, a second capacitor C2, and a third capacitor C3. The control electrode of the nineteenth transistor M19 is coupled to the first node Q, the first electrode of the nineteenth transistor M19 and the fourth clock signal terminal are coupled to receive the fourth clock signal CLKD, and the second electrode of the nineteenth transistor M19 It is coupled to the shift signal output terminal CR. The control electrode of the twenty-second transistor M22 is coupled to the first node Q, the first electrode of the twenty-second transistor M22 and the fourth clock signal terminal are coupled to receive the fourth clock signal CLKD, and the twenty-second transistor M22 The second pole and the first driving signal output terminal are coupled to OUT1. The control electrode of the twenty-fifth transistor M25 is coupled to the first node Q, the first electrode of the twenty-fifth transistor M25 and the fifth clock signal terminal are coupled to receive the fifth clock signal CLKE, and the twenty-fifth transistor M25 The second pole is coupled to the second driving signal output terminal OUT2. The first terminal of the second capacitor C2 is coupled to the first node Q, and the second terminal of the second capacitor C2 is coupled to the shift signal output terminal CR. The first terminal of the third capacitor C3 is coupled to the first node Q, and the second terminal of the third capacitor C3 is coupled to the second driving signal output terminal OUT2.

In an embodiment, when the first node Q is at a low level, the nineteenth transistor M19, the twenty-second transistor M22, and the twenty-fifth transistor M25 are turned on to provide the fourth clock signal CLKD to the shift signal output terminal CR and the first driving signal output terminal are coupled to OUT1, and the fifth clock signal CLKE is provided to the second driving signal output terminal OUT2.

The first control circuit 340 includes a seventh transistor M7, an eighth transistor M8, a tenth transistor M10, and an eleventh transistor M11. The control electrode of the seventh transistor M7 is coupled to the first electrode and the third voltage terminal to receive the third voltage V3, and the second electrode of the seventh transistor M7 is coupled to the first pull-up node QB_A. The control electrode of the eighth transistor M8 is coupled to the first node Q, the first electrode of the eighth transistor M8 is coupled to the first pull-up node QB_A, and the second electrode of the eighth transistor M8 is coupled to the second voltage terminal to receive The second voltage V2. The control electrode and the first electrode of the tenth transistor M10 are coupled to the fourth voltage terminal to receive the fourth voltage V4, and the second electrode of the tenth transistor M10 is coupled to the second pull-up node QB_B. The control electrode of the eleventh transistor M11 is coupled to the first node Q, the first electrode of the eleventh transistor M11 is coupled to the second pull-up node QB_B, the second electrode of the eleventh transistor M11 and the second voltage terminal V2 Coupled to receive the second voltage V2.

Understandably, when the pull-up node QB includes only the first pull-up node QB_A (or the second pull-up node QB_B), the first control circuit 600 may include a seventh transistor M7 and an eighth transistor M8 (or a tenth transistor M10 And the eleventh transistor M11). The specific circuit structure is similar and will not be repeated here.

In an embodiment, the third voltage terminal V3 and the fourth voltage terminal V4 may be configured to alternately provide a low level. That is, when the third voltage terminal V3 provides a high level, the fourth voltage terminal V4 provides a low level, and the tenth transistor M10 is turned on. When the third voltage terminal V3 provides a low level, the fourth voltage terminal V4 provides a high level, and the seventh transistor M7 is turned on. Therefore, only one of the seventh transistor M7 and the tenth transistor M10 is in an on state. In this way, performance drift caused by long-term conduction of the transistor can be avoided.

The third voltage can charge the first pull-up node QB_A when the seventh transistor M7 is turned on, and the second voltage can charge the second pull-up node QB_B when the tenth transistor M10 is turned on, thereby pulling the first pull-up node QB_B The voltage of the node QB_A or the second pull-up node QB_B is controlled to a low level. When the voltage of the first node Q is low, the eighth transistor M8 and the eleventh transistor M11 are turned on. For example, in the design of the transistor, the seventh transistor M7 and the eighth transistor M8 can be configured (for example, the size ratio of the two, the threshold voltage, etc.). When both M7 and M8 are turned on, the first pull-up node QB_A The voltage of can be pulled up to a high level via the second voltage V2, which can keep the twentieth transistor M20, the twenty-third transistor M23, and the twenty-sixth transistor M26 off. On the other hand, the tenth transistor M10 and the eleventh transistor M11 can be configured (for example, the size ratio of the two, the threshold voltage, etc.). When both M10 and M11 are turned on, the voltage of the second pull-up node QB_B can be It is pulled up to a high level via the second voltage V2, which can keep the twenty-first transistor M21, the twenty-fourth transistor M24, and the twenty-seventh transistor M27 off.

As shown in FIG. 3, the pull-up circuit 350 includes a ninth transistor M9, a twentieth transistor M20, a twenty-third transistor M23, a twelfth transistor M12, a twenty-first transistor M21, a twenty-fourth transistor M24, a third Twenty-six transistor M26 and twenty-seven transistor M27.

The control electrode of the ninth transistor M9 is coupled to the first pull-up node QB_A, the first electrode of the ninth transistor M9 is coupled to the first node Q, and the second electrode of the ninth transistor M9 is coupled to the second voltage terminal V2 Receive the second voltage V2. The control electrode of the twentieth transistor M20 is coupled to the first pull-up node QB_A, the first electrode of the twentieth transistor M20 is coupled to the shift signal output terminal CR, the second electrode of the twentieth transistor M20 and the second voltage The terminal V2 is coupled. The control electrode of the twenty-third transistor M23 is coupled to the first pull-up node QB_A, the first electrode of the twenty-third transistor M23 is coupled to the first drive signal output terminal OUT1, and the second electrode of the twenty-third transistor M23 The second voltage terminal V2 is coupled to receive the second voltage V2. The control pole of the twenty-sixth transistor M26 is coupled to the first pull-up node QB_A, the first pole of the twenty-sixth transistor is coupled to the second drive signal output terminal OUT2, and the second pole of the twenty-sixth transistor is coupled to the first The second voltage terminal V2 is coupled to receive the second voltage V2. In an embodiment, when the voltage of the first pull-up node QB_A is a low level, the ninth transistor M9, the twentieth transistor M20, the twenty-third transistor M23, and the twenty-sixth transistor are turned on to connect the first node Q, the shift signal output terminal CR, the first drive signal output terminal OUT1 and the second drive signal output terminal OUT2 are pulled up.

The control electrode of the twelfth transistor M12 is coupled to the second pull-up node QB_B, the first electrode of the twelfth transistor M12 is coupled to the first node Q, the second electrode of the twelfth transistor M12 and the second voltage terminal V2 Coupling. The control electrode of the twenty-first transistor M21 is coupled to the second pull-up node QB_B, the first electrode of the twenty-first transistor M21 is coupled to the shift signal output terminal CR, and the second electrode of the twenty-first transistor M21 is The second voltage terminal V2 is coupled. The control pole of the twenty-fourth transistor M24 is coupled to the second pull-up node QB_B, the first pole of the twenty-fourth transistor M24 is coupled to the first drive signal output terminal OUT1, and the second pole of the twenty-fourth transistor M24 It is coupled to the second voltage terminal V2. The control pole of the twenty-seventh transistor M27 is coupled to the second pull-up node QB_B, the first pole of the twenty-seventh transistor is coupled to the second drive signal output terminal OUT2, the second pole of the twenty-seventh transistor and the second The two voltage terminals V2 are coupled. In an embodiment, when the voltage of the second pull-up node QB_B is low, the twelfth transistor M12, the twenty-first transistor M21, the twenty-fourth transistor M24, and the twenty-seventh transistor M27 are turned on The first node Q, the shift signal output terminal CR, the first drive signal output terminal OUT1 and the second drive signal output terminal OUT2 are pulled up.

It can be understood that when the pull-up node QB includes only the first pull-up node QB_A (or the second pull-up node QB_B), the pull-up circuit 700 may include a ninth transistor M9, a twentieth transistor M20, and a twenty-third Transistor M23, twenty-sixth transistor (or, twelfth transistor M12, twenty-first transistor M21, twenty-fourth transistor M24, and twenty-seventh transistor M27). The specific circuit structure is the same and will not be repeated here.

As shown in FIG. 3, the second control circuit 360 may include a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, and an eighteenth transistor M18.

The control electrode of the thirteenth transistor M13 is coupled to the first clock signal terminal to receive the first clock signal CLKA as a blanking control signal, and the first electrode of the thirteenth transistor M13 is coupled to the first pull-up node QB_A. The control electrode of the fourteenth transistor M14 is coupled to the first control node H, the first electrode of the fourteenth transistor M14 is coupled to the second electrode of the thirteenth transistor M13, and the second electrode of the fourteenth transistor M14 is coupled to the first The two voltage terminals V2 are coupled. The control pole of the fifteenth transistor M15 is coupled to the display input signal terminal to receive the display input signal STU2, the first pole of the fifteenth transistor M15 is coupled to the first pull-up node QB_A, and the second pole of the fifteenth transistor M15 The second voltage terminal is coupled to receive the second voltage V2. In an embodiment, when the voltages of the first clock signal CLKA and the first control node H are both low level, the second voltage is supplied to the first pull-up node QB_A. In addition, when the display input signal STU2 is at a low level, the second voltage is supplied to the first pull-up node QB_A.

The control electrode of the sixteenth transistor M16 is coupled to the first clock signal terminal to receive the first clock signal CLKA as a blanking control signal, and the first electrode of the sixteenth transistor M16 is coupled to the second pull-up node QB_B. The control electrode of the seventeenth transistor M17 is coupled to the first control node H, the first electrode of the seventeenth transistor M17 is coupled to the second electrode of the sixteenth transistor M16, and the second electrode of the seventeenth transistor M17 is coupled to the first The two voltage terminals are coupled to receive the second voltage V2. The control pole of the eighteenth transistor M18 is coupled to the display input signal terminal to receive the display input signal STU2, the first pole of the eighteenth transistor M18 is coupled to the second pull-up node QB_B, and the second pole of the eighteenth transistor M18 The second voltage terminal is coupled to receive the second voltage V2. In an embodiment, when the voltages of the first clock signal CLKA and the first control node H are both low level, the second voltage is supplied to the second pull-up node QB_B. In addition, when the display input signal STU2 is at a low level, the second voltage is supplied to the second pull-up node QB_B.

It can be understood that when the pull-up node QB includes only the first pull-up node QB_A (or the second pull-up node QB_B), the pull-up circuit 700 may include the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth The transistor M15 (or, the sixteenth transistor M16, the seventeenth transistor M17, and the eighteenth transistor M18). The specific circuit structure is the same and will not be repeated here.

In addition, as shown in FIG. 3, the reset circuit 370 may include a fifth transistor M5 and a sixth transistor M6. The control electrode of the fifth transistor M5 is coupled to the blanking reset signal terminal to receive the blanking reset signal TRST, the first electrode of the fifth transistor M5 is coupled to the first node Q, and the second electrode of the fifth transistor M5 and the second The voltage terminal is coupled to receive the second voltage V2. In the embodiment, when the blanking reset signal TRST is at a low level, the fifth transistor M5 is turned on to provide the second voltage V2 to the first node Q. The control electrode of the sixth transistor M6 is coupled to the display reset signal terminal to receive the display reset signal STD, the first electrode of the sixth transistor M6 is coupled to the first node Q, the second electrode of the sixth transistor M6 and the second voltage terminal V2 is coupled. In the embodiment, when the display reset signal STD is at a low level, the sixth transistor M6 is turned on, and the second voltage V2 is supplied to the first node Q.

It can be understood that the circuits in the shift register in the embodiments of the present disclosure are not limited to the above circuit structure, and the optional circuit modification is schematically described below with reference to the drawings, and the modification is also non-limiting.

4(1)-(5) respectively show exemplary circuit diagrams of the blanking input circuit 310 according to various embodiments of the present disclosure.

As shown in FIGS. 4(1) and (2), the difference between the blanking input circuit 310 and the blanking input circuit 310 in FIG. 3 is that the first electrode of the second transistor is coupled to a different clock signal terminal to receive the corresponding clock signal As a blanking pull-down signal. For example, the third clock signal terminal CLKC or the first clock signal terminal CLKA. In other words, the blanking pull-down signal does not have to be kept at a low level all the time, and it only needs to be a low level during the period when the blanking control signal CLKA is low.

As shown in FIG. 4(3), the blanking input circuit 310 differs from the blanking input circuit 310 in FIG. 4(1) in that it further includes a blanking input transistor M3_a. The control electrode of the blanking input transistor M3_a is coupled to the second electrode of the second transistor and the first electrode of the third transistor. The first electrode of the blanking input transistor M3_a is coupled to the first voltage terminal V1, and the first electrode of the blanking input transistor M3_a The two poles are coupled to the first node Q.

As described in FIG. 4(4), the blanking input circuit 310 differs from the blanking input circuit 310 in FIG. 4(3) in that the third transistor is replaced with the transistor M3_b and the transistor M3_c. The control pole of the transistor M3_b is coupled to the first pull-up node QB_A, the control pole of the transistor M3_c is coupled to the second pull-up node QB_B, the first poles of the transistor M3_b and the transistor M3_c are both coupled to the second pole of the second transistor, the transistor M3_b The second electrode of the transistor M3_c is coupled to the second voltage terminal.

As described in FIG. 4(5), the blanking input circuit 310 differs from the blanking input circuit 310 in FIG. 4(3) in that the third transistor is replaced with a transistor M3_b, a transistor M3_c, and a transistor M3_d. The control electrode of the transistor M3_b is coupled to the first control node H, the first electrode of the transistor M3_b is coupled to the second electrode of the transistor M3_d, and the second electrode of the transistor M3_b is coupled to the second voltage terminal. The control electrode of the transistor M3_c is coupled to the first electrode of the transistor M3_b, the first electrode of the transistor M3_c is coupled to the second electrode of the second transistor M2, and the second electrode of the transistor M3_c is coupled to the second voltage terminal V2. The control electrode and the first electrode of the transistor M3_d are coupled to the third clock signal terminal CLKC.

5 (1), (2), and (3) respectively show exemplary circuit diagrams of the display input circuit 320 according to various embodiments of the present disclosure.

As shown in FIG. 5(1), the display input circuit 320 may include a fourth transistor M4 and a fourth leak-proof transistor M4_b. The control electrode and the first electrode of the fourth transistor M4 and the control electrode of the fourth anti-leakage transistor M4_b are coupled to the display input signal terminal to receive the display input signal STU and use it as a display pull-down signal, the second of the fourth transistor M4 The electrode is coupled to the first electrode of the fourth leakage prevention transistor M4_b, and the second electrode of the fourth leakage prevention transistor M4_b is coupled to the first node Q.

As shown in FIG. 5(2), the display input circuit 320 may include a fourth transistor M4 and a fourth leak-proof transistor M4_b. The control electrode of the fourth transistor M4 is coupled to the display input signal terminal to receive the display input signal STU, and the first electrode and the first voltage terminal are coupled to receive the first voltage V1 as the display pull-down signal. The control electrode and the first electrode of the fourth leakage prevention transistor M4_b are coupled to the second electrode of the fourth transistor M4, and the second electrode is coupled to the first node Q.

As shown in FIG. 5(3), the display input circuit 320 may include a fourth transistor M4. The control electrode and the first electrode of the fourth transistor are coupled to the display input signal terminal to receive the display input signal STU2 and use it as a display pull-down signal, and the second electrode is coupled to the first node Q.

6(1) and (2) respectively show exemplary circuit diagrams of the second control circuit 360 according to various embodiments of the present disclosure.

As shown in FIG. 6(1), the second control circuit 360 includes a thirteenth transistor M13, a fifteenth transistor M15, a sixteenth transistor M16, and an eighteenth transistor M18. The control electrode of the thirteenth transistor M13 is coupled to the first clock signal terminal CLKA to receive the first clock signal as a blanking control signal, the first electrode of the thirteenth transistor M13 is coupled to the first pull-up node QB_A, the tenth The second electrode of the three transistor M13 is coupled to the second voltage terminal V2. The control pole of the fifteenth transistor M15 is coupled to the display input signal terminal STU, the first pole of the fifteenth transistor M15 is coupled to the first pull-up node QB_A, and the second pole and the second voltage terminal of the fifteenth transistor M15 V2 is coupled. The control electrode of the sixteenth transistor M16 is coupled to the first clock signal terminal CLKA to receive the first clock signal as a blanking control signal. The first electrode of the sixteenth transistor M16 is coupled to the second pull-up node QB_B, the tenth The second electrode of the six transistor M16 is coupled to the second voltage terminal V2. The control electrode of the eighteenth transistor M18 is coupled to the display input signal terminal, the first electrode of the eighteenth transistor M18 is coupled to the second pull-up node QB_B, the second electrode of the eighteenth transistor M18 and the second voltage terminal V2 Coupling. With respect to the second control circuit 800 of the shift register 20 in FIG. 3, the second control circuit 360 does not include the fourteenth transistor M14 and the seventeenth transistor M17.

As shown in FIG. 6(2), the second control circuit 360 includes a fifteenth transistor M15 and an eighteenth transistor M18. The control pole of the fifteenth transistor M15 is coupled to the display input signal terminal STU2, the first pole of the fifteenth transistor M15 is coupled to the first pull-up node QB_A, and the second pole and the second voltage terminal of the fifteenth transistor M15 V2 is coupled. The control electrode of the eighteenth transistor M18 is coupled to the display input signal terminal, the first electrode of the eighteenth transistor M18 is coupled to the second pull-up node QB_B, the second electrode of the eighteenth transistor M18 and the second voltage terminal V2 Coupling. With respect to the second control circuit 360 of the shift register 20 in FIG. 3, the second control circuit 820 does not include the thirteenth transistor M13, the fourteenth transistor M14, the sixteenth transistor M16, and the seventeenth transistor M17.

FIG. 7 shows an exemplary circuit diagram of a shift register according to another embodiment of the present disclosure. As shown in FIG. 7, the difference between the shift register and the shift register in FIG. 3 is that the second control circuit 360 includes a thirteenth transistor M13, a fifteenth transistor M15, a sixteenth transistor M16, and an eighteenth transistor M18 (See the description of the second control circuit 360 in FIG. 6(1)). In addition, the shift register also adds a first anti-leakage transistor M1_b, a third anti-leakage transistor M3_b, a fifth anti-leakage transistor M5_b, a sixth anti-leakage transistor M6_b, a ninth anti-leakage transistor M9_b, a twelfth anti-leakage transistor M12_b , 28th transistor M28 and 29th transistor M29. The first leakage prevention transistor M1_b is taken as an example to describe the working principle of the leakage prevention.

The control electrode of the first anti-leakage transistor M1_b is coupled to the second clock signal terminal CLKB, the first electrode of the first anti-leakage transistor M1_b is coupled to the second electrode of the twenty-eighth transistor M28, the first anti-leakage transistor M1_b The second pole is coupled to the first control node H. The control electrode of the twenty-eighth transistor M28 is coupled to the first control node H, and the first electrode of the twenty-eighth transistor M28 is coupled to the second voltage terminal V2 to receive a second voltage of a low level. When the first control node H is at a low level, the twenty-eighth transistor M28 is turned on under the control of the level of the first control node H, so that the low-level signal input from the second voltage terminal V2 can be input to the first The first pole of the anti-leakage transistor M1_b, so that both the first and second poles of the first anti-leakage transistor M1_b are in a low level state, preventing the charge at the first control node H from leaking through the first anti-leakage transistor M1_b. At this time, since the control electrode of the first leakage prevention transistor M1_b and the control electrode of the first transistor M1 are coupled, the combination of the first transistor M1 and the first leakage prevention transistor M1_b can achieve the same effect as the aforementioned first transistor M1, At the same time, it has the effect of preventing leakage.

Similarly, the third anti-leakage transistor M3_b, the fifth anti-leakage transistor M5_b, the sixth anti-leakage transistor M6_b, the ninth anti-leakage transistor M9_b, and the twelfth anti-leakage transistor M12_b can be combined with the twenty-ninth transistor M29 to achieve anti-leakage The structure can prevent the electric charge at the first node Q from leaking. The working principle of preventing leakage of the first node Q is the same as the above-mentioned working principle of preventing leakage of the first control node H, which will not be repeated here.

The embodiment of the present disclosure also provides a gate driving circuit constituted by a shift register. As shown in FIG. 8, the gate driving circuit 30 may include M shift registers, where M is an integer greater than 1. Any one or more shift registers may adopt the structure of the shift register 10 or the shift register 20 provided by the embodiments of the present disclosure or a modification thereof. It can be understood that the gate driving circuit 30 has M×N shift register circuits. Only the first two shift registers (A1, A2) are shown schematically in FIG. 8, wherein each shift register includes, for example, two shift register circuits (N=2). As shown in FIG. 8, the first shift register A1 includes a compensation selection circuit 100, a holding circuit 200 (not shown), a shift register circuit 300_1 (hereinafter referred to as a first shift register circuit SC1), and 300_2 (hereinafter referred to as The second shift register circuit SC2). The second shift register A2 includes a compensation selection circuit 100, a holding circuit 200 (not shown), a shift register circuit 300_1 (hereinafter referred to as a third shift register circuit SC3), and 300_2 (hereinafter referred to as a fourth shift register circuit) SC4). In addition, the structures and connection relationships of the third shift register (including the fifth shift register circuit SC5 and the sixth shift register circuit SC6) to the M-th shift register are similar, and their illustrations are omitted here.

As shown in FIG. 8, the display input signal terminal STU of the first shift register circuit SC1 and the display input signal terminal STU of the second shift register circuit SC2 both receive the input signal STU. In addition, the shift signal CR output by the i-th shift register circuit is supplied to the i+2th shift register circuit as a display input signal STU. For example, the shift signal CR of the first shift register circuit SC1 serves as the display input signal STU of the third shift register circuit SC3. The shift signal CR of the second shift register circuit SC2 serves as the display input signal STU of the fourth shift register circuit SC4.

The gate driving circuit 30 further includes a first sub-clock signal line CLK_1 and a second sub-clock signal line CLK_2. The first sub-clock signal line CLK_1 provides the compensation selection control signal OE to each compensation selection circuit 100. The second sub-clock signal line CLK_2 provides the first clock signal CLKA to each shift register circuit.

The compensation selection circuit 100 in each shift register receives the shift signal CR output by the first shift register circuit in the shift register, and thereby sends the first control node H to the first control node H according to the compensation selection control signal OE and the shift signal CR Provide blanking input signal. For example, the compensation selection circuit 100 in the first shift register A1 is coupled to the shift signal output of the first shift register circuit SC1. The compensation selection circuit 100 in the second shift register A2 is coupled to the shift signal output terminal of the third shift register circuit SC3. The compensation selection circuit 100 in the third shift register A3 is coupled to the shift signal output terminal (not shown) of the fifth shift register circuit SC5.

In addition, the shift signal CR output from the i+3th shift register circuit is supplied to the i-th shift register circuit as a display reset signal STD. For example, the shift signal CR of the fourth shift register circuit SC4 serves as the display reset signal STD of the first shift register circuit SC1.

The gate drive circuit 30 also includes a blanking reset signal line TRST, which provides a blanking reset signal TRST to each shift register circuit.

As shown in FIG. 8, the gate driving circuit 30 may further include a third sub-clock signal line CLKD_1, a fourth sub-clock signal line CLKD_2, a fifth sub-clock signal line CLKD_3, and a sixth sub-clock signal line CLKD_4. In the embodiment, the third sub-clock signal line CLKD_1 provides the fourth clock signal to the 4i-3th shift register circuit. The fourth sub-clock signal line CLKD_2 provides the fourth clock signal to the 4i-2th shift register circuit. The fifth sub-clock signal line CLKD_3 provides the fourth clock signal to the 4i-1th shift register circuit. The sixth sub-clock signal line CLKD_4 provides the fourth clock signal to the 4ith shift register circuit. As shown in FIG. 8, the third sub-clock signal line CLKD_1 supplies the fourth clock signal to the first shift register circuit SC1 and the fifth shift register circuit SC5 (not shown). The fourth sub-clock signal line CLKD_2 provides a fourth clock signal to the second shift register circuit SC2 and the sixth shift register circuit SC6 (not shown). The fifth sub-clock signal line CLKD_3 supplies the fourth clock signal to the third shift register circuit SC3 and the seventh shift register circuit SC7 (not shown). The sixth sub-clock signal line CLKD_4 supplies the fourth clock signal to the fourth shift register circuit SC4 and the eighth shift register circuit SC8 (not shown).

In addition, the gate driving circuit 30 may further include a seventh sub-clock signal line CLKE_1, an eighth sub-clock signal line CLKE_2, a ninth sub-clock signal line CLKE_3, and a tenth sub-clock signal line CLKE_4. In the embodiment, the seventh sub-clock signal line CLKE_1 supplies the fifth clock signal to the 4i-3th shift register circuit. The eighth sub-clock signal line CLKE_2 provides the fifth clock signal to the 4i-2th shift register circuit. The ninth sub-clock signal line CLKE_3 supplies the fifth clock signal to the 4i-1th shift register circuit. The tenth sub-clock signal line CLKE_4 provides the fifth clock signal to the 4ith shift register circuit. As shown in FIG. 8, the seventh sub-clock signal line CLKE_1 supplies the fifth clock signal to the first shift register circuit SC1 and the fifth shift register circuit SC5 (not shown). The eighth sub-clock signal line CLKE_2 supplies a fifth clock signal to the second shift register circuit SC2 and the sixth shift register circuit SC6 (not shown). The ninth sub-clock signal line CLKE_3 supplies a fifth clock signal to the third shift register circuit SC3 and the seventh shift register circuit SC7 (not shown). The tenth sub-clock signal line CLKE_4 supplies the fifth clock signal to the fourth shift register circuit SC4 and the eighth shift register circuit SC8 (not shown).

It should be noted that the cascading relationship shown in FIG. 8 is only an example, and according to the description of the present disclosure, other cascading manners can also be adopted according to actual conditions.

The working process of the gate driving circuit 30 shown in FIG. 8 will be described below with reference to the signal timing chart in FIG. 9. In the embodiment, the shift registers (A1, A2, etc.) in the gate drive circuit 30 have the circuit structure of the shift register shown in FIG. 3, for example.

FIG. 9 shows a signal timing diagram of the gate driving circuit 30 shown in FIG. 8 when it is used to randomly compensate the fifth row of sub-pixels in the display panel. The signal STU represents the input signal STU. TRST represents the signal supplied to the blanking reset signal line TRST. The signals OE and CLKA represent the signals of the signal CLK_2 provided to the first sub-clock signal line CLK_1 and the second sub-clock line, respectively. The signals CLKD_1, CLKD_2, CLKD_3, and CLKD_4 respectively represent signals provided to the third subclock signal line CLKD_1, the fourth subclock signal line CLKD_2, the fifth subclock signal line CLKD_3, and the sixth subclock signal line CLKD_4. The signals CLKE_1, CLKE_2, CLKE_3, and CLKE_4 represent signals provided to the seventh subclock signal line CLKE_1, the eighth subclock signal line CLKE_2, the ninth subclock signal line CLKE_3, and the tenth subclock signal line CLKE_4, respectively.

H<5> represents the voltage of the first control node H in the third shift register A3 in the gate drive circuit 30, which is provided for the fifth shift register circuit SC5 and the sixth shift register circuit SC6 (not shown) Blank the input signal. Q<5> and Q<6> represent the voltage of the first node Q in the fifth shift register circuit SC5 and the sixth shift register circuit SC6, respectively.

OUT1<1>, OUT1<3>, OUT1<5> and OUT1<8> respectively represent the first shift register circuit SC1, the third shift register circuit SC3, and the fifth shift register circuit in the gate drive circuit 30 The corresponding first drive signal output terminal OUT1 in SC5 and the eighth shift register circuit SC8. OUT2<5> represents the second drive signal output terminal OUT2 of the fifth shift register circuit SC5 in the gate drive circuit 30. It should be noted that the voltages of the shift signal output terminal CR and the drive signal output terminal OUT1 in the shift register of each stage are the same.

In addition, as described above, the transistors shown in FIG. 3 are all P-type, the first voltage V1 is low level, and the second voltage V2 is high level. The third voltage V3 and the fourth voltage V4 alternately provide a low level.

It can be understood that the signal level in the signal timing diagram shown in FIG. 9 is only schematic and does not represent the true level value.

As shown in FIG. 9, one frame 1F includes a display phase and a blanking phase. Before the start of one frame 1F, the blanking reset signal line TRST and the first sub-clock signal line CLK_1 both provide low-level signals to provide low-level blanking reset signals TRST and the compensation selection control signal OE to each shift register So that the first transistor M1 in each stage of the shift register and the fifth transistor M5 in each shift register circuit are turned on. Thus, the blanking input signal STU (input signal STU of high level) is supplied to the first control node H to control the voltage of the first control node H to be high level. The second voltage V2 (high level) is supplied to the first node Q to control the voltage of the first node Q to be high level. Thus, the first control node H and the first node Q at all levels are reset to achieve a global reset.

Then, one frame 1F starts, the third voltage V3 is high level, and the fourth voltage V4 is low level. The seventh transistor M7 is turned off, and the tenth transistor M10 is turned on. The signal provided by the blanking reset signal line TRST becomes a high level, and the fifth transistor M5 is turned off.

The operation of the fifth shift register circuit SC5 (in the third shift register A3) in the random scan gate drive circuit 30 will be described in detail below. The compensation selection circuit 100 in the third shift register A3 receives the compensation selection control signal OE and the shift signal CR<5> output from the fifth shift register circuit SC5. The fifth shift register circuit SC5 receives the shift signal CR<3> output from the third shift register circuit SC3 as the display input signal STU. The fifth shift register circuit SC5 receives the shift signal CR<8> output from the eighth shift register circuit SC8 as the display reset signal STD.

In the display stage Display of one frame 1F, the working process of the first shift register circuit SC1 is described as follows.

In the first period, the display input signal terminal of the first shift register circuit SC1 receives the low-level input signal STU, and the fourth transistor M4 is turned on, so that the first node Q<1 in the first shift register circuit SC1 > Pulled down to low level via the first voltage V1 and held by the second capacitor C2. The nineteenth transistor M19, the twenty-second transistor M22, and the twenty-fifth transistor M25 are turned on under the control of the voltage of the first node Q<1>. Since the fourth clock signal terminal CLKD (coupled to the third sub-clock signal line CLKD_1) and the fifth clock signal CLKE (coupled to the seventh sub-clock signal line CLKE_1) are both high, the first shift register circuit The high-level shift signal CR<1>, the first drive signal OUT1<1>, and the second drive signal OUT2<1> are output.

In the second period, the fourth clock signal terminal CLKD inputs a low-level signal, the potential of the first node Q<1> is further pulled down due to the bootstrap effect, so the nineteenth transistor M19, the twenty-second transistor M22 and The twenty-fifth transistor M25 remains on, so that both the shift signal output terminal CR<1> and the first drive signal output terminal OUT1<1> output low-level signals. For example, the low-level signal output from the shift signal output terminal CR<1> can be used for the scanning shift of the upper and lower shift register units, while the first drive signal output terminal OUT1<1> and the second drive signal are output The low level signal output from the terminal OUT2<1> can be used to drive the sub-pixel unit in the display panel for display.

In the third period, the fourth clock signal terminal CLKD inputs a high-level signal. Since the first node Q<1> remains low at this time, the nineteenth transistor M19, the twenty-second transistor M22, and the twentieth The five transistor M25 remains turned on, so that the shift signal CR<1>, the first driving signal OUT1<1>, and the second driving signal OUT2<1> are all high level. Due to the bootstrap effect of the second capacitor C2, the potential of the first node Q<1> will also increase.

In the fourth period, since the display reset signal terminal STD of the first shift register circuit and the shift signal output terminal CR<4> of the fourth shift register circuit are connected, the shift signal of the fourth shift register circuit at this time The output terminal CR<4> outputs a low level, so the display reset signal terminal STD of the first shift register circuit inputs a low level, the sixth transistor M6 is turned on, and the first node Q<1> is pulled up to a high level, The reset of the first node Q<1> is completed. Since the first node Q<1> is at a high level, the eleventh transistor M11 is turned off, and at the same time, the low level input at the fourth voltage terminal V4 can make the voltage of the second pull-up node QBB become a low level. The twelve transistors M12 are turned on to further control the voltage of the first node Q<1> to be high. At the same time, the twenty-first transistor M21, the twenty-fourth transistor M24, and the twenty-seventh transistor M27 are also turned on, so that the shift signal output terminal CR<1> and the first drive signal output terminal OUT1<1> can be The drive signal input terminal OUT2<1> is further pulled up.

After the first shift register circuit drives the sub-pixels in the first row of the display panel to complete the display, and so on, the second and third shift register circuits drive the sub-pixels in the display panel row by row to complete the display drive of one frame. At this point, the display phase of one frame 1F ends.

At the same time, the pull-up control node H is also charged in the Display stage of the first frame 1F. For example, when the fifth row of sub-pixels needs to be compensated in the first frame 1F, it is displayed in the Display stage of the first frame 1F. Also proceed as follows. The following describes the working process of the fifth shift register circuit SC5 and related shift register circuits as follows.

In the third period, the third shift register circuit SC3 outputs a low-level shift signal CR<3> so that the display input signal STU of the fifth shift register circuit SC5 is a low level. The fourth transistor M4 is turned on to provide the first voltage V1 to the first node Q<5>, and the voltage of the first node Q<5> becomes a low level. Thus, the eighth transistor M8 and the eleventh transistor M11 are turned on. The first pull-up node QB_A and the second pull-up node QB_B are pulled high by the high-level second voltage V2. In addition, since the display input signal STU is at a low level, the fifteenth transistor M15 and the eighteenth transistor M18 are turned on, and the high-level second voltage V2 is provided to the first pull-up node QB_A and the second pull-up node, respectively QB_B, so that the first pull-up node QB_A and the second pull-up node QB_B can be assisted to pull up. At this time, the twentieth transistor M20, the twenty-first transistor M21, the twenty-third transistor M23, the twenty-fourth transistor M24, the twenty-sixth transistor M26, and the twenty-seventh transistor are all turned off.

In addition, the first node Q<5> is at a low level, so that the nineteenth transistor M19, the twenty-second transistor M22, and the twenty-fifth transistor M25 are turned on, and the fourth clock signal CLKD (and the third sub-clock signal The line CLKD_1 is coupled) to the shift signal output terminal CR, the first drive signal output terminal OUT1<5>, and the fifth clock signal CLKE (coupled to the seventh sub-clock signal line CLKE_1) is provided to the second drive signal The output terminal OUT2<5>, respectively output high-level signals.

In the fourth period, the display input signal STU is at a high level, and the fourth transistor is turned off. The first node Q<5> is held at a low level under the holding action of the second capacitor C2. A low-level signal is provided to the fourth clock signal terminal CLKD through the third sub-clock signal line CLKD_1, and a low-level signal is provided to the fifth clock signal terminal CLKE through the seventh sub-clock signal line CLKE_1. The voltage of the first node Q<5> is further pulled down due to the bootstrap effect. The nineteenth transistor M19, the twenty-second transistor M22, and the twenty-fifth transistor M25 remain on, so that the shift signal output terminal CR<5>, the first drive signal output terminal OUT1<5>, and the second drive signal output Both OUT2<5> output low level signal. In addition, the first pull-up node QB_A and the second pull-up node QB_B maintain high levels, the twentieth transistor M20, the twenty-first transistor M21, the twenty-third transistor M23, the twenty-fourth transistor M24, the twentieth The six transistor M26 and the twenty-seventh transistor remain off.

In addition, in the third shift register A3, the shift signal CR (OUT1<5>) of the fifth shift register circuit SC5 is supplied to the compensation selection circuit 100 (ie, the first pole of the first transistor M1), the compensation selection The timing of the control signal OE in the display phase is set to be the same as the timing of the shift signal CR (OUT1<5>). Thus, in the fourth period, the compensation selection control signal OE is supplied as a low-level signal. At this time, the first transistors M1 in all shift registers are turned on. Since the first electrode of the first transistor M1 in the third shift register A3 receives the low-level shift signal CR (OUT1<5>), the first control node H<5> of the third shift register A3 changes Is low. In this case, the third shift register A3 supplies a low-level blanking input signal to the holding circuit 200 and the fifth shift register circuit SC5 and the sixth shift register circuit SC6 via the first control node H<5>. Thereafter, the blanking input signal is maintained by the first capacitor C1, so that the voltage of the first control node H<5> is maintained at a low level.

In the fifth period, the nineteenth transistor M19, the twenty-second transistor M22, and the twenty-fifth transistor M25 remain on. A high-level signal is provided to the fourth clock signal terminal CLKD through the third sub-clock signal line CLKD_1, and a high-level signal is provided to the fifth clock signal terminal CLKE through the seventh sub-clock signal line CLKE_1, so that the shift signal output terminal CR< 5>, the first drive signal output terminal OUT1<5> and the second drive signal output terminal OUT2<5> both output high level signals. Due to the equational transition of the voltage across the second capacitor C2 and the third capacitor C3, the voltage at the first node Q<5> will rise by an amplitude, but is still low. At this time, since the display reset signal STD (ie, OUT1<8>) is at a high level, the first node Q<5> will not be pulled up, so that the pull-up node Q can be maintained at a low level .

In the sixth period, the eighth shift register circuit SC8 outputs a low-level shift signal CR<8>, so that the display reset signal STD of the fifth shift register circuit is a low-level signal, and the sixth transistor M6 is turned on To reset the voltage of the first node Q<5> to a high level. In addition, since the voltage of the first node Q<5> is high, the eleventh transistor M11 is turned off, and the voltage of the second pull-up node QB_B is pulled down to the low level through the tenth transistor M10. Thus, the twelfth transistor M12 is turned on to radiate noise to the first node Q<5>. In addition, the twenty-first transistor M21, the twenty-fourth transistor M24, and the twenty-seventh transistor M27 are turned on to provide the second voltage V2 to the shift signal output terminal CR<5> and the first drive signal output terminal OUT1 <5> and the second drive signal output terminal OUT2<5>, thereby outputting high-level signals respectively.

In the display phase of the above-mentioned one frame 1F, since the first clock signal CLKA is always kept at a low level, the third transistor M3 remains off. The third transistor M3 may isolate the influence of the first control node H on the first node Q.

In the display stage, similar to the above-mentioned operation process of the fifth shift register circuit SC5, the sixth shift register circuit SC6 also receives the blanking input signal provided by the compensation selection circuit 100 of the third shift register A3 via the first control node H . The sixth shift register circuit SC6 outputs a shift signal and a drive signal according to the fourth clock signal CLKD provided by the fourth sub-clock signal line CLKD_2 and the fifth clock signal CLKE provided by the eighth sub-clock signal line CLKE_2.

Then, the blanking phase Blank of one frame 1F starts. In the seventh period, the first control node H<5> remains low, and the second transistor M2 is turned on. The first clock signal CLKA is a low-level signal, and the third transistor M3 is turned on. Thereby, the first voltage V1 of the first voltage terminal is supplied to the first node Q<5>, so that the voltage of the first node Q<5> becomes a low level. During this period, the fourth clock signal CLKD and the fifth clock signal terminal CLKE are both high-level signals, so that the shift signal output terminal CR<5>, the first drive signal output terminal OUT1<5> and the second drive signal are output Both OUT2<5> output high level signal.

In the eighth period, the voltage of the first control node H<5> is kept at a low level, and the second transistor M2 remains turned on. The first clock signal CLKA becomes a high-level signal, and the third transistor M3 is turned off. At this time, the output circuit can output the corresponding driving signal according to the corresponding clock signal to drive the sensing transistor to work. As shown in FIG. 9, the fourth clock signal CLKD provided by the third sub-clock signal line CLKD_1 is a low-level signal, so that the first node Q<5> undergoes a secondary potential drop, and the shift signal CR<5> and the first The drive signals OUT1<5> are all low. At this time, the low-level first driving signal OUT1<5> can drive the sensing transistor in the fifth row of sub-pixels in the display panel to sense the driving current of the row of sub-pixels, thereby compensating based on the sensed driving current. In addition, the second driving signal output terminal OUT2<5> outputs the second driving signal under the control of the fifth clock signal CLKE provided by the seventh sub-clock signal line CLKE_1.

In addition, since the fourth sub-clock signal line CLKD_2 provides the fourth shift register circuit SC6 with the high-level fourth clock signal CLKD, the eighth sub-clock signal line CLKE_2 provides the sixth shift register circuit SC6 with the high-level fourth Since the five clock signal CLKE, the sixth shift register circuit SC6 outputs the high-level first drive signal OUT1<6> and the second drive signal OUT2<6>. Thus, although the first pull-up node H<5> in the third register A3 is still low, the sixth row of sub-pixels will not be compensated.

It can be understood that for the third shift register A3, the fifth shift register circuit SC5 and the sixth shift register circuit SC6 both receive the blanking input signal (corresponding to the voltage of H<5>) provided by the compensation selection module 100 . When the fifth row and the sixth row of sub-pixels need to be compensated simultaneously during the blanking phase of a frame, the clock signal provided by the corresponding sub-clock signal line can also be changed, so that the sixth shift register circuit SC6 can also Under the control of the clock signal, the corresponding driving signal is output in the blanking phase to drive the sensing transistor to work, thereby achieving the compensation for the sub-pixels in the sixth row. Based on this, the gate driving circuit 30 can compensate multiple rows of sub-pixels simultaneously.

In the 9th period, the fourth clock signal CLKD and the fifth clock signal CLKE both become high level, the shift signal output terminal CR<5>, the first drive signal output terminal OUT1<5> and the second drive signal output Both OUT2<5> output high level signal. Due to the equational transition of the voltage across the second capacitor C2 and the third capacitor C3, the voltage of the first node Q<5> rises by an amplitude, but is still low.

In the tenth period, the blanking reset signal line TRST provides a low-level signal to the blanking reset signal terminal TRST, and the fifth transistor M5 is turned on to reset the first node Q<5> to a high level. The compensation selection control signal OE is also a low level, the first transistor M1 is turned on, and the voltage of the first control node H<5> is reset using a high-level shift signal CR<5>.

The drive timing of 1F in one frame ends. For subsequent driving of the gate driving circuit in other stages such as other frames, reference may be made to the above description, and details are not repeated here.

It should be noted that, in the above description of the working principle of random compensation, the driving signal corresponding to the fifth row of sub-pixels of the display panel is output as an example for description in the blanking phase of the first frame, but this disclosure does not make any limited. For example, when it is necessary to compensate for the i-th row of sub-pixels of the display panel during the blanking phase of a frame, during the display phase of the frame, the timing of the compensation selection control signal OE and the i-th shift register circuit are included. The timing of the shift signal CR received by the compensation selection circuit of the shift register is the same, so as to control and maintain the voltage of the first control node of the shift register, and then in the blanking stage, pass the i-th shift register circuit Correspondingly controls the i-th shift register circuit to output a driving signal to drive the sensing transistor to perform compensation for the i-th row of sub-pixels. It should be noted here that the same timing of the two signals refers to time synchronization at a low level, and does not require the same amplitude of the two signals.

On the other hand, the embodiments of the present disclosure also provide an array substrate. The array substrate may include a gate driving circuit according to an embodiment of the present disclosure. In addition, the embodiments of the present disclosure also provide a display device including the above array substrate. In an embodiment, the display device may be any product or component with a display function such as a liquid crystal panel, an LCD TV, a display, an OLED panel, an OLED TV, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, etc. .

In addition, the embodiments of the present disclosure also provide a method for driving a shift register.

FIG. 10 shows a schematic flowchart of a method for driving a shift register according to an embodiment of the present disclosure. The shift register may be any applicable shift register based on the embodiments of the present disclosure.

In step 1010, the compensation selection circuit may provide a blanking input signal to the holding circuit and the shift register circuit according to the compensation selection control signal and one of the N shift signals output from the N shift signal output terminals. In an embodiment, when compensation is required for a row of sub-pixels, the timing of the compensation selection control signal and the shift signal received by the compensation selection circuit of the shift register including the corresponding shift register circuit may be controlled in step 1010 The timing of is the same, so as to control the voltage of the first control node of the shift register. Then, the compensation selection circuit supplies the received shift signal as a blanking input signal to the holding circuit and the shift register circuit according to the compensation selection control signal.

In step 1020, the holding circuit may hold the blanking input signal.

Furthermore, in an embodiment, in the display stage, the display input circuit may provide the display pull-down signal to the first node according to the display input signal. According to the voltage of the first node, N shift signals are output from N shift signal output terminals, and N first drive signals are output from N first drive signal output terminals. The first driving signal can be used to drive the sub-pixels for display.

In step 1030, the blanking input circuit may provide the blanking pull-down signal to the first node according to the blanking input signal and the blanking control signal.

At step 1040, according to the voltage of the first node, N shift signals are output from the N shift signal output terminals, and N first drive signals are output from the N first drive signal output terminals. Thus, the first driving signal can be used to compensate the sub-pixels.

Those skilled in the art can understand that although the above steps are described in order, they do not constitute a limitation on the order of the methods, and the embodiments of the present disclosure can also be implemented in any other suitable order.

Several embodiments of the present disclosure have been described in detail above, but the scope of protection of the present disclosure is not limited thereto. Obviously, those of ordinary skill in the art can make various modifications, substitutions, or variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the appended claims.

Claims

A shift register includes a compensation selection circuit, a holding circuit and N shift register circuits;

Wherein, the holding circuit is configured to hold the blanking input signal;

Each of the N shift register circuits includes:

A blanking input circuit configured to provide a blanking pull-down signal to the first node according to the blanking input signal and the blanking control signal;

An output circuit configured to output a shift signal from the shift signal output terminal and a first drive signal from the first drive signal output terminal according to the voltage of the first node;

The compensation selection circuit is configured to, according to the compensation selection control signal and the shift signal output by one of the N shift register circuits, pass the first control node to the holding circuit and the N shift register circuits provide the blanking input signal;

Among them, N is a natural number greater than 1.
The shift register according to claim 1, wherein the holding circuit includes a first capacitor;

The first terminal of the first capacitor is coupled to the first control node, and the other terminal is coupled to the second voltage terminal to receive the second voltage.
The shift register according to claim 1, wherein the compensation selection circuit includes a first transistor;

Wherein, the control electrode of the first transistor and the compensation selection control signal terminal are coupled to receive the compensation selection control signal, and the first electrode of the first transistor and one of the N shift register circuits are shifted The shift signal output terminal of the register circuit is coupled, and the second electrode of the first transistor is coupled to the first control node.
The shift register according to claim 1, wherein the blanking input circuit includes a second transistor and a third transistor,

Wherein, the control electrode of the second transistor is coupled to the first control node, and the first electrode of the second transistor is coupled to the first voltage terminal to receive the first voltage as the blanking pull-down signal , The second electrode of the second transistor is coupled to the first electrode of the third transistor;

The control electrode of the third transistor is coupled to the first clock signal terminal to receive the first clock signal as the blanking control signal, and the second electrode of the third transistor is coupled to the first node.
The shift register according to claim 1, wherein the output circuit includes: a nineteenth transistor, a twenty-second transistor, and a second capacitor;

Wherein, the control electrode of the nineteenth transistor is coupled to the first node, the first electrode of the nineteenth transistor and the fourth clock signal terminal are coupled to receive a fourth clock signal, the nineteenth The second pole of the transistor is coupled to the output terminal of the shift signal;

The control electrode of the twenty-second transistor is coupled to the first node, and the first electrode of the twenty-second transistor is coupled to the fourth clock signal terminal to receive a fourth clock signal. The second electrode of the twenty-two transistor is coupled to the first driving signal output terminal;

The second capacitor is coupled between the first node and the shift signal output terminal.
The shift register according to claim 1, wherein each of the shift register circuits further includes a display input circuit;

Wherein, the display input circuit is configured to provide a display pull-down signal to the first node according to a display input signal.
The shift register according to claim 6, wherein the display input circuit includes a fourth transistor;

Wherein, the control electrode of the fourth transistor and the display input signal terminal are coupled to receive the display input signal, and the first electrode and the first voltage terminal of the fourth transistor are coupled to receive the first voltage as the display Pulling down the signal, the second electrode of the fourth transistor is coupled to the first node.
The shift register according to any one of claims 1 to 7, wherein each of the shift register circuits further includes a first control circuit, a pull-up circuit, and a second control circuit;

Wherein, the first control circuit is configured to control the voltage of the pull-up node according to the voltage of the first node;

The pull-up circuit is configured to provide a second voltage from a second voltage terminal to the first node, the shift signal output terminal, and the first drive signal output terminal according to the voltage of the pull-up node ;

The second control circuit is configured to control the voltage of the pull-up node according to the blanking control signal and the voltage of the first control node, and to control the voltage of the pull-up node according to the display input signal.
The shift register according to claim 8, wherein the pull-up node comprises a first pull-up node;

Wherein, the first control circuit includes:

A seventh transistor, the control electrode of the seventh transistor is coupled to the first electrode and the third voltage terminal, and the second electrode of the seventh transistor is coupled to the first pull-up node; and

An eighth transistor, the control electrode of the eighth transistor is coupled to the first node, the first electrode of the eighth transistor is coupled to the first pull-up node, and the second electrode of the eighth transistor Coupled to the second voltage terminal;

Wherein, the pull-up circuit includes:

A ninth transistor, the control electrode of the ninth transistor is coupled to the first pull-up node, the first electrode of the ninth transistor is coupled to the first node, and the second electrode of the ninth transistor Coupled to the second voltage terminal;

A twentieth transistor, the control electrode of the twentieth transistor is coupled to the first pull-up node, the first electrode of the twentieth transistor is coupled to the shift signal output terminal, and the second The second electrode of the ten transistor is coupled to the second voltage terminal; and

A twenty-third transistor, the control electrode of the twenty-third transistor is coupled to the first pull-up node, and the first electrode of the twenty-third transistor is coupled to the first drive signal output terminal, The second electrode of the twenty-third transistor is coupled to the second voltage terminal;

Wherein, the second control circuit includes:

A thirteenth transistor, the control electrode of the thirteenth transistor and the first clock signal terminal are coupled to receive the first clock signal as the blanking control signal, the first pole of the thirteenth transistor and the thirteenth transistor A pull-up node is coupled;

A fourteenth transistor, the control electrode of the fourteenth transistor is coupled to the first control node, the first electrode of the fourteenth transistor is coupled to the second electrode of the thirteenth transistor, the The second electrode of the fourteenth transistor is coupled to the second voltage terminal; and

A fifteenth transistor, a control electrode of the fifteenth transistor and a display input signal terminal are coupled to receive the display input signal, and a first electrode of the fifteenth transistor is coupled to the first pull-up node, The second electrode of the fifteenth transistor is coupled to the second voltage terminal.
The shift register according to claim 9, wherein the pull-up node further comprises a second pull-up node;

Wherein, the first control circuit further includes:

A tenth transistor, the control electrode of the tenth transistor is coupled to the first electrode and the fourth voltage terminal, and the second electrode of the tenth transistor is coupled to the second pull-up node; and

An eleventh transistor, the control electrode of the eleventh transistor is coupled to the first node, the first electrode of the eleventh transistor is coupled to the second pull-up node, and the eleventh transistor Is coupled to the second pole of the second voltage terminal;

Wherein, the pull-up circuit also includes:

A twelfth transistor, the control electrode of the twelfth transistor is coupled to the second pull-up node, the first electrode of the twelfth transistor is coupled to the first node, and the twelfth transistor Is coupled to the second pole of the second voltage terminal;

A twenty-first transistor, the control pole of the twenty-first transistor is coupled to the second pull-up node, and the first pole of the twenty-first transistor is coupled to the shift signal output terminal. The second electrode of the twenty-one transistor is coupled to the second voltage terminal; and

A twenty-fourth transistor, the control pole of the twenty-fourth transistor is coupled to the second pull-up node, the first pole of the twenty-fourth transistor is coupled to the first drive signal output, The second pole of the twenty-fourth transistor is coupled to the second voltage terminal;

Wherein, the second control circuit further includes:

A sixteenth transistor, the control electrode of the sixteenth transistor and the first clock signal terminal are coupled to receive the first clock signal as the blanking control signal, the first electrode of the sixteenth transistor and the first Two pull-up nodes are coupled;

A seventeenth transistor, a control electrode of the seventeenth transistor is coupled to the first control node, a first electrode of the seventeenth transistor is coupled to a second electrode of the sixteenth transistor, the The second electrode of the seventeenth transistor is coupled to the second voltage terminal; and

An eighteenth transistor, the control electrode of the eighteenth transistor is coupled to the display input signal terminal to receive the display input signal, and the first electrode of the eighteenth transistor is coupled to the second pull-up node, The second electrode of the eighteenth transistor is coupled to the second voltage terminal.
The shift register according to claim 8, wherein each of the shift register circuits further includes a reset circuit;

Wherein, the reset circuit is configured to reset the first node according to a blanking reset signal from a blanking reset signal terminal, and reset the first node according to a display reset signal from a display reset signal terminal.
The shift register according to claim 11, wherein the reset circuit includes a fifth transistor and a sixth transistor;

The control electrode of the fifth transistor is coupled to the blanking reset signal terminal, the first electrode of the fifth transistor is coupled to the first node, and the second electrode of the fifth transistor is coupled to the first Two voltage terminals are coupled;

The control electrode of the sixth transistor is coupled to the display reset signal terminal, the first electrode of the sixth transistor is coupled to the first node, the second electrode of the sixth transistor and the second The voltage terminal is coupled.
The shift register according to claim 10, wherein the output circuit further comprises a twenty-fifth transistor and a third capacitor;

The control electrode of the twenty-fifth transistor is coupled to the first node, the first electrode of the twenty-fifth transistor and the fifth clock signal terminal are coupled to receive a fifth clock signal, the twentieth The second electrode of the five transistors is coupled to the second driving signal output terminal;

The third capacitor is coupled between the first node and the second driving signal output terminal.
The shift register according to claim 13, wherein the pull-up circuit further includes a twenty-sixth transistor and a twenty-seventh transistor;

Wherein, the control electrode of the twenty-sixth transistor is coupled to the first pull-up node, the first electrode of the twenty-sixth transistor is coupled to the second driving signal output terminal, and the second The second electrode of the sixteen transistor is coupled to the second voltage terminal;

The control pole of the twenty-seventh transistor is coupled to the second pull-up node, the first pole of the twenty-seventh transistor is coupled to the second drive signal output terminal, and the twenty-seventh The second electrode of the transistor is coupled to the second voltage terminal.
The shift register according to claim 1, wherein the shift register includes a compensation selection circuit and a holding circuit.
A gate drive circuit, comprising M shift registers according to any one of claims 1 to 15 and a first sub-clock signal line;

Wherein, the first sub-clock signal line provides a compensation selection control signal to each shift register.
The gate driving circuit according to claim 16, further comprising a second sub-clock signal line and a blanking reset signal line;

Among them, the shift signal output by the i-th shift register circuit is provided to the i+2th shift register circuit as a display input signal;

The second sub-clock signal line provides a first clock signal to each shift register circuit;

The blanking reset signal line provides a blanking reset signal to each shift register circuit;

The shift signal output from the i+3th shift register circuit is supplied to the i th shift register circuit as a display reset signal.
The gate driving circuit according to claim 16 or 17, further comprising a third sub-clock signal line, a fourth sub-clock signal line, a fifth sub-clock signal line, and a sixth sub-clock signal line;

Wherein, the third sub-clock signal line provides a fourth clock signal to the 4i-3th shift register circuit;

The fourth sub-clock signal line provides a fourth clock signal to the 4i-2th shift register circuit;

The fifth sub-clock signal line provides a fourth clock signal to the 4i-1th shift register circuit;

The sixth sub-clock signal line provides a fourth clock signal to the 4ith shift register circuit.
The gate driving circuit according to claim 16 or 17, further comprising a seventh subclock signal line, an eighth subclock signal line, a ninth subclock signal line, and a tenth subclock signal line;

Wherein, the seventh sub-clock signal line provides a fifth clock signal to the 4i-3th shift register circuit;

The eighth sub-clock signal line provides a fifth clock signal to the 4i-2th shift register circuit;

The ninth sub-clock signal line provides a fifth clock signal to the 4i-1th shift register circuit;

The tenth sub-clock signal line provides a fifth clock signal to the 4ith shift register circuit.
An array substrate comprising the gate drive circuit according to any one of claims 16 to 19.
A display device comprising the array substrate according to claim 20.
A method for driving a shift register according to any one of claims 1 to 15, comprising:

According to the compensation selection control signal and one of the N shift signals, a blanking input signal is provided;

Maintaining the blanking input signal;

Providing a blanking pull-down signal to the first node according to the blanking input signal and the blanking control signal; and

According to the voltage of the first node, N shift signals are output from N shift signal output terminals, and N first drive signals are output from N first drive signal output terminals.