CN112041688A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
CN112041688A
CN112041688A CN201980027259.6A CN201980027259A CN112041688A CN 112041688 A CN112041688 A CN 112041688A CN 201980027259 A CN201980027259 A CN 201980027259A CN 112041688 A CN112041688 A CN 112041688A
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silicon oxide
oxide film
gas discharge
silicon
discharge path
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CN201980027259.6A
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CN112041688B (en
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铃木爱美
山本康雄
明石照久
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Denso Corp
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Denso Corp
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Priority claimed from JP2019055127A external-priority patent/JP6897703B2/en
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00277—Processes for packaging MEMS devices for maintaining a controlled atmosphere inside of the cavity containing the MEMS
    • B81C1/00293—Processes for packaging MEMS devices for maintaining a controlled atmosphere inside of the cavity containing the MEMS maintaining a controlled atmosphere with processes not provided for in B81C1/00285
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00349—Creating layers of material on a substrate
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
    • G01C19/00—Gyroscopes; Turn-sensitive devices using vibrating masses; Turn-sensitive devices without moving masses; Measuring angular rate using gyroscopic effects
    • G01C19/56—Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces
    • G01C19/5783—Mountings or housings not specific to any of the devices covered by groups G01C19/5607 - G01C19/5719
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
    • G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
    • G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
    • G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
    • H01L23/08—Containers; Seals characterised by the material of the container or its electrical properties the material being an electrical insulator, e.g. glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/84—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by variation of applied mechanical force, e.g. of pressure
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
    • B81C2201/019—Bonding or gluing multiple substrate layers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/03—Bonding two components
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
    • G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
    • G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
    • G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
    • G01P15/0802—Details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
    • G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
    • G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
    • G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
    • G01P15/125—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values by capacitive pick-up

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
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  • Radar, Positioning & Navigation (AREA)
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  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Micromachines (AREA)
  • Pressure Sensors (AREA)

Abstract

Recesses (14, 23) are formed in at least 1 of the silicon substrates (11, 13, 21). In addition, silicon oxide films (12, 22) are formed on at least 1 of the plurality of silicon substrates at a portion separated from a region to be formed of the space (30), and grooves (17, 28) are formed in the silicon oxide films (12, 22) so as to surround the region to be formed and reach the outer peripheries of the plurality of silicon substrates. Further, the silicon substrate having the silicon oxide film formed therein and another silicon substrate among the silicon substrates are bonded by direct bonding via the silicon oxide film so as to cover the groove portion, a gas discharge path (40) is formed, a laminated structure of the silicon substrates and the silicon oxide film is formed, and a space is formed inside the laminated structure by the recess portion. Then, the gas in the space is discharged to the outside of the laminated structure through the gas discharge passage by the heat treatment.

Description

Method for manufacturing semiconductor device
Cross reference to related applications
The present application is based on japanese patent application No. 2018-5, 24, 2018 and japanese patent application No. 2019-55127, 22, 3, 2019, the disclosures of which are incorporated herein by reference.
Technical Field
The present invention relates to a method for manufacturing a semiconductor device having a space formed therein.
Background
As such a semiconductor device, for example, there is an acceleration sensor in which a fixed electrode formed on a support substrate and a movable electrode displaceable relative to the support substrate are arranged in an internal space, and acceleration is detected by using a change in capacitance between the electrodes when the movable electrode is displaced. Further, an angular velocity sensor may be used that vibrates a part of the substrate as a deformable movable portion in an internal space and detects a displacement amount of the movable portion when an angular velocity is applied to the substrate to detect the angular velocity.
In order to improve the performance of these sensors, it is important to set the pressure in the space where the movable electrode and the like are arranged to a pressure suitable for the application.
In contrast, for example, patent document 1 proposes a method of suppressing pressure variation due to residual gas caused by the manufacturing process by enlarging the internal space.
Documents of the prior art
Patent document
Patent document 1: japanese patent laid-open No. 2014-173961
Disclosure of Invention
However, according to the method described in patent document 1, since the gas remains in the internal space, it is difficult to make the internal space to have a low pressure of 100Pa or less, for example, about 10 Pa.
In view of the above problems, an object of the present invention is to provide a method for manufacturing a semiconductor device in which an internal space can be made lower than a conventional one.
In 1 aspect of the present invention, a method for manufacturing a semiconductor device having a space (30) formed therein includes: preparing a plurality of silicon substrates (11, 13, 21); forming a recess (14, 23) in at least 1 of the plurality of silicon substrates; forming a silicon oxide film (12, 22) on at least 1 of the plurality of silicon substrates at a portion separated from a region to be formed in the space, the silicon oxide film (12, 22) having a groove portion (17, 28) that surrounds the region to be formed and reaches the outer periphery of the plurality of silicon substrates; bonding a silicon substrate having a silicon oxide film formed thereon of the plurality of silicon substrates and another silicon substrate of the plurality of silicon substrates by direct bonding via the silicon oxide film so as to cover the groove portion, forming a gas discharge path (40) and forming a laminated structure of the plurality of silicon substrates and the silicon oxide film, and forming a space inside the laminated structure by the recess portion; after the space is formed, the gas in the space is discharged to the outside of the laminated structure through the gas discharge passage by the heat treatment.
In this way, after the substrates are bonded to form the laminated structure and the space inside the laminated structure, the gas inside the space is discharged to the outside of the laminated structure through the gas discharge passage, and therefore the internal space can be made lower in pressure than in the conventional case. By such a manufacturing method, a semiconductor device having a laminated structure of the support layer, the 1 st silicon oxide film, the active layer, the 2 nd silicon oxide film, and the cap layer and having an element portion in a space is manufactured. Since such a semiconductor device is in a state in which the residual gas is discharged through the gas discharge path, the performance of the semiconductor device can be improved.
The reference numerals with parentheses given to the respective components and the like indicate an example of correspondence between the components and the like and specific components and the like described in the embodiments to be described later.
Drawings
Fig. 1 is a sectional view of a semiconductor device according to embodiment 1.
Fig. 2 is an enlarged view of a portion II of fig. 1.
Fig. 3A is a sectional view showing a manufacturing process of the sensor portion.
Fig. 3B is a sectional view showing a manufacturing process of the sensor portion next to fig. 3A.
Fig. 3C is a sectional view showing a manufacturing process of the sensor portion, which follows fig. 3B.
Fig. 3D is a sectional view showing a manufacturing process of the sensor portion, which follows fig. 3C.
Fig. 3E is a sectional view showing a manufacturing process of the sensor portion, which follows fig. 3D.
Fig. 4A is a sectional view showing a manufacturing process of the lid portion.
Fig. 4B is a sectional view showing a manufacturing process of the lid portion next to fig. 4A.
Fig. 4C is a sectional view showing a manufacturing process of the lid portion next to fig. 4B.
Fig. 4D is a sectional view showing a manufacturing process of the lid portion, which follows fig. 4C.
Fig. 4E is a sectional view showing a manufacturing process of the lid portion, which follows fig. 4D.
Fig. 5 is a plan view of the insulating layer.
Fig. 6A is a cross-sectional view showing a bonding step.
Fig. 6B is a cross-sectional view showing the joining step following fig. 6A.
Fig. 7 is an enlarged view of a VII portion of fig. 6.
Fig. 8 is a diagram showing the results of an experiment investigating the presence or absence of a gas discharge path and the discharge efficiency of residual gas in a space.
Fig. 9 is a cross-sectional view of the semiconductor device according to embodiment 2, which corresponds to fig. 2.
Fig. 10A is a sectional view showing a manufacturing process of the lid portion according to embodiment 2.
Fig. 10B is a sectional view showing a manufacturing process of the lid portion next to fig. 10A.
Fig. 10C is a sectional view showing a manufacturing process of the lid portion next to fig. 10B.
Fig. 10D is a sectional view showing a manufacturing process of the lid portion next to fig. 10C.
Fig. 10E is a sectional view showing a manufacturing process of the lid portion next to fig. 10D.
Fig. 11 is a sectional view showing a manufacturing process of the semiconductor device according to embodiment 2, and corresponds to fig. 7.
Fig. 12 is a sectional view showing a manufacturing process of a semiconductor device according to another embodiment, and corresponds to fig. 7.
Fig. 13 is a sectional view showing a manufacturing process of a semiconductor device according to another embodiment, and corresponds to fig. 7.
Fig. 14 is a sectional view showing a manufacturing process of a semiconductor device according to another embodiment, and corresponds to fig. 7.
Fig. 15 is a sectional view showing a manufacturing process of a semiconductor device according to another embodiment, and corresponds to fig. 7.
Fig. 16 is a sectional view showing a manufacturing process of a semiconductor device according to another embodiment, and corresponds to fig. 7.
Fig. 17 is a sectional view showing a manufacturing process of a semiconductor device according to another embodiment, and corresponds to fig. 7.
Fig. 18 is a sectional view showing a manufacturing process of a semiconductor device according to another embodiment, and corresponds to fig. 7.
Fig. 19 is a plan view of an insulating layer of another embodiment.
Detailed Description
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent portions are given the same reference numerals and will be described.
(embodiment 1)
Embodiment 1 will be explained. The semiconductor device of the present embodiment is a physical quantity sensor manufactured using mems (micro electro mechanical systems), and includes a sensor portion 10 and a lid portion 20 directly bonded to the sensor portion 10, as shown in fig. 1.
The sensor unit 10 is formed by sequentially laminating a support layer 11 made of silicon (Si) and a silicon oxide film (SiO)2) An soi (silicon on insulator) structure including an insulating layer 12 and an active layer 13 made of Si. The supporting layer 11 is electrically insulated from the active layer 13 by the insulating layer 12.
The surface of the support layer 11 is formed with a recess 14, and the insulating layer 12 is formed so as to cover the surface of the support layer 11 and the inner wall surface of the recess 14. The active layer 13 is bonded to the surface of the support layer 11 by surface-activated bonding via the insulating layer 12. As described above, the sensor unit 10 of the present embodiment has a cavity SOI structure in which a space is formed between the support layer 11 and the insulating layer 12, and the active layer 13.
A part of the active layer 13 located above the recess 14 is removed, and the remaining part is set as an element portion 15. The element portion 15 is displaceable relative to the portion of the active layer 13 that is engaged with the support layer 11.
For example, by forming a movable electrode in the element portion 15, forming a fixed electrode in the insulating layer 12 formed in the recess 14 or the recess 23 described later, and detecting a change in capacitance between these electrodes, the semiconductor device can be used as an acceleration sensor. Further, by configuring the element portion 15 to vibrate so as to be able to detect the displacement amount of the element portion 15 when an angular velocity is applied to the element portion 15, the semiconductor device can be used as an angular velocity sensor.
The lid portion 20 protects the element portion 15, and includes a substrate 21 made of Si. SiO is formed on the back surface of the substrate 212 An insulating layer 22 is formed. The substrate 21 is bonded to the active layer 13 by surface activation bonding via the insulating layer 22. The active layer 13 and the substrate 21 are electrically insulated by an insulating layer 22.
In a portion of the lid 20 facing the recess 14, the insulating layer 22 and a portion of the substrate 21 are removed to form a recess 23. In the semiconductor device, a space 30 is formed by the recess 14 and the recess 23, and the element portion 15 is disposed in the space 30.
As shown in fig. 2, a gas discharge path 40 is formed in a portion outside the space 30 in the insulating layer 22. The gas discharge path 40 is formed to discharge the gas in the space 30 to the outside of the semiconductor device, and is formed to surround the space 30 and reach the outside of the semiconductor device.
As shown in fig. 1, the lid portion 20 is formed with a through electrode for applying an electric signal to the element portion 15 and obtaining an output of the element portion 15.
Specifically, insulating film 24 is formed on the surface of substrate 21, and through-hole 25 penetrating substrate 21, insulating layer 22, and insulating film 24 is formed in a portion outside space 30 in lid 20. An insulating film 26 is formed on the inner wall surface of the through hole 25. At the bottom of the through hole 25, the insulating film 26 is removed, and an electrode film 27 is formed so as to cover the surface of the active layer 13 exposed from the insulating film 26 and the surface of the insulating film 26 and reach the upper portion of the insulating film 24.
The electrode film 27 is electrically connected to the element portion 15, and can apply an electric signal to the element portion 15 via the electrode film 27 to obtain an output of the element portion 15. In fig. 1, only 1 through-electrode is shown, but the number of through-electrodes required for the element portion 15 to function is formed in the lid portion 20.
A method for manufacturing a semiconductor device will be described. First, a method for manufacturing the sensor unit 10 will be described with reference to fig. 3A to 3E. In the step shown in fig. 3A, an Si wafer constituting the support layer 11 is prepared, and a resist 51 having a shape corresponding to the recess 14 is formed on the surface of the support layer 11 by photolithography. Then, a part of the support layer 11 is removed by drie (deep Reactive Ion etching) using the resist 51 as a mask, thereby forming the concave portion 14.
In the step shown in fig. 3B, the resist 51 is stripped by stripping (ashing), and the wafer is cleaned. Then, the support layer 11 is thermally oxidized to form SiO on the surface of the support layer 112An insulating layer 12 formed on the back surface of the supporting layer 11 and made of SiO2And an insulating film 16.
In the step shown in fig. 3C, an Si wafer constituting the active layer 13 is prepared, and the support layer 11 and the active layer 13 are bonded by surface active bonding. Specifically, after the bonding surface between the support layer 11 and the active layer 13 is activated by oxygen plasma, the support layer 11 and the active layer 13 are exposed to the atmosphere, and moisture in the atmosphere is adsorbed to the bonding surface between the support layer 11 and the active layer 13, thereby modifying the OH groups. The support layer 11 and the active layer 13 are bonded to each other. In addition, the bonding strength can be improved by performing heat treatment as needed.
In the step shown in fig. 3D, the active layer 13 is polished to be thin, and then the wafer is cleaned. Then, a resist 52 having a shape corresponding to the element portion 15 is formed on the surface of the active layer 13 by photolithography.
In the step shown in fig. 3E, a part of the active layer 13 is removed by DRIE using the resist 52 as a mask. Then, the resist 52 is stripped by the photoresist stripping, and the wafer is cleaned. Thereby, the element portion 15 is formed in the portion of the active layer 13 located above the recess 14.
Next, a method for manufacturing the lid 20 will be described with reference to fig. 4A to 4E. In the step shown in fig. 4A, a Si wafer constituting the substrate 21 is prepared, and the substrate 21 is thermally oxidized to form SiO on the back surface of the substrate 212 An insulating layer 22 formed on the surface of the substrate 21 and made of SiO2And an insulating film 24. Then, a resist 53 having a shape corresponding to the gas discharge path 40 is formed on the insulating layer 22 by photolithography. Then, a part of the insulating layer 22 is removed by rie (reactive Ion etching) using the resist 53 as a mask, thereby forming the groove 28. The groove 28 is formed over the entire surface of the wafer so as to surround a region to be formed of the recess 23 and reach the outer periphery of the wafer.
In the step shown in fig. 4B, the resist 53 is removed by oxygen stripping, and the wafer is cleaned. Thereby, the insulating layer 22 is exposed. In the step shown in fig. 4C, a resist 54 having a shape corresponding to the recess 23 is formed on the insulating layer 22 by photolithography. Then, a part of the insulating layer 22 is removed by etching using the resist 54 as a mask. Thereby, a part of the substrate 21 is exposed.
In the step shown in fig. 4D, a part of the substrate 21 is removed by DRIE using the resist 54 as a mask, thereby forming the concave portion 23. In the step shown in fig. 4E, the resist 54 is removed by oxygen stripping, and the wafer is cleaned. Thereby, the insulating layer 22 is exposed.
A plan view of the insulating layer 22 after the resist 54 is removed is shown in fig. 5. That is, a plurality of recesses 23 are arranged in a grid pattern, and a groove 28 is formed so as to surround the periphery of each recess 23. In the present embodiment, two linear groove portions 28 are formed between two adjacent concave portions 23.
After the steps shown in fig. 3A to 3E and fig. 4A to 4E, the sensor portion 10 and the lid portion 20 are joined by the steps shown in fig. 6A and 6B. In the step shown in fig. 6A, wlp (wafer Level packaging) is performed. Specifically, the active layer 13 and the insulating layer 22 are bonded by surface activation bonding in a vacuum. Thereby, a space 30 surrounded by the concave portions 14 and the concave portions 23 is formed, and the element portion 15 is enclosed in the space 30.
Further, when the surface activation treatment is performed, moisture and nitrogen in the atmosphere are adsorbed on the wafer surface after the exposure to the atmosphere. When the heat treatment is performed after the bonding, the adsorbed water is decomposed into hydrogen and oxygen, and the oxygen enters the oxide film, leaving the hydrogen in the space 30. Further, nitrogen is desorbed from the inner wall surface of the space 30 by the heat treatment, and is released into the space 30. In this way, residual gas containing hydrogen, nitrogen, and the like, which is caused by the manufacturing process, is enclosed in the space 30.
In the step shown in fig. 6A, as shown in fig. 7, the groove 28 is covered with the active layer 13, and a fine void surrounded by the active layer 13, the substrate 21, and the insulating layer 22 is formed outside the space 30. The gap serves as a gas discharge path 40 for discharging the residual gas.
In the step shown in fig. 6B, the gas component inside the wall surface of the space 30 or in the vicinity of the wall surface is activated and desorbed from the wall surface of the space 30 by high-temperature annealing in a nitrogen atmosphere. Then, the high temperature annealing in nitrogen environment is continued to activate the residual gas and follow the Si and SiO with the lowest energy barrier2Moves to the gas exhaust path 40. Reaches the gas discharge passageThe residual gas in the path 40 is exhausted to the outside of the wafer through the gas exhaust path 40. This reduces the pressure in the space 30, and the space 30 becomes a high vacuum. The amount of the residual gas to be discharged can be controlled by the heat treatment conditions.
Then, annealing in an oxygen atmosphere is performed, and an oxide film is formed on the active layer 13 and the substrate 21 exposed to the gas exhaust path 40 by oxygen inside the wafer. As a result, as shown in fig. 2, the gas discharge path 40 is blocked, and the inflow of gas from the outside is suppressed. Note that, although the gas discharge path 40 described here is blocked, the gas discharge path 40 may be partially and completely blocked, but this means that the active layer 13 and the substrate 21 are not exposed to the gas discharge path 40, and their exposed surfaces are covered with the insulating layer 22. In other words, the gas discharge path 40 is formed at a position away from the active layer 13 and the substrate 21. Therefore, even after the gas discharge path 40 is clogged, the gas discharge path 40 can be confirmed if infrared microscope observation or electron microscope observation is performed. Further, there are also cases where: the wafer is finally divided into chip units by dicing, but in the cut surface, silicon, glass pieces, or the like enter the gas discharge path 40, and the gas discharge path 40 cannot be visually recognized. In this case, the gas discharge path 40 can be confirmed by infrared microscope observation or electron microscope observation. That is, after dicing, the gas discharge path 40 is also formed to reach the outer periphery of the substrate 21 and the like.
After the gas discharge path 40 is blocked, the insulating film 16 is removed by etching. Further, a through electrode is formed on the lid 20. Specifically, a resist having a shape corresponding to the through-hole 25 is formed on the surface of the insulating film 24, and the through-hole 25 penetrating the substrate 21, the insulating layer 22, and the insulating film 24 is formed by etching using the resist as a mask. After the insulating film 26 is formed on the inner wall surface of the through hole 25 by thermal oxidation, the insulating film 26 formed on the bottom of the through hole 25 is removed by etching, thereby exposing the active layer 13. Then, an electrode film 27 is formed by sputtering or the like so as to cover the active layer 13 and the insulating film 26 and reach the upper portion of the insulating film 24. This forms a through electrode, and can apply a signal to the element portion 15.
After the removal of the insulating film 16 and the formation of the through-electrodes, dicing is performed to divide the wafer into chip units. Thus, a semiconductor device is manufactured.
As described above, in the present embodiment, the gas discharge path 40 for discharging the residual gas in the space 30 is formed, and the heat treatment is performed after the sensor portion 10 and the lid portion 20 are joined, whereby the residual gas in the space 30 can be discharged to the outside of the wafer, and the space 30 can be made into a high vacuum. Further, the pressure fluctuation due to the desorption of the gas adsorbed on the inner wall surface of the space 30 can be suppressed.
Further, by controlling the amount of the residual gas to be discharged in accordance with the heat treatment conditions, the pressure inside the space 30 can be set to a desired pressure, and the performance of the semiconductor device can be improved. For example, in an acceleration sensor, an angular velocity sensor, or the like, the sensitivity can be improved.
Further, by blocking the gas discharge path 40 after the discharge of the residual gas, the inflow and outflow of the gas can be suppressed, and the internal pressure can be stably maintained for a long period of time. This stabilizes the performance of the semiconductor device over a long period of time.
On the other hand, since the residual gas can be exhausted to the outside of the wafer by using the gas exhaust path 40 of fig. 7, annealing in an oxygen atmosphere may be performed as needed, and the same effect as that of the gas exhaust path 40 of fig. 2 can be obtained even in the form of the gas exhaust path 40 of fig. 7. In this case, the lid 20 and the active layer 13 are exposed at the position where the gas discharge path 40 is formed, and the lid 20, the active layer 13, and the insulating layer 22 constitute the gas discharge path 40.
In addition, in this embodiment mode, since a getter (getter) film is not used to remove the residual gas, the manufacturing cost of the semiconductor device can be reduced as compared with the case of using a getter film.
Through experiments, the presence or absence of the gas discharge path 40 and the discharge efficiency of the residual gas in the space 30 were investigated. As a result, the results shown in FIG. 8 were obtained. In this experiment, annealing was performed at 1050 ℃ for 20 hours at maximum, and the change in pressure in the space 30 was investigated. The pressure ratio in the figure is represented as a ratio to the pressure at that time, assuming that the internal pressure in the space 30 is the highest, as 100%.
As shown in the figure, when the gas discharge passage 40 is present, the pressure drop rate is high, and the pressure can be reduced to about 10% compared to that before annealing. Therefore, it is understood that the residual gas can be appropriately discharged. The pressure in the space 30 when annealing was performed at 1050 ℃ for 20 hours was 94 Pa. Therefore, by providing the gas discharge path 40, the pressure in the space 30 can be set to 100Pa or less, and a high vacuum state can be achieved. When the pressure in the space 30 can be set to 100Pa or less, the Q value at the time of detecting the physical quantity in the element unit 15 becomes a value higher than 5000, and is higher than the Q value in the case of exceeding 100Pa by about 1 digit. Therefore, the vibration characteristics of the element portion 15 can be improved, and the leakage vibration (noise) can be reduced, so that the physical quantity can be detected with high accuracy.
In contrast, in the case where the gas discharge path 40 is not provided, the pressure drop rate is low, and the pressure does not change much even when annealing is performed. Therefore, it is found that the residual gas cannot be appropriately discharged. In this way, if the gas discharge path 40 is not provided, the residual gas cannot be sufficiently discharged. Therefore, it is difficult to detect the physical quantity with high accuracy.
In the case where the gas discharge path 40 is not provided, the pressure in the space 30 is the highest when the annealing is performed for 5 hours, and therefore the pressure at this time is expressed as a ratio of 100% of the pressure. If the residual gas can be appropriately exhausted by performing annealing, although the pressure before annealing is the highest, in the case where the gas exhaust path 40 is not provided, the residual gas is not appropriately exhausted, and therefore, the fluctuation of the pressure is small, and it is conceivable that such an error occurs.
(embodiment 2)
Embodiment 2 will be explained. The present embodiment is different from embodiment 1 in the configuration of the lid portion 20, and the rest is the same as embodiment 1, and therefore only the differences from embodiment 1 will be described.
As shown in fig. 9, in the present embodiment, a groove portion 29 as a base having a semicircular cross section is formed in the substrate 21. The insulating layer 22 is formed on the back surface of the substrate 21 and inside the groove portion 29, and the insulating layer 22 formed in the groove portion 29 is formed with a groove portion 28 having a semicircular cross section in accordance with the shape of the groove portion 29.
In the present embodiment, the lid portion 20 is manufactured by the steps shown in fig. 10A to 10E. In the step shown in fig. 10A, an Si wafer constituting the substrate 21 is prepared, and a resist 55 having a shape corresponding to the gas discharge path 40 is formed by photolithography on the back surface of the substrate 21 to be bonded to the sensor portion 10. Then, by isotropic etching using the resist 55 as a mask, a groove portion 29 having a semicircular cross section is formed in the substrate 21. The groove 29 is formed to surround a region to be formed of the recess 23 and reach the outer periphery of the substrate 21.
In the step shown in fig. 10B, the resist 55 is removed by oxygen stripping, and the wafer is cleaned to expose the back surface of the substrate 21. Then, the substrate 21 is thermally oxidized to form SiO on the back surface of the substrate 21 and inside the groove portion 292An insulating layer 22 formed on the surface of the substrate 21 and made of SiO2And an insulating film 24. At this time, the insulating layer 22 formed inside the groove portion 29 is formed with a groove portion 28 having a semicircular cross section in accordance with the shape of the groove portion 29.
In the step shown in fig. 10C, a resist 56 having a shape corresponding to the recess 23 is formed on the insulating layer 22 by photolithography. Then, a part of the insulating layer 22 is removed by RIE using the resist 56 as a mask. Thereby, a part of the substrate 21 is exposed.
In the step shown in fig. 10D, a part of the substrate 21 is removed by DRIE using the resist 56 as a mask, thereby forming the concave portion 23. In the step shown in fig. 10E, the resist 56 is removed by oxygen stripping, and the wafer is cleaned. Thereby, the insulating layer 22 is exposed.
After the step shown in fig. 10E, WLP is performed to bond the active layer 13 and the insulating layer 22. Thereby, the space 30 is formed as in embodiment 1, and the element portion 15 and the residual gas are enclosed in the space 30. Further, as shown in fig. 11, a fine gas discharge path 40 surrounded by the active layer 13 and the insulating layer 22 is formed outside the space 30.
After the active layer 13 and the insulating layer 22 are bonded, the residual gas in the space 30 is exhausted to the outside of the wafer through the gas exhaust passage 40, as in embodiment 1. Then, annealing in an oxygen atmosphere is performed, and an oxide film is formed on the active layer 13 exposed to the gas discharge path 40 by oxygen inside the wafer. As a result, as shown in fig. 9, the gas discharge path 40 is blocked, and inflow of gas from the outside is suppressed.
In the present embodiment in which the groove portion 29 is formed in the substrate 21 and the gas discharge path 40 is formed by the gap between the insulating layer 22 and the active layer 13 formed in the groove portion 29, the same effects as those of embodiment 1 can be obtained.
On the other hand, since the residual gas can be exhausted to the outside of the wafer by using the gas exhaust path 40 of fig. 11, annealing in an oxygen atmosphere may be performed as needed, and the same effect as that of the gas exhaust path 40 of fig. 9 can be obtained also in the form of the gas exhaust path 40 of fig. 11.
(other embodiments)
The present invention has been described in terms of the above embodiments, but is not limited to the embodiments, and various modifications and equivalent variations are also included. In addition, various combinations and forms, and further, other combinations and forms including only one element, more than one element, or less than one element are also within the scope and spirit of the present invention.
For example, as shown in fig. 12, the groove 17 may be formed by removing a part of the insulating layer 12, and the gas discharge path 40 may be formed by a space surrounded by the supporting layer 11, the insulating layer 12, and the active layer 13. After the step shown in fig. 3B, the gas discharge path 40 is formed by removing a portion of the insulating layer 12 corresponding to the gas discharge path 40 by photolithography and etching, and bonding the insulating layer 12 to the active layer 13. Of course, in the case of such a configuration, if necessary, annealing treatment in an oxygen atmosphere may be performed, and the surfaces of the active layer 13 and the support layer 11 may be covered with the insulating layer 12, so that the gas discharge path 40 may be formed at a position apart from the support layer 11 and the active layer 13.
In addition, although the groove 28 is formed to penetrate the insulating layer 22 in embodiment 1, the groove 28 may be formed to have a depth up to a halfway point in the thickness direction of the insulating layer 22 as shown in fig. 13, and the gas discharge path 40 may be configured by a void surrounded by the insulating layer 22 and the active layer 13. After the insulating layer 22 is half-etched in the step shown in fig. 4A to form the groove 28, the steps shown in fig. 4B to 4E and fig. 6A are performed in the same manner as in embodiment 1 to form such a gas discharge path 40. For example, by forming the groove portion 28 by wet isotropic etching, a gas discharge path having a semicircular cross section is formed as shown in fig. 13.
As shown in fig. 14, a gas discharge path 40 similar to that in fig. 13 may be formed between the insulating layer 12 and the active layer 13. Such a gas discharge path 40 is formed by performing the step shown in fig. 3C after the step shown in fig. 3B by half-etching the insulating layer 12 using a mask not shown.
As shown in fig. 15, a gas discharge path 40 similar to that of embodiment 2 may be formed in the sensor unit 10. That is, the groove portion 18 having a semicircular cross section may be formed on the surface of the support layer 11, and the gas discharge path 40 may be formed by a space surrounded by the insulating layer 12 and the active layer 13 formed inside the groove portion 18. Such a gas discharge path 40 is formed by forming a groove 18 in the support layer 11 at a portion outside the recess 14 by isotropic etching using a mask not shown after the step shown in fig. 3A, and performing the step shown in fig. 3C.
As shown in fig. 16, both of the gas discharge path 40 surrounded by the insulating layer 22 and the active layer 13 formed in the groove portion 29 and the gas discharge path 40 surrounded by the insulating layer 12 and the active layer 13 formed in the groove portion 18 may be formed.
In embodiment 2, the cross section of the gas discharge path 40 is formed in a semicircular shape, but the cross section of the gas discharge path 40 may be formed in another shape. For example, the grooves 29 and the gas discharge paths 40 having a rectangular cross section may be formed by anisotropic etching such as RIE as shown in fig. 17.
Further, as shown in fig. 18, the gas discharge path 40 may be formed only by the groove portion 29 formed in the substrate 21, and the insulating layer 22 may be absent at this position. Of course, the gas discharge path 40 may be formed only by the groove portion formed on the support layer 11 side, and the insulating layer 12 may not be disposed at this position.
As shown in fig. 19, the groove 28 may be formed of a rectangular groove surrounding each concave portion 23 and a linear groove connecting adjacent rectangular grooves.
In fig. 5 and 19, the groove 28 is formed in a rectangular frame shape so as to surround the entire circumference of each concave portion 23, but the entire circumference of each concave portion 23 is not necessarily surrounded, and the groove 28 may be formed in a U shape facing 3 sides of each concave portion 23 having a rectangular shape, for example.
Further, the gas discharge path 40 may be formed by forming grooves in the active layer 13 in addition to or instead of the support layer 11 and the substrate 21.
Further, since the residual gas can be exhausted to the outside of the wafer by the gas exhaust passage 40 shown in the other embodiments, the annealing in the oxygen atmosphere may be performed as needed, and the same effect can be obtained even if not performed.
The sensor portion 10 may have a normal SOI structure in which no cavity is formed. In this case, a part of the insulating layer 12 is removed by etching when the element portion 15 is formed, and a space is formed in a lower portion of the element portion 15 so that the element portion 15 can be displaced. Further, SiO is not formed on the wall surface of the space 30 at the portion constituted by the sensor unit 102The film has a space 30 constituted by a space surrounded by the recess 23 and a space formed by etching when the element portion 15 is formed.
In addition, although the semiconductor device including a plurality of insulating layers used for bonding Si substrates has been described in embodiments 1 and 2, the present invention may be applied to a semiconductor device including only 1 insulating layer. The present invention can also be applied to semiconductor devices other than sensors. Further, as the sensor, a case has been described in which the sensor is applicable to a capacitance type acceleration sensor that detects acceleration based on a change in capacitance, or a vibration type angular velocity sensor that vibrates the element portion 15 and detects an applied angular velocity. However, these are merely examples, and other physical quantity sensors, for example, a vibration type acceleration sensor that vibrates the element portion 15 and detects applied acceleration, may be applied.

Claims (10)

1. A method for manufacturing a semiconductor device having a space (30) formed therein,
the method comprises the following steps:
preparing a plurality of silicon substrates (11, 13, 21);
forming a recess (14, 23) in at least 1 of the plurality of silicon substrates;
forming silicon oxide films (12, 22) on at least 1 of the silicon substrates at a portion separated from the region to be formed in the space, the silicon oxide films (12, 22) having groove portions (17, 28) that surround the region to be formed and reach outer peripheries of the silicon substrates;
forming a gas discharge path (40) by bonding a silicon substrate having the silicon oxide film formed thereon among the plurality of silicon substrates and another silicon substrate among the plurality of silicon substrates by direct bonding via the silicon oxide film so as to cover the groove portion, thereby forming a laminated structure of the plurality of silicon substrates and the silicon oxide film, the space being formed inside the laminated structure by the recess portion; and
after the space is formed, the gas in the space is discharged to the outside of the laminated structure through the gas discharge passage by heat treatment.
2. The method for manufacturing a semiconductor device according to claim 1,
the step of forming the silicon oxide film having the groove portions is a step of:
after the silicon oxide film is formed on at least 1 of the plurality of silicon substrates, the groove portion is formed by etching a part of the silicon oxide film.
3. The method for manufacturing a semiconductor device according to claim 1,
the step of forming the silicon oxide film having the groove portions formed thereon includes the steps of:
forming a groove (29) as a base in at least 1 of the plurality of silicon substrates on which the silicon oxide film is formed; and
after the grooves serving as the foundation are formed, the silicon oxide film in which the grooves are formed by reflecting the shape of the grooves serving as the foundation is formed on at least 1 of the plurality of silicon substrates.
4. A semiconductor device having a space (30) formed therein,
comprising:
a support layer (11) made of silicon;
an active layer (13) which is composed of silicon, has an element section (15), and is joined to the support layer via a 1 st silicon oxide film (12); and
a lid (20) made of silicon, bonded to the active layer through a 2 nd silicon oxide film (22), and having a recess (23) formed at a position corresponding to the element section;
a laminated structure of the support layer, the 1 st silicon oxide film, the active layer, the 2 nd silicon oxide film, and the lid portion is configured, and the space is formed inside the laminated structure by the recess portion;
at least 1 of the 1 st silicon oxide film and the 2 nd silicon oxide film is provided with a gas discharge path (40) which surrounds the space and reaches the outer periphery of the active layer.
5. The semiconductor device according to claim 4,
the gas discharge path includes a void provided in at least 1 of the 1 st silicon oxide film and the 2 nd silicon oxide film.
6. The semiconductor device according to claim 4,
the gas discharge path is formed in the 1 st silicon oxide film;
the support layer and the active layer are exposed from the 1 st silicon oxide film at a position where the gas discharge path is formed, and the gas discharge path includes a void surrounded by the support layer, the active layer, and the 1 st silicon oxide film.
7. The semiconductor device according to claim 4,
the gas discharge path is formed in the 2 nd silicon oxide film;
the active layer and the lid portion are exposed from the 2 nd silicon oxide film at a position where the gas discharge path is formed, and the gas discharge path includes a void surrounded by the active layer, the lid portion, and the 2 nd silicon oxide film.
8. The semiconductor device according to claim 4,
the gas discharge path is formed in the 1 st silicon oxide film;
the support layer and the active layer are covered with the 1 st silicon oxide film at positions where the gas discharge paths are formed, and the gas discharge paths are formed at positions away from the support layer and the active layer.
9. The semiconductor device according to claim 4,
the gas discharge path is formed in the 2 nd silicon oxide film;
the active layer and the lid portion are also covered with the 2 nd silicon oxide film at a position where the gas discharge path is formed, and the gas discharge path is formed at a position apart from the active layer and the lid portion.
10. The semiconductor device according to any one of claims 4 to 9,
the pressure in the space is 100Pa or less, and the getter film is not provided in the space.
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