CN112038232A - Sab氮化硅膜制造方法及sab工艺控制模块 - Google Patents

Sab氮化硅膜制造方法及sab工艺控制模块 Download PDF

Info

Publication number
CN112038232A
CN112038232A CN202010877976.2A CN202010877976A CN112038232A CN 112038232 A CN112038232 A CN 112038232A CN 202010877976 A CN202010877976 A CN 202010877976A CN 112038232 A CN112038232 A CN 112038232A
Authority
CN
China
Prior art keywords
sab
sccm
etching
gas
sin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010877976.2A
Other languages
English (en)
Inventor
刘哲郡
林聪�
徐莹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Original Assignee
Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huali Integrated Circuit Manufacturing Co Ltd filed Critical Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Priority to CN202010877976.2A priority Critical patent/CN112038232A/zh
Publication of CN112038232A publication Critical patent/CN112038232A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02351Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to corpuscular radiation, e.g. exposure to electrons, alpha-particles, protons or ions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67017Apparatus for fluid treatment
    • H01L21/67063Apparatus for fluid treatment for etching
    • H01L21/67069Apparatus for fluid treatment for etching for drying etching
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

本发明公开了一种SAB氮化硅膜制造方法,包括如下步骤:形成半导体器件的栅极结构、源区和漏区,栅极结构包括依次形成于半导体衬底表面的栅介质层和多晶硅栅,源区和漏区形成于对应的所述多晶硅栅的两侧;沉积SAB SiN形成SAB膜层;执行SAB膜层刻蚀;执行步骤S2时,沉积条件为:沉积源SiH4气体流量调节范围为100sccm~200sccm,沉积源NH3气体流量调节范围为0sccm~150sccm,沉积源He气体流量调节范围为0sccm~2000sccm。本发明还公开了一种用于半导体机台控制SAB工艺参数的SAB工艺控制模块。本发明能克服现有技术的缺陷,能提高栅极间SAB氮化硅膜覆盖率,提高SAB氮化硅膜均一性,防止SAB刻蚀中出现过刻蚀造成硅损耗,避免造成漏电增大,提高产品良率。

Description

SAB氮化硅膜制造方法及SAB工艺控制模块
技术领域
本发明涉及集成电路生产制造领域,特别是涉及一种SAB氮化硅膜制造方法。本发明还涉及一种SAB工艺控制模块。
背景技术
在集成电路生产制造中常常会用到有自对准的金属硅化物(Salicide)和无自对准的金属硅化物(Salicide)两种器件,因此要用到金属硅化物阻挡层(SAB)工艺。现有工艺采用SiN与OX(氧气)形成的氧化膜作为SAB膜,通过刻蚀来形成SAB区。
不同于传统逻辑工艺,eFlash工艺中的基本存储单元Cell,栅极Poly间距随基本存储单元尺寸cell size缩小而减小。随着侧墙的增加,在SAB SiN沉积与刻蚀后,由于淀积的SAB膜均一性较差,非常容易在小间距的栅极间出现硅损耗,造成漏电增大,良率损耗。
发明内容
在发明内容部分中引入了一系列简化形式的概念,该简化形式的概念均为本领域现有技术简化,这将在具体实施方式部分中进一步详细说明。本发明的发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征,更不意味着试图确定所要求保护的技术方案的保护范围。
本发明要解决的技术问题是提供一种能提高栅极间SAB氮化硅膜覆盖率,提高SAB氮化硅膜均一性,防止SAB刻蚀中出现过刻蚀造成硅损耗的SAB氮化硅膜制造方法。
本发明要解决的另一技术问题是提供一种用于半导体生产机台,能提高栅极间SAB氮化硅膜覆盖率,提高SAB氮化硅膜均一性,防止SAB刻蚀中出现过刻蚀造成硅损耗的SAB工艺控制模块。
为解决上述技术问题,本发明提供的SAB氮化硅膜制造方法,包括如下步骤:
S1,形成半导体器件的栅极结构、源区和漏区,栅极结构包括依次形成于半导体衬底表面的栅介质层和多晶硅栅,源区和漏区形成于对应的所述多晶硅栅的两侧;
S2,沉积SAB SiN形成SAB膜层;
S3,执行SAB膜层刻蚀;
其中,执行步骤S2时,沉积条件为:沉积源SiH4气体流量调节范围为100sccm~200sccm,沉积源NH3气体流量调节范围为0sccm~150sccm,沉积源He气体流量调节范围为0sccm~2000sccm。
可选择的,进一步改进所述的SAB氮化硅膜制造方法,沉积源SiH4气体流量调节范围为176sccm,沉积源NH3气体流量调节范围为100sccm,沉积源He气体流量调节范围为2000sccm。
可选择的,进一步改进所述的SAB氮化硅膜制造方法,执行步骤S3时,通过SiN和OX采用第一刻蚀选择比执行主刻蚀,且使主刻蚀时间在原有主刻蚀时间上减少第一预设时段;通过SiN和OX采用第二刻蚀选择比执行过刻蚀,且使过刻蚀时间在原有过刻蚀时间上增加第二预设时段。
可选择的,进一步改进所述的SAB氮化硅膜制造方法,第一刻蚀选择比SiN和OX刻蚀选择比为1:1,第一预设段范围为8S-12s;
第二刻蚀选择比SiN和OX刻蚀选择比为∞:1,第二预设段范围为30S-100s。
可选择的,进一步改进所述的SAB氮化硅膜制造方法,第一预设段为10s,第二预设段为60s。
本发明一种SAB工艺控制模块,其用于半导体机台控制SAB工艺参数,在执行沉积SAB SiN形成SAB膜层时,该SAB工艺控制模块控制沉积条件为:沉积源SiH4气体流量调节范围为100sccm~200sccm,沉积源NH3气体流量调节范围为0sccm~150sccm,沉积源He气体流量调节范围为0sccm~2000sccm。
可选择的,进一步改进所述的SAB工艺控制模块,在执行沉积SAB SiN形成SAB膜层时,该SAB工艺控制模块控制沉积条件为:沉积源SiH4气体流量调节范围为176sccm,沉积源NH3气体流量调节范围为100sccm,沉积源He气体流量调节范围为2000sccm。
可选择的,进一步改进所述的SAB工艺控制模块,执行SAB膜层刻蚀时,该SAB工艺控制模块控制SiN和OX采用第一刻蚀选择比执行主刻蚀,且使主刻蚀时间在原有主刻蚀时间上减少第一预设时段;该SAB工艺控制模块控制SiN和OX采用第二刻蚀选择比执行过刻蚀,且使过刻蚀时间在原有过刻蚀时间上增加第二预设时段。
可选择的,进一步改进所述的SAB工艺控制模块,第一刻蚀选择比SiN和OX刻蚀选择比为1:1,第一预设段范围为8S-12s;
第二刻蚀选择比SiN和OX刻蚀选择比为∞:1,第二预设段范围为30S-100s。
可选择的,进一步改进所述的SAB工艺控制模块,第一预设段为10s,第二预设段为60s。
本发明从两个方面来改善现有技术的缺陷:首先,通过改变现有技术SAB SiN沉积条件(改变沉积源SiH4、NH3和He的流量)改善氮化硅在小间距栅极间的台阶结构处SAB氮化硅膜覆盖率,提高SAB氮化硅膜均一性,避免造成硅损耗。其次,通过氮化硅膜刻蚀时,(相对现有技术)减少主刻蚀并控制主刻蚀选择比,增加过刻蚀时间并控制过刻蚀选择比的方案避免栅极间底部膜层出现过刻蚀。参考图1所示,采用现有技术形成的栅极间SAB氮化硅膜与其他位置SAB氮化硅膜厚度均一性差,在后续刻蚀过程中会造成栅极间硅损耗。参考图2所示,采用本发明形成的栅极间SAB氮化硅膜与其他位置SAB氮化硅膜厚度均一性一致,在后续刻蚀过程中不会造成栅极间硅损耗。
本发明两个方面的工艺改善是相互独立的关系,可以独立实施均能克服现有技术的缺陷,能提高栅极间SAB氮化硅膜覆盖率,提高SAB氮化硅膜均一性,防止SAB刻蚀中出现过刻蚀造成硅损耗,避免造成漏电增大,提高产品良率。如果将本发明两个方面的工艺改善结合使用将能获得更好的技术效果。
附图说明
本发明附图旨在示出根据本发明的特定示例性实施例中所使用的方法、结构和/或材料的一般特性,对说明书中的描述进行补充。然而,本发明附图是未按比例绘制的示意图,因而可能未能够准确反映任何所给出的实施例的精确结构或性能特点,本发明附图不应当被解释为限定或限制由根据本发明的示例性实施例所涵盖的数值或属性的范围。下面结合附图与具体实施方式对本发明作进一步详细的说明:
图1是通过现有技术形成的栅极间SAB氮化硅膜覆盖效果示意图。
图2是通过本发明形成的栅极间SAB氮化硅膜覆盖效果示意图。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式,本领域技术人员可由本说明书所公开的内容充分地了解本发明的其他优点与技术效果。本发明还可以通过不同的具体实施方式加以实施或应用,本说明书中的各项细节也可以基于不同观点加以应用,在没有背离发明总的设计思路下进行各种修饰或改变。需说明的是,在不冲突的情况下,以下实施例及实施例中的特征可以相互组合。本发明下述示例性实施例可以多种不同的形式来实施,并且不应当被解释为只限于这里所阐述的具体实施例。应当理解的是,提供这些实施例是为了使得本发明的公开彻底且完整,并且将这些示例性具体实施例的技术方案充分传达给本领域技术人员。
第一实施例,本发明提供一种SAB氮化硅膜制造方法,包括如下步骤:
S1,形成半导体器件的栅极结构、源区和漏区,栅极结构包括依次形成于半导体衬底表面的栅介质层和多晶硅栅,源区和漏区形成于对应的所述多晶硅栅的两侧;
S2、沉积SAB SiN形成SAB膜层;
S3,执行SAB膜层刻蚀;
执行步骤S2时,沉积条件为:沉积源SiH4气体流量调节范围为100sccm~200sccm,沉积源NH3气体流量调节范围为0sccm~150sccm,沉积源He气体流量调节范围为0sccm~2000sccm。示例性的现有技术中沉积源SiH4气体流量调节范围为300sccm,沉积源NH3气体流量调节范围为200sccm,沉积源He气体流量调节范围为3000sccm。沉积源气体流量调节范围不属于本发明第一实施例的范围,则无法改善栅极间SAB氮化硅膜覆盖率,只有在本发明第一实施例的范围内实施沉积才能改善栅极间SAB氮化硅膜覆盖率。
可选择的,改进上述第一实施例,沉积源SiH4气体流量调节范围为176sccm,沉积源NH3气体流量调节范围为100sccm,沉积源He气体流量调节范围为2000sccm。
第二实施例,本发明提供一种SAB氮化硅膜制造方法,包括如下步骤:
S1,形成半导体器件的栅极结构、源区和漏区,栅极结构包括依次形成于半导体衬底表面的栅介质层和多晶硅栅,源区和漏区形成于对应的所述多晶硅栅的两侧;
S2、沉积SAB SiN形成SAB膜层;
S3,执行SAB膜层刻蚀;
执行步骤S3时,通过SiN和OX采用第一刻蚀选择比执行主刻蚀,且使主刻蚀时间在原有主刻蚀时间上减少第一预设时段;通过SiN和OX采用第二刻蚀选择比执行过刻蚀,且使过刻蚀时间在原有过刻蚀时间上增加第二预设时段。
示例性的现有技术中主刻蚀时间为30S,SiN和OX刻蚀选择比为2:1,过刻蚀时间为50S,SiN和OX刻蚀选择比为100:1;该刻蚀参数范围不属于本发明第二实施例的范围,则无法改善栅极间SAB氮化硅膜过刻蚀的缺陷会造成硅损耗,只有在本发明第二实施例的范围内实施刻蚀才能避免过刻蚀的缺陷会造成硅损耗。
可选择的,改进上述第二实施例,第一刻蚀选择比SiN和OX刻蚀选择比为1:1,第一预设段范围为8S-12s;
第二刻蚀选择比SiN和OX刻蚀选择比为∞:1,第二预设段范围为30S-100s。
可选择的,进一步改进上述第二实施例,第一预设段为10s,第二预设段为60s。
第三实施例,本发明提供一种SAB氮化硅膜制造方法,包括如下步骤:
S1,形成半导体器件的栅极结构、源区和漏区,栅极结构包括依次形成于半导体衬底表面的栅介质层和多晶硅栅,源区和漏区形成于对应的所述多晶硅栅的两侧;
S2、沉积SAB SiN形成SAB膜层,沉积条件为:沉积源SiH4气体流量调节范围为100sccm~200sccm,沉积源NH3气体流量调节范围为0sccm~150sccm,沉积源He气体流量调节范围为0sccm~2000sccm;
S3,执行SAB膜层刻蚀,通过SiN和OX采用第一刻蚀选择比执行主刻蚀,且使主刻蚀时间在原有主刻蚀时间上减少第一预设时段;通过SiN和OX采用第二刻蚀选择比执行过刻蚀,且使过刻蚀时间在原有过刻蚀时间上增加第二预设时段。
可选择的,改进上述第三实施例,沉积源SiH4气体流量调节范围为176sccm,沉积源NH3气体流量调节范围为100sccm,沉积源He气体流量调节范围为2000sccm;
第一刻蚀选择比SiN和OX刻蚀选择比为1:1,第一预设段范围为8S-12s;
第二刻蚀选择比SiN和OX刻蚀选择比为∞:1,第二预设段范围为30S-100s;
可选择的,进一步改进上述第三实施例,第一预设段为10s,第二预设段为60s。
第四实施例,本发明提供一种SAB工艺控制模块,其用于半导体机台控制SAB工艺参数,在执行沉积SAB SiN形成SAB膜层时,该SAB工艺控制模块控制沉积条件为:沉积源SiH4气体流量调节范围为100sccm~200sccm,沉积源NH3气体流量调节范围为0sccm~150sccm,沉积源He气体流量调节范围为0sccm~2000sccm。
可选择的,改进上述第四实施例,在执行沉积SAB SiN形成SAB膜层时,该SAB工艺控制模块控制沉积条件为:沉积源SiH4气体流量调节范围为176sccm,沉积源NH3气体流量调节范围为100sccm,沉积源He气体流量调节范围为2000sccm。
第五实施例,本发明提供一种SAB工艺控制模块,其用于半导体机台控制SAB工艺参数,执行SAB膜层刻蚀时,该SAB工艺控制模块控制SiN和OX采用第一刻蚀选择比执行主刻蚀,且使主刻蚀时间在原有主刻蚀时间上减少第一预设时段;该SAB工艺控制模块控制SiN和OX采用第二刻蚀选择比执行过刻蚀,且使过刻蚀时间在原有过刻蚀时间上增加第二预设时段。
可选择的,改进上述第五实施例,第一刻蚀选择比SiN和OX刻蚀选择比为1:1,第一预设段范围为8S-12s;
第二刻蚀选择比SiN和OX刻蚀选择比为∞:1,第二预设段范围为30S-100s。
可选择的,进一步改进上述第五实施例,第一预设段为10s,第二预设段为60s。
第六实施例,本发明提供一种SAB工艺控制模块,其用于半导体机台控制SAB工艺参数,在执行沉积SAB SiN形成SAB膜层时,该SAB工艺控制模块控制沉积条件为:沉积源SiH4气体流量调节范围为100sccm~200sccm,沉积源NH3气体流量调节范围为0sccm~150sccm,沉积源He气体流量调节范围为0sccm~2000sccm;
并且,执行SAB膜层刻蚀时,该SAB工艺控制模块控制SiN和OX采用第一刻蚀选择比执行主刻蚀,且使主刻蚀时间在原有主刻蚀时间上减少第一预设时段;该SAB工艺控制模块控制SiN和OX采用第二刻蚀选择比执行过刻蚀,且使过刻蚀时间在原有过刻蚀时间上增加第二预设时段。
可选择的,改进上述第六实施例,在执行沉积SAB SiN形成SAB膜层时,该SAB工艺控制模块控制沉积条件为:沉积源SiH4气体流量调节范围为176sccm,沉积源NH3气体流量调节范围为100sccm,沉积源He气体流量调节范围为2000sccm;
第一刻蚀选择比SiN和OX刻蚀选择比为1:1,第一预设段范围为8S-12s;
第二刻蚀选择比SiN和OX刻蚀选择比为∞:1,第二预设段范围为30S-100s。
可选择的,进一步改进上述第六实施例,第一预设段为10s,第二预设段为60s。
除非另有定义,否则这里所使用的全部术语(包括技术术语和科学术语)都具有与本发明所属领域的普通技术人员通常理解的意思相同的意思。还将理解的是,除非这里明确定义,否则诸如在通用字典中定义的术语这类术语应当被解释为具有与它们在相关领域语境中的意思相一致的意思,而不以理想的或过于正式的含义加以解释。
以上通过具体实施方式和实施例对本发明进行了详细的说明,但这些并非构成对本发明的限制。在不脱离本发明原理的情况下,本领域的技术人员还可做出许多变形和改进,这些也应视为本发明的保护范围。

Claims (10)

1.一种SAB氮化硅膜制造方法,包括如下步骤:
S1,形成半导体器件的栅极结构、源区和漏区,栅极结构包括依次形成于半导体衬底表面的栅介质层和多晶硅栅,源区和漏区形成于对应的所述多晶硅栅的两侧;
S2,沉积SAB SiN形成SAB膜层;
S3,执行SAB膜层刻蚀;
其特征在于,执行步骤S2时,沉积条件为:沉积源SiH4气体流量调节范围为100sccm~200sccm,沉积源NH3气体流量调节范围为0sccm~150sccm,沉积源He气体流量调节范围为0sccm~2000sccm。
2.如权利要求1所述的SAB氮化硅膜制造方法,其特征在于:
沉积源SiH4气体流量调节范围为176sccm,沉积源NH3气体流量调节范围为100sccm,沉积源He气体流量调节范围为2000sccm。
3.如权利要求1所述的SAB氮化硅膜制造方法,其特征在于:
执行步骤S3时,通过SiN和OX采用第一刻蚀选择比执行主刻蚀,且使主刻蚀时间在原有主刻蚀时间上减少第一预设时段;通过SiN和OX采用第二刻蚀选择比执行过刻蚀,且使过刻蚀时间在原有过刻蚀时间上增加第二预设时段。
4.如权利要求3所述的SAB氮化硅膜制造方法,其特征在于:第一刻蚀选择比SiN和OX刻蚀选择比为1:1,第一预设段范围为8S-12s;
第二刻蚀选择比SiN和OX刻蚀选择比为∞:1,第二预设段范围为30S-100s。
5.如权利要求4所述的SAB氮化硅膜制造方法,其特征在于:第一预设段为10s,第二预设段为60s。
6.一种SAB工艺控制模块,其用于半导体机台控制SAB工艺参数,其特征在于:
在执行沉积SAB SiN形成SAB膜层时,该SAB工艺控制模块控制沉积条件为:沉积源SiH4气体流量调节范围为100sccm~200sccm,沉积源NH3气体流量调节范围为0sccm~150sccm,沉积源He气体流量调节范围为0sccm~2000sccm。
7.如权利要求6所述的SAB工艺控制模块,其特征在于:
在执行沉积SAB SiN形成SAB膜层时,该SAB工艺控制模块控制沉积条件为:沉积源SiH4气体流量调节范围为176sccm,沉积源NH3气体流量调节范围为100sccm,沉积源He气体流量调节范围为2000sccm。
8.如权利要求6所述的SAB工艺控制模块,其特征在于:
执行SAB膜层刻蚀时,该SAB工艺控制模块控制SiN和OX采用第一刻蚀选择比执行主刻蚀,且使主刻蚀时间在原有主刻蚀时间上减少第一预设时段;该SAB工艺控制模块控制SiN和OX采用第二刻蚀选择比执行过刻蚀,且使过刻蚀时间在原有过刻蚀时间上增加第二预设时段。
9.如权利要求8所述的SAB工艺控制模块,其特征在于:
第一刻蚀选择比SiN和OX刻蚀选择比为1:1,第一预设段范围为8S-12s;
第二刻蚀选择比SiN和OX刻蚀选择比为∞:1,第二预设段范围为30S-100s。
10.如权利要求9所述的SAB工艺控制模块,其特征在于:第一预设段为10s,第二预设段为60s。
CN202010877976.2A 2020-08-27 2020-08-27 Sab氮化硅膜制造方法及sab工艺控制模块 Pending CN112038232A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010877976.2A CN112038232A (zh) 2020-08-27 2020-08-27 Sab氮化硅膜制造方法及sab工艺控制模块

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010877976.2A CN112038232A (zh) 2020-08-27 2020-08-27 Sab氮化硅膜制造方法及sab工艺控制模块

Publications (1)

Publication Number Publication Date
CN112038232A true CN112038232A (zh) 2020-12-04

Family

ID=73585797

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010877976.2A Pending CN112038232A (zh) 2020-08-27 2020-08-27 Sab氮化硅膜制造方法及sab工艺控制模块

Country Status (1)

Country Link
CN (1) CN112038232A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115602542A (zh) * 2022-01-29 2023-01-13 和舰芯片制造(苏州)股份有限公司(Cn) 一种防止漏电的半导体sab制作方法及半导体器件

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW473829B (en) * 2000-07-25 2002-01-21 Ibm An improved method of depositing a conformal h-rich Si3N4 layer onto a patterned structure
TWI225287B (en) * 2003-12-23 2004-12-11 Macronix Int Co Ltd Method for fabricating a non-volatile memory and metal interconnects process
CN101167165A (zh) * 2005-05-26 2008-04-23 应用材料股份有限公司 增加pecvd氮化硅膜层的压缩应力的方法
JP2013105765A (ja) * 2011-11-10 2013-05-30 Renesas Electronics Corp 半導体装置の製造方法
CN103137550A (zh) * 2011-12-05 2013-06-05 中芯国际集成电路制造(上海)有限公司 在层间介质层自对准形成空隙的方法
CN106298677A (zh) * 2015-06-12 2017-01-04 中芯国际集成电路制造(上海)有限公司 半导体存储器及其制造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW473829B (en) * 2000-07-25 2002-01-21 Ibm An improved method of depositing a conformal h-rich Si3N4 layer onto a patterned structure
TWI225287B (en) * 2003-12-23 2004-12-11 Macronix Int Co Ltd Method for fabricating a non-volatile memory and metal interconnects process
CN101167165A (zh) * 2005-05-26 2008-04-23 应用材料股份有限公司 增加pecvd氮化硅膜层的压缩应力的方法
JP2013105765A (ja) * 2011-11-10 2013-05-30 Renesas Electronics Corp 半導体装置の製造方法
CN103137550A (zh) * 2011-12-05 2013-06-05 中芯国际集成电路制造(上海)有限公司 在层间介质层自对准形成空隙的方法
CN106298677A (zh) * 2015-06-12 2017-01-04 中芯国际集成电路制造(上海)有限公司 半导体存储器及其制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115602542A (zh) * 2022-01-29 2023-01-13 和舰芯片制造(苏州)股份有限公司(Cn) 一种防止漏电的半导体sab制作方法及半导体器件

Similar Documents

Publication Publication Date Title
US9059215B2 (en) Method for adjusting the threshold voltage of LTPS TFT
JP2006524438A (ja) シリコンを導入することによって、仕事関数を微調整したメタルゲート構造を形成する方法
US7071519B2 (en) Control of high-k gate dielectric film composition profile for property optimization
US20030227055A1 (en) Semiconductor device having\ gate with negative slope and method for manufacturing the same
CN112038232A (zh) Sab氮化硅膜制造方法及sab工艺控制模块
KR20000041393A (ko) 반도체소자의 게이트전극 형성방법
KR20060038245A (ko) 게이트스페이서를 구비한 반도체 소자의 제조 방법
TWI691019B (zh) 快閃記憶體裝置及其製造方法
CN101577221B (zh) 多晶硅薄膜及多晶硅栅极的形成方法
CN101740368A (zh) 半导体器件及其栅极的形成方法
CN115312374A (zh) 沟槽式器件晶圆的制备方法及沟槽式器件晶圆
CN109300781B (zh) Ono膜层的制造方法
US6962861B2 (en) Method of forming a polysilicon layer comprising microcrystalline grains
KR20040110016A (ko) 반도체소자의 게이트전극 형성방법
CN117747433B (zh) 一种沟槽栅型功率器件及其制备方法、元胞版图结构
KR100633988B1 (ko) 반도체 소자 및 그 제조 방법
WO2021179925A1 (zh) 厚度分布均匀的膜层形成方法及半导体结构
WO2022105281A1 (zh) 半导体结构及半导体结构的制造方法
KR100580050B1 (ko) 반도체 소자의 폴리 실리콘 게이트 제조 방법
CN101930921A (zh) 提高栅极尺寸均匀性的方法
KR100955924B1 (ko) 반도체 소자의 콘택 플러그 형성방법
JPH11297988A (ja) 金属シリサイドのスパイキング効果を防止するゲート電極製造方法
KR20080002548A (ko) 메탈전극의 이상 산화를 방지할 수 있는 반도체소자의 제조방법
CN116759304A (zh) 半导体结构的制备方法
KR100336566B1 (ko) 반도체소자의제조방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20201204

RJ01 Rejection of invention patent application after publication