CN112017964A - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

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CN112017964A
CN112017964A CN202010165588.1A CN202010165588A CN112017964A CN 112017964 A CN112017964 A CN 112017964A CN 202010165588 A CN202010165588 A CN 202010165588A CN 112017964 A CN112017964 A CN 112017964A
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gate
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林资敬
吴卓斌
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本公开涉及半导体装置的制造方法。在半导体装置中形成源极/漏极区域的方法，以及包括以该方法形成的源极/漏极区域的半导体装置。在一实施例中，方法包括蚀刻半导体鳍片以形成第一凹槽，半导体鳍片定义第一凹槽的侧壁及底部表面，半导体鳍片在第一方向上延伸；在第一凹槽中形成包括单一连续材料的源极/漏极区域，单一连续材料自第一凹槽的底部表面延伸至高于半导体鳍片的顶部表面，形成源极/漏极区域的前驱物气体包括磷化氢(PH3)，并包括砷化氢(AsH3)或单甲基硅甲烷(CH6Si)中至少一者；以及在相邻于源极/漏极区域的半导体鳍片上形成在垂直于第一方向的第二方向上延伸的栅极。

Description

半导体装置的制造方法
技术领域
本公开涉及一种半导体装置，特别涉及一种以低扩散率掺杂物掺杂的半导体装置。
背景技术
半导体装置被用于各种电子应用中，例如个人电脑、移动电话、数码相机、以及其他电子设备。半导体装置通常经由下列方式制造：在半导体基板上依序沉积绝缘或介电层、导电层、以及半导体层的材料，以及使用微影图案化各种材料层以在其上形成电路组件与元件。
半导体工业持续地通过不断降低最小特征尺寸以改进各种电子组件(例如：晶体管、二极管、电阻器、电容器等)的整合密度，这允许在给定的面积中整合更多的组件。然而，随着最小特征尺寸的降低，出现了需要被解决的其他问题。
发明内容
本公开实施例提供一种半导体装置的制造方法。上述方法包括蚀刻一半导体鳍片以形成第一凹槽，上述半导体鳍片定义第一凹槽的多个侧壁及底部表面，上述半导体鳍片在第一方向上延伸；在第一凹槽中形成源极/漏极区域，源极/漏极区域包括单一连续材料，单一连续材料自第一凹槽的底部表面延伸至高于上述半导体鳍片的顶部表面，用于形成源极/漏极区域的前驱物气体包括磷化氢(PH3)，以及包括砷化氢(AsH3)或单甲基硅甲烷(CH6Si)中的至少一者；以及在相邻于源极/漏极区域的上述半导体鳍片上形成一栅极，上述栅极在垂直于第一方向的第二方向上延伸。
本公开实施例提供一种半导体装置的制造方法。上述方法包括形成延伸自基板的一鳍片；在上述鳍片上形成栅极堆叠；形成沿着栅极堆叠的侧壁的栅极间隔物；蚀刻上述鳍片以形成第一凹槽，第一凹槽在栅极间隔物下以垂直于基板的主要表面的方向延伸；以及在第一凹槽中外延沉积源极/漏极材料，源极/漏极材料包括以砷掺杂的SiP，源极/漏极材料在栅极间隔物下以垂直于基板的主要表面的方向延伸，源极/漏极材料接触上述鳍片的水平表面以及垂直表面。
本公开实施例提供一种半导体装置的制造方法。上述方法包括蚀刻半导体鳍片以形成一凹槽；在上述凹槽中形成源极/漏极区域，源极/漏极区域包括半导体材料，半导体材料包括以砷及碳掺杂的SiP，以砷及碳掺杂的SiP沿着上述凹槽的侧壁及底部表面接触半导体鳍片；在相邻于源极/漏极区域的半导体鳍片上形成一栅极；在源极/漏极区域中形成硅化区；以及形成延伸至硅化区中的源极/漏极接点。
附图说明
本公开从后续实施方式及附图可更佳理解。须强调的是，依据产业的标准作法，各种特征并未按比例绘制。事实上，各种特征的尺寸可能任意增加或减少以清楚论述。
图1根据一些实施例，显示鳍式场效晶体管(FinFET)范例的三维附图。
图2至图7是根据一些实施例所示，制造FinFET的中间阶段的截面图。
图8A、图8B、图9A与图9B是根据一些实施例所示，制造FinFET的中间阶段的截面图。
图10A至图10D是根据一些实施例所示，制造FinFET的中间阶段的截面图。
图11A、图11B、图12A、图12B、图13A与图13B是根据一些实施例所示，制造FinFET的中间阶段的截面图。
图14A至图14C是根据一些实施例所示，制造FinFET的中间阶段的截面图。
图15A、图15B、图16A、图16B、图17A与图17B是根据一些实施例所示，制造FinFET的中间阶段的截面图。
其中，附图标记说明如下：
50:基板
52:鳍片
56:STI区域
86:源极/漏极区域
92:栅极介电层
94:栅极电极
A-A’,B-B’,C-C’:截面
50N,50P:区域
51:分隔器
54:绝缘材料
60:虚拟介电层
62:虚拟栅极层
64:遮罩层
58:通道区域
72:虚拟栅极
74:遮罩
80:栅极密封间隔物
82:栅极间隔物
W1,W2:宽度
D1:深度
87:接触蚀刻停止层
88:第一层间介电质
90:凹槽
91:区域
94A:衬垫层
94B:功函数调谐层
94C:填充材料
96:栅极遮罩
98:硅化区
108:第二层间介电质
111:开口
T1:厚度
D2:深度
110:栅极接点
112:源极/漏极接点
具体实施方式
以下的公开提供许多不同实施例或范例，用以实施本公开的不同特征。本公开的各部件及排列方式，其特定范例叙述于下以简化说明。理所当然的，这些范例并非用以限制本公开。举例来说，若叙述中有着第一特征成形于第二特征之上或上方，其可能包含第一特征与第二特征以直接接触成形的实施例，亦可能包含有附加特征形成于第一特征与第二特征之间，而使第一特征与第二特征间并非直接接触的实施例。此外，本公开可在多种范例中重复参考数字及/或字母。该重复的目的是为简化及清晰易懂，且本身并不规定所讨论的多种实施例及/或配置间的关系。
进一步来说，本公开可能会使用空间相对术语，例如“在…下方”、“下方”、“低于”、“在…上方”、“高于”及类似词汇，以便于叙述附图中一个元件或特征与其他元件或特征间的关系。除了附图所描绘的方位外，空间相对术语亦欲涵盖使用中或操作中的装置其不同方位。设备可能会被转向不同方位(旋转90度或其他方位)，而此处所使用的空间相对术语则可相应地进行解读。
具有低掺杂物向外扩散(low dopant out-diffusion)的单一材料，可被用于半导体装置中的源极/漏极区域。上述材料可被以有具有低扩散率(low-diffusivity)的掺杂物掺杂。在一些实施例中，源极/漏极区域可为n型源极/漏极区域，n型源极/漏极区域包括磷掺杂的硅以及低扩散率掺杂物，低扩散率掺杂物可包括碳及/或砷(arsenic)。源极/漏极区域可具有自约1×1021到约5×1021原子/立方厘米(atoms/cm3)的磷掺杂物浓度、自约1×1020到约3×1021原子/cm3的砷掺杂物浓度、以及自约0.1％至约2％的碳掺杂物的原子浓度。形成包括碳及/或砷掺杂物的单一材料的源极/漏极区域，可在不需要第二材料所形成的额外源极/漏极的情况下，降低来自源极/漏极区域以及漏极引发能带负载(drain-inducedbarrier loading,DIBL)的漏电(leakage)，这允许用于形成源极/漏极区域的单一材料的体积得以增加。这降低了源极/漏极区域的整体电阻、改善直流电流增益(DC gain)、并增加了震荡器速度(oscillator speed)。因此，装置的性能得到了改进。
图1根据一些实施例，显示FinFET的范例的三维附图。FinFET包括基板50(例如：半导体基板)上的鳍片52。浅沟槽隔离(Shallow trench isolation,STI)区域56被设置在基板50中，而鳍片52自相邻的STI区域56之间突出(protrude)，且突出并高于相邻的STI区域56。尽管STI区域56被描述/示出为与基板50分隔，但如本文中所使用的术语“基板”，可仅被用于指称半导体基板，或可被用于指称包括隔离区域的半导体基板。此外，尽管鳍片52被显示为与基板50一样的单一且连续的材料，但鳍片52及/或基板50可包括单一材料或多种材料。在此文内容中，鳍片52是指在相邻的STI区域56之间延伸的部分。
栅极介电层92沿着鳍片52的侧壁并位在鳍片52的顶部表面上，而栅极电极94位在栅极介电层92上方。源极/漏极区域86可被形成在鳍片52的位于栅极介电层92及栅极电极94的相对侧上的部分中，如下文将参考图10A至图10D所讨论的。图1更显示了被用于后续附图的参考截面图。截面A-A’沿着栅极电极94的纵轴，且举例来说，沿着垂直于FinFET的源极/漏极区域86之间的电流的方向。截面B-B’垂直于截面A-A’并沿着鳍片52的纵轴，且举例来说，沿着FinFET的源极/漏极区域86之间的电流的方向。截面C-C’与截面A-A’平行，且延伸穿过FinFET的源极/漏极区域。为了清楚起见，后续附图会参考这些参考截面。
本文讨论的一些实施例是在使用栅极后制(gate-last)制程形成FinFET的背景下进行讨论的。在其他实施例中，可使用栅极先制(gate-first)制程。此外，一些实施例思及了在诸如平面FET的平面装置中使用的态样。
图2至图17B是根据一些实施例所示，FinFET的制造的中间阶段的截面图。图2至图7显示图1中所示的参考截面A-A’，除了鳍片/FinFET数量为多个之外。图8A、图9A、图10A、图11A、图12A、图13A、图14A、图15A、图16A、以及图17A是沿着图1所示的参考截面A-A’所显示，而图8B、图9B、图10B、图11B、图12B、图13B、图14B、图14C、图15B、图16B、以及图17B则是沿着图1所示的类似截面B-B’所显示，除了鳍片/FinFET数量为多个以外。图10C及图10D是沿着图1所示的参考截面C-C’所显示，除了鳍片/FinFET数量为多个以外。
在图2中，基板50被提供。基板50可为半导体基板，例如体半导体(bulksemiconductor)、绝缘层上半导体(semiconductor-on-insulator,SOI)基板等，基板可被掺杂(例如：以p型或n型掺杂物)，或是未被掺杂。基板50可为晶圆，例如硅晶圆。一般而言，SOI基板是在绝缘层上形成的半导体材料层。绝缘层，举例来说，可为埋入式氧化物(buriedoxide,BOX)层、氧化硅层等。绝缘层被设置在基板上，基板通常为硅或玻璃基板。亦可使用其他基板，例如多层基板或梯度(gradient)基板。在一些实施例中，基板50的半导体材料可包括硅；锗；化合物半导体，包括碳化硅(silicon carbide)、砷化镓(gallium arsenic)、磷化镓(gallium phosphide)、磷化铟(indium phosphide)、砷化铟(indium arsenide)、及/或锑化铟(indium antimonide)；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、及/或GaInAsP；或其组合。
基板50具有区域50N以及区域50P。区域50N可被用于形成n型装置，例如NMOS晶体管，如n型FinFET。区域50P可被用于形成p型装置，例如PMOS晶体管，如p型FinFET。区域50N可被物理性地与区域50P分隔(如分隔器51所示)，且任何数量的装置特征(例如：其他主动装置、掺杂区域、隔离结构等)可被设置在区域50N与区域50P之间。
在图3中，鳍片52被形成在基板50中。鳍片52为半导体带(strip)。在一些实施例中，可通过在基板50中蚀刻沟槽来在基板50中形成鳍片52。蚀刻可为任何可接受的蚀刻制程，例如反应式离子蚀刻(reactive ion etch,RIE)、中子束蚀刻(neutral beam etchNBE)等、或其组合。蚀刻可为非等向性的(anisotropic)。
可通过任何合适的方法来图案化鳍片52。举例来说，可使用一或多个微影(photolithography)制程以图案化鳍片52，包括双重图案化(double-patterning)或多重图案化(multi-patterning)。一般而言，双重图案化或多重图案化结合了微影制程及自我对准(self-aligned)制程，这允许创建具有小间距的图案，举例来说，图案的间距小于另外使用单一、直接的微影制程所能得到的间距。举例来说，在一个实施例中，牺牲层(并未单独显示)被形成在基板50上，并使用微影制程将的图案化。使用自我对准制程在图案化的牺牲层旁边形成间隔物(spacer，并未单独显示)。牺牲层接着被移除，而剩余之间隔物随后会被用于图案化鳍片52。
在图4中，绝缘材料54被形成在基板50上以及相邻的鳍片52之间。绝缘材料54可为诸如氧化硅的氧化物、氮化物等、或其组合，且绝缘材料54可通过下列方法形成：高密度等离子体化学气相沉积(high density plasma chemical vapor deposition,HDP-CVD)、流动式CVD(flowable CVD,FCVD)(例如：在远程等离子体系统中进行基于CVD的材料沉积，并进行后处理(post curing)以使其转变为另一种材料，例如氧化物)等、或其组合。亦可使用以任何可接受的制程形成的其他绝缘材料。在所绘实施例中，绝缘材料54是由FCVD制程所形成的氧化硅。一旦形成绝缘材料，便可执行退火(anneal)制程。在一个实施例中，绝缘材料54被形成，使得过量的绝缘材料54覆盖鳍片52。尽管绝缘材料54被显示为单层，但一些实施例则可利用多于一层。举例来说，在一些实施例中，可以先沿着基板50以及鳍片52的表面形成衬垫(liner，未显示)。之后，可在衬垫上形成诸如上述的填充材料。
在图5中，对绝缘材料54施加移除制程，以移除鳍片52上的多余的绝缘材料54。在一些实施例中，可利用平坦化制程，例如化学机械研磨(chemical mechanical polish,CMP)、回蚀刻(etch back)制程、其组合等制程。平坦化制程会曝露鳍片52，使得在完成平坦化制程之后，鳍片52与绝缘材料54的顶部表面是呈水平的。
在图6中，绝缘材料54被掘入(recess)以形成浅沟槽隔离(shallow trenchisolation,STI)区域56。绝缘材料54被掘入，使得区域50N及区域50P中的鳍片52的上方部分自相邻的STI区域56之间突出。此外，STI区域56的顶部表面可具有如图所示的平坦表面、凸状表面、凹状表面、或其组合。STI区域56的顶部表面可通过适当的蚀刻而被形成为平坦的、凸状的、及/或凹状的。可使用可接受的蚀刻制程以掘入STI区域56，例如对绝缘材料54的材料具有选择性的蚀刻制程(例如：蚀刻绝缘材料54时具有比蚀刻鳍片52的材料时更高的速率)。举例来说，以合适的蚀刻制程执行化学氧化物的移除，例如使用稀释氢氟酸(dilute hydrofluoric,dHF)的蚀刻制程。
参照图2至图6所述的制程仅为一个范例，一个关于鳍片52可如何形成的范例。在一些实施例中，鳍片可通过外延生长(epitaxial growth)制程形成。举例来说，可在基板50的顶部表面上形成介电层，并可蚀刻穿过介电层的沟槽，以曝露下方的基板50。可在沟槽中外延生长同质外延(homoepitaxial)结构，并可掘入介电层，使得同质外延结构自介电层突出以形成鳍片。此外，在一些实施例中，异质外延(heteroepitaxial)结构可被用于鳍片52。举例来说，图5中的鳍片52可被掘入，且可在被掘入的鳍片52上外延生长与鳍片52不同的材料。在这些实施例中，鳍片52包括被掘入的材料，以及设置于被掘入的材料上的外延生长材料。在更进一步的实施例中，可在基板50的顶部表面上形成介电层，且可蚀刻出穿过介电层的沟槽。接着可使用与基板50不同的材料在沟槽中外延生长异质外延结构，且可掘入介电层，使得异质外延结构自介电层突出以形成鳍片52。在外延生长同质外延或异质外延结构的一些实施例中，可在生长期间对外延生长材料进行原位(in situ)掺杂，如此一来可免去之前或后续的布植(implantation)，尽管原位掺杂及布植掺杂可一同被使用。
此外，在区域50N(例如：NMOS区域)中外延生长与区域50P(例如：PMOS区域)中的材料不同的材料可能是有利的。在各种实施例中，鳍片52的上方部分可由硅锗(SixGe1-x，其中x可在0至1的范围内)、碳化硅、纯或基本上纯的锗、III-V族化合物半导体、II-VI化合物半导体等形成。举例来说，用于形成III-V族化合物半导体的可用材料包括但不限于：InAs、AlAs、GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlP、GaP等。
仍旧是图6，可在鳍片52及/或基板50中形成适当的井(well，并未单独显示)。在一些实施例中，可在区域50N中形成P井，并在区域50P中形成N井。在一些实施例中，P井或N井被同时形成在区域50N及区域50P中。
在井的类型不同的实施例中，可使用光阻(photoresist)或其他遮罩(并未单独显示)以实现对区域50N及区域50P的不同布植操作。举例来说，光阻可被形成在区域50N中的鳍片52及STI区域56上。图案化光阻以曝露基板50的区域50P，例如PMOS区域。可通过使用自旋涂布技术以形成光阻，并可使用可接受的微影技术以图案化光阻。一旦光阻被图案化，便在区域50P中执行n型杂质布植，且光阻可被用作遮罩以基本上防止n型杂质被布植到区域50N中(例如：NMOS区域中)。n型杂质可为布植到该区域中的磷、砷、锑等，其浓度等于或小于1018cm-3，例如在约1017cm-3与约1018cm-3之间。在布植之后，光阻可被移除，例如通过可接受的灰化(ashing)制程移除。
在区域50P的布植之后，于区域50P中的鳍片52及STI区域56上形成光阻。图案化光阻以曝露基板50的区域50N，例如NMOS区域。可通过使用自旋涂布技术以形成光阻，并可使用可接受的微影技术以图案化光阻。一旦光阻被图案化，便在区域50N中执行p型杂质布植，且光阻可被用作遮罩以基本上防止p型杂质被布植到区域50P中(例如：PMOS区域中)。p型杂质可为布植到该区域中的硼、BF2、铟等，其浓度等于或小于1018cm-3，例如在约1017cm-3与约1018cm-3之间。在布植之后，光阻可被移除，例如通过可接受的灰化制程移除。
在区域50N及区域50P的布植后，可执行退火以活化(activate)所布植的p型及/或n型杂质。在一些实施例中，可在生长期间对外延鳍片的生长材料进行原位掺杂，如此一来可免去布植制程，尽管原位掺杂及布植掺杂可一同被使用。
在图7中，虚拟介电层60被形成在鳍片52上。虚拟介电层60，举例来说，可为氧化硅、氮化硅、其组合等，且可根据可接受的技术进行沉积或热生长。在虚拟介电层60上形成虚拟栅极层62，并在虚拟栅极层62上形成遮罩层64。虚拟栅极层62可被沉积在虚拟介电层60上，并接着被平坦化，例如以CMP进行平坦化。遮罩层64可被沉积在虚拟栅极层62上。虚拟栅极层62可为导电材料，并可选自一个群组，该群组包括非晶硅(amorphous silicon)、多晶硅(polysilicon)、多晶硅锗(poly-SiGe)、金属氮化物、金属硅化物、金属氧化物、以及金属。虚拟栅极层62可通过下列方法沉积：物理气相沉积(physical vapor deposition,PVD)、CVD、溅镀(sputter)沉积、或其他本技术领域已知并已用于沉积导电材料的技术。虚拟栅极层62可由对隔离区域的蚀刻具有高蚀刻选择性的其他材料制成。遮罩层64，举例来说，可包括SiN、SiON等。在此范例中，单一虚拟栅极层62及单一遮罩层64被形成并横跨区域50N及区域50P。应注意的是，所示的虚拟栅极层60仅覆盖鳍片52，这种表现方法仅是用于说明的目的。在一些实施例中，虚拟介电层60可被沉积，以使虚拟介电层60覆盖STI区域56，并在虚拟栅极层62与STI区域56之间延伸。
图8A至图17B显示实施例装置的制造的各种附加操作。图8A至图17B显示区域50N及区域50P中任一者的特征。举例来说，图8A至图17B所示的结构可同时应用于区域50N及区域50P。在每个附图所附的文字中描述了区域50N与区域50P在结构上的差异(如果有的话)。
在图8A及图8B中，可使用可接受的微影与蚀刻技术对遮罩层64(参见图7)进行图案化，以形成遮罩74。遮罩74的图案可接着被转移到虚拟栅极层62。在一些实施例中(未单独显示)，遮罩74的图案亦可通过可接受的蚀刻技术而被转移到虚拟介电层60，以形成虚拟栅极72。虚拟栅极72覆盖各别的鳍片52的通道区域58。遮罩74的图案可被用于将每个虚拟栅极72与相邻的虚拟栅极物理性地分隔。虚拟栅极72亦可具有基本垂直于各个鳍片52的长度方向的长度方向。
仍旧是图8A及图8B，可在虚拟栅极72及/或遮罩74的曝露表面上形成栅极密封(seal)间隔物80。尽管并未显示于图8A及图8B，但栅极密封间隔物80亦可形成在鳍片52的曝露表面上，例如鳍片52的侧壁上。继续在非等向性蚀刻之后的热氧化或沉积，可形成栅极密封间隔物80。
在形成栅极密封间隔物80后，可执行用于轻度掺杂的源极/漏极(lightly dopedsource/drain,LDD)区域(未明确显示)的布植。在具有不同装置类型的实施例中，与上文在图6中所讨论的布植类似，可在区域50N上形成遮罩(例如：光阻)，并同时曝露区域50P，而适当类型(例如：p型)的杂质可被布植到区域50P中曝露的鳍片52中。遮罩可接着被移除。随后，可在区域50P上形成遮罩(例如：光阻)，并同时曝露区域50N，而适当类型(例如：n型)的杂质可被布植到区域50N中曝露的鳍片52中。遮罩可接着被移除。n型杂质可为先前所述的任何n型杂质，而p型杂质可为先前所述的任何p型杂质。轻度掺杂的源极/漏极区域可具有约1015cm-3至约1016cm-3的杂质浓度。可使用退火以活化所布植的杂质。
在图9A及图9B中，沿着虚拟栅极72及遮罩74的侧壁在栅极密封间隔物80上形成栅极间隔物82。可通过顺应性地(conformally)沉积绝缘材料并随后非等向性地蚀刻绝缘材料，以形成栅极间隔物82。栅极间隔物82的绝缘材料可为氮化硅、SiCN、其组合等。
在图10A及图10B中，源极/漏极区域86被形成在鳍片52中，以在各个通道区域58中施加应力(stress)，进而提高性能。源极/漏极区域86被形成在鳍片52中，使得每个虚拟栅极72被设置在对应的相邻的一对源极/漏极区域86之间。在一些实施例中，源极/漏极区域86可延伸到鳍片52中，且亦可以穿过鳍片52。在一些实施例中，栅极间隔物82及栅极密封间隔物80被用于以适当的横向距离将源极/漏极区域86与虚拟栅极72彼此分隔，使得源极/漏极区域86不会使后续形成的最终FinFET的栅极短路。
可通过遮蔽区域50P(例如：PMOS区域)以形成区域50N(例如：NMOS区域)中的源极/漏极区域86。接着通过在区域50N中蚀刻鳍片52的源极/漏极区域，以在鳍片52中形成凹槽(recess)。相邻的虚拟栅极72的栅极间隔物82之间的凹槽的宽度W1，可为约20纳米(nm)至约35nm，例如约25nm。如图10B所示，凹槽的至少一部分可在栅极间隔物82下方以垂直于基板50的主要表面的方向延伸。凹槽在相邻的虚拟栅极72的通道区域58之间的宽度W2，可为约20nm至约40nm，例如约30nm。从鳍片52的顶部表面所测量的凹槽的深度D1，可为约35nm至约60nm，例如约40nm。
接着，可使用外延沉积制程等在区域50N中生长源极/漏极区域86。可使用下列方法形成源极/漏极区域86：外延生长、CVD(例如：气相外延(vapor phase epitaxy,VPE))、原子层沉积(atomic layer deposition,ALD)、等离子体增强型化学气相沉积(plasma-enhanced CVD,PECVD)、等离子体增强型原子层沉积(PEALD)、分子束外延(molecular beamepitaxy,MBE)、金属有机CVD(metalorganic CVD,MOCVD)等。源极/漏极区域86可包括任何可接受的材料，例如适用于n型FinFET的材料。举例来说，若鳍片52为硅，则区域50N中的源极/漏极区域86可包括在通道区域58中施加拉伸应变(tensile strain)的材料，例如硅、SiC、SiCP、SiP等。在特定实施例中，源极/漏极区域86可包括SiP。源极/漏极区域86可使用硅前驱物及磷前驱物进行沉积，其中硅前驱物包括硅甲烷(SiH4)、二氯硅烷(dichlorosilane,DCS,SiH2Cl2)、二硅烷(disilane，DS,Si2H6)、三氯硅烷(trichlorosilane,SiHCl3)、四氯硅烷(tetrachlorosilane，SiCl4)、三硅烷(trisilane，Si3H8)、四硅烷(tetrasilane,Si4H10)、其组合等，而磷前驱物则包括磷化氢(phosphine，PH3)、三氯化磷(phosphorus trichloride，PCl3)等。可通过以约50sccm(单位时间标准毫升数)至约1000sccm(例如：约500sccm)的流量率(flowrate)使硅前驱物流动，并以约20sccm至约500sccm(例如：约300sccm)的流量率使磷前驱物流动，以形成源极/漏极区域86。如此一来，硅前驱物与磷前驱物的比为约1：1至约5：2，例如约5：3。源极/漏极区域86可具有约1×1021至约5×1021原子/cm3的磷浓度。源极/漏极区域86可具有固定的组成，使得与鳍片52相邻的磷浓度为约1×1021至约5×1021原子/cm3。
源极/漏极区域86可被以掺杂物物质(dopant species)掺杂，以进一步增加通道区域58中的拉伸应变，并减少掺杂物自源极/漏极区域86的向外扩散(out-diffusion)。举例来说，可将碳(碳所具有的晶格常数小于硅的晶格常数)并入到源极/漏极区域86中，以在通道区域58中提供额外的拉伸应变。源极/漏极区域86中所包含的磷亦可增加通道区域58中的拉伸应变。在用于形成源极/漏极区域86的沉积制程中，可通过包括碳前驱物的制程以碳对源极/漏极区域86进行原位掺杂，其中碳前驱物例如单甲基硅甲烷(monomethylsilane，MMS，CH6Si)、乙烯(ethylene，C2H4)等。含碳前驱物可以以约20sccm至约300sccm，例如约100sccm的流量率流动，并同时形成源极/漏极区域86，使得硅前驱物与碳前驱物的比为约1∶1至约25：1，例如约5：1。源极/漏极区域86可具有自约0.1原子百分比(atomic percent)到约2原子百分比的碳浓度。
源极/漏极区域86亦可以掺杂物物质掺杂，以便于减少或消除掺杂物物质自源极/漏极区域86到鳍片52的扩散。举例来说，可将具有比磷还低的扩散系数的砷并入源极/漏极区域86中，以降低掺杂物自源极/漏极区域86到鳍片52的扩散。碳亦可被包括在源极/漏极区域86中，以降低掺杂物自源极/漏极区域86到鳍片52的扩散。在源极/漏极区域86中包括低扩散系数物质，可减少来自源极/漏极区域86的漏电以及漏极引发能带负载(DIBL)。在用于形成源极/漏极区域86的沉积制程中，可通过包括砷前驱物的制程以砷对源极/漏极区域86进行原位掺杂，其中砷前驱物例如砷化氢(arsine,AsH3)、叔丁基胂(tertiarybutylarsine，TBA，C4H11As)等。含砷前驱物可以以约20sccm至约500sccm，例如约300sccm的流量率(flow rate)流动，同时形成源极/漏极区域86，使得硅前驱物与砷前驱物的比为约1：1至约25：1，例如约5：3。源极/漏极区域86可同时被碳及砷掺杂，且砷前驱物与碳前驱物的比为约1：1至约5：1，例如约3：1。源极/漏极区域86可具有约1×1020至约3×1021原子/cm3的砷浓度。
如图10B至图10D所示，源极/漏极区域86可包括单一连续材料，单一连续材料可包括SiP：As、SiP：C：As、SiP：C，且单一连续材料沿着整个凹槽接触鳍片52，源极/漏极区域86被形成在凹槽中，并延伸至高于鳍片52的顶部表面。源极/漏极区域86延伸至鳍片52上方的部分可具有端面(facet)。源极/漏极区域86可通过将鳍片52的表面直接曝露于硅前驱物、磷前驱物、碳前驱物、砷前驱物或其组合而形成。
在鳍片52中形成有LDD区域的实施例中，在形成源极/漏极区域86之后，LDD区域所具有的磷浓度可自约1x1019原子/cm3到约1x1020原子/cm3，例如约3x1020原子/cm3。在形成源极/漏极区域86之后，可不掺杂剩余的鳍片52。因此，在源极/漏极区域86与鳍片52之间，以及在源极/漏极区域86与LDD区域之间的界面处的磷浓度，可能存在阶段变化(stepchange)。源极/漏极区域86中的磷浓度与LDD区域中的磷浓度的比，可为约10：1至约500：1，例如约100：1。
可通过遮蔽区域50N(例如：NMOS区域)以形成区域50P(例如：PMOS区域)中的源极/漏极区域86。接着通过在区域50P中蚀刻鳍片52的源极/漏极区域，以在鳍片52中形成凹槽。然后，在凹槽中外延生长区域50P中的源极/漏极区域86。源极/漏极区域86可包括任何可接受的材料，例如适用于p型FinFET的材料。举例来说，若鳍片52为硅，则区域50P中的源极/漏极区域86可包括在通道区域58中施加压缩应变(compressive strain)的材料，例如SiGe、SiGeB、Ge、GeSn等。区域50P中的源极/漏极区域86亦可具有自鳍片52的对应表面凸起的表面，并可具有端面。
与先前讨论的用于形成轻度掺杂的源极/漏极区域的制程类似，可在区域50P中的源极/漏极区域86及/或鳍片52中布植掺杂物，以形成源极/及极区域，并接之以退火制程。源极/漏极区域可具有约1019原子/cm3至约1021原子/cm3的杂质浓度。用于源极/漏极区域的n型及/或p型杂质可为先前讨论的任何杂质。在一些实施例中，可以在生长期间原位掺杂源极/漏极区域86。
外延制程被用于在区域50N及区域50P中形成源极/漏极区域86如此一来，源极/漏极区域86的上方表面具有端面，这些端面横向地向外扩张并超过鳍片52的侧壁。在一些实施例中，这些端面导致相同FinFET的相邻源极/漏极区域86的合并，如图10C所示。在其他实施例中，如图10D所示，在外延制程完成后，相邻的源极/漏极区域86维持分离。
以低扩散掺杂物共掺杂(co-doping)区域50N中的源极/漏极区域86，允许在源极/漏极区域86的整个体积中使用磷浓度更高的材料，同时减少漏电及DIBL，这降低了源极/漏极区域86的整体电阻。这进而改善了包括共掺杂的源极/漏极区域86的晶体管的直流电流增益及振荡器速度，装置性能因此得到了改善。
在图11A及图11B中，第一层间介电质(interlayer dielectric,ILD)88被沉积在图10A至图10D所示的结构上。第一层间介电质88可由介电材料形成，并可通过任何合适的方法来沉积，例如CVD、等离子体增强型CVD(PECVD)、或是FCVD。介电材料可包括磷硅酸盐玻璃(phosphosilicate glass,PSG)、硼硅酸盐玻璃(borosilicate glass,BSG)、掺硼磷硅酸盐玻璃(boron-doped phosphosilicate glass,BPSG)、未掺杂的硅酸盐玻璃(undopedsilicate glass,USG)等。亦可使用通过任何可接受的方法形成的其他绝缘材料。在一些实施例中，接触蚀刻停止层(contact etch stop layer,CESL)87被设置在第一层间介电质88与源极/漏极区域86、遮罩74、栅极间隔物82、以及栅极密封间隔物80之间。接触蚀刻停止层87可包括介电材料，例如氮化硅、氧化硅、氮氧化硅等，它们的蚀刻速率不同于上方的第一层间介电质88的材料。
在图12A及图12B中，可执行诸如CMP的平坦化制程，以使第一层间介电质88的顶部表面与虚拟栅极72或遮罩74的顶部表面呈水平。平坦化制程亦可移除虚拟栅极72上的遮罩74，以及移除栅极密封间隔物80及栅极间隔物82沿着遮罩74的侧壁的那些部分。在平坦化制程后，虚拟栅极72、栅极密封间隔物80、栅极间隔物82、第一层间介电质88、以及接触蚀刻停止层87的顶部表面彼此间可呈水平。因此，虚拟栅极72的顶部表面可经由第一层间介电质88而曝露。在一些实施例中，可保留遮罩74，在这种案例中，平坦化制程会使第一层间介电质88的顶部表面与遮罩74的顶部表面呈水平。
在图13A及图13B中，虚拟栅极72以及遮罩74(若存在的话)在一或多个蚀刻操作中被移除，因此形成了凹槽90。虚拟介电层60在凹槽90中的部分亦可被移除。在一些实施例中，仅有虚拟栅极72被移除，而虚拟介电层60被留下并经由凹槽90而曝露。在一些实施例中，虚拟介电层60自晶粒(die)的第一区域(例如：核心逻辑区域)中的凹槽90中被移除，但被保留在晶粒的第二区域(例如：输入/输出区域)中的凹槽90中。在一些实施例中，经由非等向性干式蚀刻制程移除虚拟栅极72。举例来说，蚀刻制程可包括使用反应气体的干式蚀刻制程，这些反应气体选择性地蚀刻虚拟栅极72，而不蚀刻第一层间介电质88或栅极间隔物82。每个凹槽90曝露对应的鳍片52的通道区域58。每个通道区域58被设置在相邻且成对的源极/漏极区域86之间。在移除期间，当蚀刻虚拟栅极72时，虚拟介电层60可被用作蚀刻停止层。在移除虚拟栅极72后，虚拟介电层60可接着被选择性地移除。
在图14A及图14B中，栅极介电层92及栅极电极94被形成以替换栅极。图14C显示了图14B的区域91的详细附图。栅极介电层92被顺应性地沉积在凹槽90中，例如在鳍片52的顶部表面及侧壁上，以及在栅极密封间隔物80/栅极间隔物82的侧壁上。栅极介电层92亦可被形成在第一层间介电质88的顶部表面上。在一些实施例中，栅极介电层92包括高k值介电材料，且在这些实施例中，栅极介电层92可具有大于约7.0的k值，且栅极介电层92可包括Hf、Al、Zr、La、Mg、Ba、Ti、Pb、或其组合的金属氧化物或硅酸盐(silicate)。可通过分子束沉积(molecular-beam deposition,MBD)、ALD、PECVD等来沉积栅极介电层92。在虚拟介电层60的一部分被保留在凹槽90中的实施例中，栅极介电层92包括虚拟介电层60的材料(例如：SiO2)。
栅极电极94被沉积在栅极介电层92上，并填充凹槽90的剩余部分。栅极电极94可包括含金属的材料，例如TiN、TiO、TaN、TaC、Co、Ru、Al、W、其组合、或其多层。尽管在图14B中所示是单层的栅极电极94，但栅极电极94可包括任意数量的薄层，例如任意数量的衬垫(liner)层94A、任意数量的功函数调谐(work function tuning)层94B、以及填充材料94C，如图14C所示。在填充栅极电极94之后，可执行诸如CMP的平坦化制程，以移除栅极介电层92及栅极电极94的多余部分，例如栅极介电层92及栅极电极94被设置在第一层间介电层88的顶部表面上的部分。栅极介电层92及栅极电极94的剩余部分形成最终获得的FinFET的替换栅极。栅极电极94及栅极介电层92可共同被称作“栅极”、“替换栅极”、或是“栅极堆叠”。栅极堆叠可沿着鳍片52的通道区域58的侧壁延伸。
在区域50N及区域50P中，栅极介电层92的形成可同时发生，使得每个区域中的栅极介电层92由相同的材料形成，而栅极电极94的形成可同时发生，使得每个区域中的栅极电极94由相同的材料形成。在一些实施例中，每个区域中的栅极介电层92可通过不同的制程形成，使得区域50N与区域50P中的栅极介电层92可以是不同的材料，及/或每个区域中的栅极电极94可通过不同的制程形成，使得区域50N与区域50P中的栅极电极94可以是不同的材料。当使用不同的制程时，各种遮蔽操作可被用于遮蔽及曝露适当的区域。
在图15A及图15B中，第二层间介电质108被沉积在第一层间介电质88上。在一些实施例中，第二层间介电质108是通过流动式CVD方法形成的可流动薄膜。在一些实施例中，第二层间介电质108是由诸如PSG、BSG、BPSG、USG等的介电材料所形成，且可通过诸如CVD及PECVD的任何合适的方法来进行沉积。根据一些实施例，在形成第二层间介电质108之前，可掘入栅极堆叠(包括栅极介电层92及栅极电极94)，使得栅极凹槽被形成在栅极堆叠的正上方以及栅极密封间隔物80的相对部分之间，如图15A及图15B所示。包括一或多层介电材料(例如：氮化硅、氮氧化硅等)的栅极遮罩96被填充在凹槽中，接着执行平坦化制程以移除在第一层间介电质88的顶部表面上延伸的介电材料的多余部分。随后形成栅极接点(contact)110(显示于图17A及图17B中)，穿过栅极遮罩96以接触被掘入的栅极电极94的顶部表面。
在图16A及图16B中，开口111被形成并延伸穿过第二层间介电质108、第一层间介电质88、以及接触蚀刻停止层87而抵达源极/漏极区域86之中，且硅化区(silicideregion)98被形成于源极/漏极区域86中。开口111可通过可接受的蚀刻制程来形成，例如包括RIE、NBE等的非等向性蚀刻制程。开口111可以深度D2延伸至源极/漏极区域86中，深度D2的测量是自源极/漏极区域86的顶部表面测量到开口111的底部表面，深度D2自约5nm至约15nm，例如约10nm。硅化区98的形成可通过下列方法执行，首先在源极/漏极区域86上沉积用于形成硅化或锗化区的可与半导体材料(例如：硅或锗)反应的金属，例如镍、钴、钛、钽、铂、钨、其他贵金属(noble metal)、其他耐火金属(refractory metal)、稀土金属(rareearth metal)、或其合金。接着使用热退火制程以形成硅化区98。沉积的金属的任何未反应部分被移除，例如通过蚀刻制程移除。在特定实施例中，硅化区98包括TiSi。尽管硅化区98被称为“硅化区”，但硅化区98亦可为锗化区或硅锗化区(例如：包括硅化物和锗化物的区域)。硅化区域98的厚度T1可自约2nm到约10nm，例如约6nm。
在图17A及图17B中，根据一些实施例，栅极接点110及源极/漏极接点112被形成，并穿过第二层间介电质108及第一层间介电质88。源极/漏极接点112被形成在开口111中。穿过第二层间介电质108及栅极遮罩96形成用于栅极接点110的开口。可使用可接受的微影及蚀刻技术来形成用于栅极接点110的开口。在开口111以及用于栅极接点110的开口中形成诸如扩散阻挡层(diffusion barrier layer)、粘着层(adhesion layer)等的衬垫及导电材料。衬垫可包括钛、氮化钛、钽、氮化钽等。导电材料可为铜、铜合金、银、金、钨、钴、铝、镍等。可执行诸如CMP的平坦化制程，以自第二层间介电质108的表面移除多余的材料。剩余的衬垫及导电材料在开口111与用于栅极接点110的开口中形成源极/漏极接点112及栅极接点110。在一些实施例中，可通过在沉积源极/漏极接点112后执行的退火制程，在源极/漏极区域86与源极/漏极接点112之间的界面处，形成诸如硅化区98的硅化物。源极/漏极接点112物理性地并电性地耦接至源极/漏极区域86，而栅极接点110物理性地并电性地耦接至栅极电极94。源极/漏极接点112及栅极接点110可在不同的制程中形成，或者，可在相同的制程中形成。尽管显示为被形成相同的横截面，但应理解的是，每个源极/漏极接点112以及栅极接点110，可被形成为不同的横截面，这可避免接点的短路。
如上所述，形成掺杂有低扩散率掺杂物的半导体材料的源极/漏极区域86，可降低源极/漏极区域86的漏电及DIBL，并同时允许源极/漏极区域86具有较高的掺杂物浓度，这会降低源极/漏极区域86的整体电阻。这改善了包括源极/漏极区域86的装置的装置直流电流增益及振荡器速度，并使得装置的性能得到了改进。
根据一个实施例，一种半导体装置制造方法包括蚀刻一半导体鳍片以形成第一凹槽，上述半导体鳍片定义第一凹槽的多个侧壁及底部表面，上述半导体鳍片在第一方向上延伸；在第一凹槽中形成源极/漏极区域，源极/漏极区域包括单一连续材料，单一连续材料自第一凹槽的底部表面延伸至高于上述半导体鳍片的顶部表面，用于形成源极/漏极区域的前驱物气体包括磷化氢(PH3)，以及包括砷化氢(AsH3)或单甲基硅甲烷(CH6Si)中的至少一者；以及在相邻于源极/漏极区域的上述半导体鳍片上形成一栅极，上述栅极在垂直于第一方向的第二方向上延伸。在一个实施例中，源极/漏极区域是形成在半导体装置的NMOS区域中。在一个实施例中，源极/漏极区域是在自摄氏400度至摄氏800度的温度下形成。在一个实施例中，源极/漏极区域是在自5托至600托的压力下形成。在一个实施例中，第一凹槽具有低于上述半导体鳍片的顶部表面自35纳米至60纳米的深度，以及具有自20纳米至35纳米的宽度。在一个实施例中，源极/漏极区域具有自1x1021至5x1021原子/立方厘米的磷浓度，以及具有自0.1至2原子百分比碳浓度。在一个实施例中，源极/漏极区域具有自1x1021至5x1021原子/立方厘米的磷浓度，以及具有自1x1020至3x1021原子/立方厘米的砷浓度。
根据另一个实施例，一种半导体装置制造方法包括形成延伸自基板的一鳍片；在上述鳍片上形成栅极堆叠；形成沿着栅极堆叠的侧壁的栅极间隔物；蚀刻上述鳍片以形成第一凹槽，第一凹槽在栅极间隔物下以垂直于基板的主要表面的方向延伸；以及在第一凹槽中外延沉积源极/漏极材料，源极/漏极材料包括以砷掺杂的SiP，源极/漏极材料在栅极间隔物下以垂直于基板的主要表面的方向延伸，源极/漏极材料接触上述鳍片的水平表面以及垂直表面。在一个实施例中，源极/漏极材料具有自1x1021至5x1021原子/立方厘米的磷浓度，以及具有自1x1020至3x1021原子/立方厘米的砷浓度。在一个实施例中，源极/漏极材料还包括碳，且其中源极/漏极材料具有自1x1021至5x1021原子/立方厘米的磷浓度，以及具有自0.1至2原子百分比的碳浓度。在一个实施例中，源极/漏极材料具有自1x1020至3x1021原子/立方厘米的砷浓度。在一个实施例中，上述方法还包括在源极/漏极材料的顶部表面上形成硅化区，硅化区具有自2纳米至10纳米的厚度。在一个实施例中，硅化区包括TiSi。在一个实施例中，上述方法还包括形成源极/漏极接点以与硅化区接触，源极/漏极接点延伸到源极/漏极材料之中，且延伸到低于源极/漏极材料的顶部表面自5纳米至15纳米。在一个实施例中，源极/漏极接点包括钨。
根据又一个实施例，一种半导体装置制造方法包括蚀刻半导体鳍片以形成一凹槽；在上述凹槽中形成源极/漏极区域，源极/漏极区域包括半导体材料，半导体材料包括以砷及碳掺杂的SiP，以砷及碳掺杂的SiP沿着上述凹槽的侧壁及底部表面接触半导体鳍片；在相邻于源极/漏极区域的半导体鳍片上形成一栅极；在源极/漏极区域中形成硅化区；以及形成延伸至硅化区中的源极/漏极接点。在一个实施例中，硅化区包括TiSi，而源极/漏极接点包括钨。在一个实施例中，源极/漏极区域具有自1x1021至5x1021原子/立方厘米的磷浓度、具有自1x1020至3x1021原子/立方厘米的砷浓度、以及自0.1至2原子百分比的碳浓度。在一个实施例中，源极/漏极区域的形成是使用第一前驱物以及第二前驱物，第一前驱物包括硅甲烷(SiH4)、二氯硅烷(SiH2Cl2)、或二硅烷(Si2H6)中的至少一者，而第二前驱物包括磷化氢(PH3)、砷化氢(AsH3)、以及单甲基硅甲烷(CH6Si)。在一个实施例中，源极/漏极区域是在自摄氏400度至摄氏800度的温度下，以及5托至600托的压力下形成。
前述内文概述多项实施例或范例的特征，如此可使于本技术领域中技术人员更佳地了解本公开的态样。本技术领域中技术人员应当理解他们可轻易地以本公开为基础设计或修改其他制程及结构，以完成相同的目的及/或达到与本文介绍的实施例或范例相同的优点。本技术领域中技术人员亦需理解，这些等效结构并未脱离本公开的精神及范围，且在不脱离本公开的精神及范围的情况下，可对本公开进行各种改变、置换以及变更。

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1.一种半导体装置的制造方法，包括：
蚀刻一半导体鳍片以形成一第一凹槽，上述半导体鳍片定义上述第一凹槽的多个侧壁及一底部表面，上述半导体鳍片在一第一方向上延伸；
在上述第一凹槽中形成一源极/漏极区域，上述源极/漏极区域包括一单一连续材料，上述单一连续材料自上述第一凹槽的底部表面延伸至高于上述半导体鳍片的顶部表面，用于形成上述源极/漏极区域的一前驱物气体包括磷化氢，以及包括砷化氢或单甲基硅甲烷中的至少一者；以及
在相邻于上述源极/漏极区域的上述半导体鳍片上形成一栅极，上述栅极在垂直于上述第一方向的一第二方向上延伸。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210391464A1 (en) * 2020-06-10 2021-12-16 Samsung Electronics Co., Ltd. Integrated circuit device

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8497528B2 (en) * 2010-05-06 2013-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a strained structure
US9245805B2 (en) 2009-09-24 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Germanium FinFETs with metal gates and stressors
US8962400B2 (en) 2011-07-07 2015-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. In-situ doping of arsenic for source and drain epitaxy
US20130011984A1 (en) * 2011-07-07 2013-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Using Hexachlorodisilane as a Silicon Precursor for Source/Drain Epitaxy
US9236267B2 (en) 2012-02-09 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cut-mask patterning process for fin-like field effect transistor (FinFET) device
US9142643B2 (en) * 2012-11-15 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming epitaxial feature
US8987791B2 (en) * 2013-02-27 2015-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and methods for forming the same
US9159824B2 (en) 2013-02-27 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with strained well regions
US9093514B2 (en) 2013-03-06 2015-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Strained and uniform doping technique for FINFETs
US9029226B2 (en) * 2013-03-13 2015-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for doping lightly-doped-drain (LDD) regions of finFET devices
US9570586B2 (en) * 2013-11-20 2017-02-14 Globalfoundries Inc. Fabrication methods facilitating integration of different device architectures
KR102105363B1 (ko) * 2013-11-21 2020-04-28 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US9136106B2 (en) 2013-12-19 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
US9608116B2 (en) 2014-06-27 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. FINFETs with wrap-around silicide and method forming the same
US9406752B2 (en) * 2014-12-29 2016-08-02 Globalfoundries Inc. FinFET conformal junction and high EPI surface dopant concentration method and device
US9418897B1 (en) 2015-06-15 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Wrap around silicide for FinFETs
US9520482B1 (en) 2015-11-13 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting metal gate
US10276715B2 (en) * 2016-02-25 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor and method for fabricating the same
US9570556B1 (en) * 2016-03-03 2017-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9812363B1 (en) 2016-11-29 2017-11-07 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of forming same
WO2018111251A1 (en) * 2016-12-14 2018-06-21 Intel Corporation Transistor source/drain amorphous interlayer arrangements

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210391464A1 (en) * 2020-06-10 2021-12-16 Samsung Electronics Co., Ltd. Integrated circuit device
US11575044B2 (en) * 2020-06-10 2023-02-07 Samsung Electronics Co., Ltd. Integrated circuit device

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