CN111968970B - 一种esd保护器件 - Google Patents

一种esd保护器件 Download PDF

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CN111968970B
CN111968970B CN202010886061.8A CN202010886061A CN111968970B CN 111968970 B CN111968970 B CN 111968970B CN 202010886061 A CN202010886061 A CN 202010886061A CN 111968970 B CN111968970 B CN 111968970B
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李泽宏
程然
王志明
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University of Electronic Science and Technology of China
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    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/7404—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device
    • H01L29/7412—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device the device being a diode

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Abstract

本发明属于功率半导体技术领域，涉及一种ESD保护器件。本发明相比于传统的横向SCR，优化了体内的电场分布，增大了体内的过电流面积，从而增大了器件的过电流能力，提高了器件的ESD保护能力，同时通过深槽的结构，减小了器件的横扩，可以实现在相同面积下更高的维持电压。本发明既充分利用SCR结构强泄流能力的特点，又通过深槽结构实现SCR在相同面积下更高的维持电压，可以实现高维持电压、低导通电阻、强鲁棒性等ESD保护性能。

Description

一种ESD保护器件
技术领域
本发明属于功率半导体技术领域，具体涉及一种ESD保护器件。
背景技术
静电放电(electro-static discharge,ESD)指静电电荷在两个不同静电电位的媒体间发生相互转移的超速放电现象。放电时其速度往往处于纳秒量级并伴随着极大的电流。在集成电路迅猛发展的今天，芯片的尺寸不断减小。许多消费级电子产品的工作电压越来越低，除此之外由于主板面积的小型化，也使得消费级电子设备对静电放电更加敏感。例如笔记本电脑，手机，硬盘等电子产品，由于频繁的和人体接触极易受到静电放电的冲击，如果没有选择合适的保护器件，可能会造成机器的性能不稳定甚至损坏，造成设备制造商和消费者的损失。因此，研究高性能、高可靠性的ESD防护器件对提高集成电路的成品率和可靠性具有至关重要的作用。
通常用作ESD保护的器件有二极管、GGNMOS(栅接地的NMOS)、BJT(三极管)、SCR(可控硅)等。但在某些特定应用中，需要ESD保护器件具有特定的触发电压，电流泄放能力较强，同时还需要降低ESD器件的寄生电容。这就需要在进行ESD保护器件的设计时需要考虑泄放电流、触发电压、保持电压和寄生电容等参数的折中。
发明内容
本发明是提供一种新型ESD保护器件，用于解决现有的ESD器件小面积和高性能的矛盾。
本发明的技术方案是：一种ESD保护器件，如图2所示，包括P型衬底201和位于P型衬底201上表面的N型外延层202；在N型外延层202上层一侧具有P型重掺杂区203和N型重掺杂区204，P型重掺杂区203和N型重掺杂区204之间有间距且N型重掺杂区204位于外侧；N型外延层202、P型重掺杂区203和N型重掺杂区204上表面具有隔离介质层205，隔离介质层205上表面一侧具有阳极金属层206，且阳极金属层206贯穿P型重掺杂区203和N型重掺杂区204上表面的隔离介质层205从而与P型重掺杂区203和N型重掺杂区204接触；
在N型外延层202上层另一侧，具有P型重掺杂扩散区209和N型重掺杂扩散区211，P型重掺杂扩散区209和N型重掺杂扩散区211之间有间距且P型重掺杂扩散区209位于外侧，在P型重掺杂扩散区209和N型重掺杂扩散区211中均具有多个沟槽；
在隔离介质层205上表面另一侧具有阴极金属层207，且阴极金属层207贯穿隔离介质层205从而与P型重掺杂扩散区209和N型重掺杂扩散区211接触。
进一步的，所述介质层205采用的材料为二氧化硅。
上述方案中的P型重掺杂扩散区209和N型重掺杂扩散区211分别是由P型重掺杂沟槽区210和N型重掺杂沟槽区212经过高温退火扩散形成的。
本发明的有益效果为：相比于传统的横向SCR，本发明优化了体内的电场分布，增大了体内的过电流面积，从而增大了器件的过电流能力，提高了器件的ESD保护能力，同时通过深槽的结构，减小了器件的横扩，可以实现在相同面积下更高的维持电压。本发明既充分利用SCR结构强泄流能力的特点，又通过深槽结构实现SCR在相同面积下更高的维持电压，可以实现高维持电压、低导通电阻、强鲁棒性等ESD保护性能。
附图说明
图1为常规的横向SCR结构示意图；
附图标记说明：P型衬底101，N型阱区102，P型重掺杂区103，N型重掺杂区104，隔离介质层105，阳极金属层106，阴极金属层107，P型重掺杂扩散区109，N型重掺杂扩散区110。
图2为本发明中SCR的结构示意图；
图3为本发明和其他器件组合应用连接方式示意图。
附图标记说明：P型衬底201，N型外延层202，P型重掺杂区203，N型重掺杂区204，隔离介质层205，阳极金属层206，阴极金属层207，P型重掺杂扩散区209，P型重掺杂沟槽区210，N型重掺杂扩散区211，N型重掺杂沟槽区212，图3是本发明的衍生结构，其中213为N型重掺杂区，214为STI隔离。
具体实施方式
下面结合附图，详细描述本发明的技术方案：
如图2所示，本发明的ESD保护器件，包括P型衬底201，N型外延层202，P型重掺杂区203，N型重掺杂区204，隔离介质层205，阳极金属层206，阴极金属层207，P型重掺杂扩散区209，P型重掺杂沟槽区210，N型重掺杂扩散区211，N型重掺杂沟槽区212。所述的N型外延层202形成于P型衬底201上；所述的P型重掺杂区203以及N型重掺杂区204位于N型外延层202内部上表面，并且通过阳极金属层206短接；所述的P型重掺杂沟槽区210和N型重掺杂沟槽区212位于N型外延层202内部上表面，并且通过阴极金属层207相短接；所述的P型重掺杂沟槽区210和N型重掺杂沟槽区212底部位于P型衬底201内；所述的P型重掺杂区203、N型重掺杂区204、P型重掺杂扩散区209、P型重掺杂沟槽区210、N型重掺杂扩散区211、N型重掺杂沟槽区212与N型外延层202通过隔离介质层205隔离。
特别地，所述的P型重掺杂扩散区209和N型重掺杂扩散区211分别是由和P型重掺杂沟槽区210和N型重掺杂沟槽区212经过高温退火扩散形成的。
如图3所示，在图2的基础上加入了N型重掺杂区213和STI隔离214。
本实施例的工作原理如下：
本发明提供一种新型ESD保护器件，P型重掺杂区203、N型外延层202、P型重掺杂扩散区209形成PNP双极晶体管，N型重掺杂区204、P型衬底201、N型重掺杂沟槽区211形成NPN三极管，当阳极金属层206上电压较小时，两个双极晶体管均处于截止状态，集电极电流由集电结的反向漏电构成，电流增益非常小，SCR结构呈现高阻状态；随着阳极金属层206上电压不断增加，N型外延层202和P型衬底201的PN结耗尽区会随之扩展，直至发生雪崩击穿。当雪崩击穿发生时，碰撞电离产生的电子会流向N型外延层202，空穴会流向P型衬底201。当电子电流在N型外延层202上产生的压降和在P型衬底201上产生的压降足以使两个双极晶体管的发射结开启时，两个双极晶体管开启。并且由于两个双极晶体管的基极分别与另一个双极晶体管的集电极耦合，电流会被互相放大，两者形成正反馈，SCR触发从而获得极强的电流泄放能力。并且本发明优化了体内的电场分布，增大了体内的过电流面积，从而增大了器件的过电流能力，提高了器件的ESD保护能力，同时通过深槽的结构，减小了器件的横扩，可以实现在相同面积下更高的维持电压。同时，在此基础上加入了N型重掺杂区213和STI隔离214，形成了与SCR器件工艺兼容的二极管，通过串联二极管的形式，实现ESD器件的超低电容，更有利于降低对系统影响，应用于高速接口。

Claims (2)

1.一种ESD保护器件，其特征在于，包括P型衬底(201)和位于P型衬底(201)上表面的N型外延层(202)；在N型外延层(202)上层一侧具有P型重掺杂区(203)和N型重掺杂区(204)，P型重掺杂区(203)和N型重掺杂区(204)之间有间距且N型重掺杂区(204)位于外侧；N型外延层(202)、P型重掺杂区(203)和N型重掺杂区(204)上表面具有隔离介质层(205)，隔离介质层(205)上表面一侧具有阳极金属层(206)，且阳极金属层(206)贯穿P型重掺杂区(203)和N型重掺杂区(204)上表面的隔离介质层(205)从而与P型重掺杂区(203)和N型重掺杂区(204)接触；
在N型外延层(202)上层另一侧，具有P型重掺杂扩散区(209)和N型重掺杂扩散区(211)，P型重掺杂扩散区(209)和N型重掺杂扩散区(211)之间有间距且P型重掺杂扩散区(209)位于外侧，在P型重掺杂扩散区(209)和N型重掺杂扩散区(211)中均具有多个沟槽；
在隔离介质层(205)上表面另一侧具有阴极金属层(207)，且阴极金属层(207)贯穿隔离介质层(205)从而与P型重掺杂扩散区(209)和N型重掺杂扩散区(211)接触。
2.根据权利要求1所述的一种ESD保护器件，其特征在于，所述介质层(205)采用的材料为二氧化硅。
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