CN111916496A - IGBT grid bus structure - Google Patents

IGBT grid bus structure Download PDF

Info

Publication number
CN111916496A
CN111916496A CN202010557347.1A CN202010557347A CN111916496A CN 111916496 A CN111916496 A CN 111916496A CN 202010557347 A CN202010557347 A CN 202010557347A CN 111916496 A CN111916496 A CN 111916496A
Authority
CN
China
Prior art keywords
grid
gate
oxide layer
field oxide
polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202010557347.1A
Other languages
Chinese (zh)
Other versions
CN111916496B (en
Inventor
郑婷婷
李宇柱
李伟邦
骆健
董长城
叶枫叶
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanruilianyan Semiconductor Co ltd
Original Assignee
Nanruilianyan Semiconductor Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanruilianyan Semiconductor Co ltd filed Critical Nanruilianyan Semiconductor Co ltd
Priority to CN202010557347.1A priority Critical patent/CN111916496B/en
Publication of CN111916496A publication Critical patent/CN111916496A/en
Application granted granted Critical
Publication of CN111916496B publication Critical patent/CN111916496B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention discloses an IGBT grid bus structure, which comprises a substrate, a field oxide layer and grid polycrystalline silicon, wherein the field oxide layer and the grid polycrystalline silicon are sequentially arranged from outside to inside along one end of the upper surface of the substrate; the field oxide layer is covered on the upper surface of the substrate, the field oxide layer is covered on the upper surface of the field oxide layer, the grid polysilicon is covered on the upper surface of the field oxide layer, and a grid contact hole is formed in the dielectric layer on the upper surface of the grid polysilicon; the upper surface of the grid polysilicon is prevented from steps and unevenness, and when the grid contact hole is etched in the dielectric layer on the upper surface of the grid polysilicon, the influence of the unevenness on the upper surface of the grid polysilicon is avoided, and the complete grid contact hole can be etched.

Description

IGBT grid bus structure
Technical Field
The invention relates to the technical field of power semiconductor devices, in particular to an IGBT grid bus structure.
Background
An Insulated Gate Bipolar Transistor (IGBT) chip combines the advantages of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) and a Bipolar Junction Transistor (BJT), and has the characteristics of high input impedance, low voltage control power consumption, simple control circuit, high voltage resistance, large current bearing, and the like, and thus is widely applied to various power conversion. The IGBT grid bus has the functions of synchronously opening all cells of the chip and the like, and the performance of the IGBT chip can be effectively improved by reasonably designing the grid bus.
Fig. 1 is a conventional gate bus structure, which includes a field oxide layer 1, a gate polysilicon 2, a gate metal 3, a gate contact hole 4, etc., wherein the gate polysilicon 2 overlaps the field oxide layer 1, and the gate polysilicon 2 is located above the field oxide layer 1, because the field oxide layer 1 has a certain thickness, after the gate polysilicon 2 overlaps the field oxide layer 1, a step is easily formed at the junction to cause unevenness of the surface of the gate polysilicon 2; when the dielectric layer 5 above the gate polysilicon 2 is provided with the gate contact hole 4, process defects are easily generated due to the uneven surface of the gate polysilicon 2.
Disclosure of Invention
The invention aims to provide an IGBT grid bus structure, which aims to solve the problems that in the prior art, the surface of grid polycrystalline silicon is uneven, and when a grid contact hole is formed in a dielectric layer above the grid polycrystalline silicon, process defects are easy to occur.
In order to achieve the purpose, the invention provides the following technical scheme:
the invention provides an IGBT grid bus structure, which comprises a substrate, a field oxide layer and grid polycrystalline silicon, wherein the field oxide layer and the grid polycrystalline silicon are sequentially arranged from outside to inside along one end of the upper surface of the substrate;
the field oxide layer is covered on the upper surface of the substrate, the field oxide layer is covered on the upper surface of the field oxide layer, the grid polysilicon is covered on the upper surface of the field oxide layer, and a grid contact hole is formed in the dielectric layer on the upper surface of the grid polysilicon.
Furthermore, an active area groove gate is arranged on the upper surface of the substrate, one end of the active area groove gate extends to the lower part of the grid polycrystalline silicon, groove polycrystalline silicon is filled in the active area groove gate, and the groove polycrystalline silicon is connected with the grid polycrystalline silicon.
Furthermore, the distance D between one end of the active region trench gate close to the grid polysilicon and one end of the grid contact hole far away from the field oxide layer is larger than 0.
Furthermore, the field oxide layer is parallel to the grid polysilicon, and the active region trench gate is vertical to the grid polysilicon.
Furthermore, the inner surface of the trench gate of the active area and the whole upper surface of the substrate are coated with a gate oxide layer.
Furthermore, a grid metal is arranged on the upper surface of the dielectric layer, a conductor is filled in the grid contact hole, one end of the conductor is connected with the grid polycrystalline silicon, and the other end of the conductor is connected with the grid metal.
Compared with the prior art, the invention has the beneficial effects that:
according to the IGBT grid bus structure provided by the invention, the grid contact hole is formed in the dielectric layer on the upper surface of the grid polysilicon, the field oxide layer and the grid polysilicon are sequentially arranged from outside to inside along one end of the upper surface of the substrate, and the gap is reserved between the field oxide layer and the grid polysilicon, so that the upper surface of the grid polysilicon is prevented from having steps and unevenness, when the grid contact hole is etched in the dielectric layer on the upper surface of the grid polysilicon, the influence of the unevenness of the upper surface of the grid polysilicon is avoided, and the complete grid contact hole can be etched.
Drawings
FIG. 1 is a schematic diagram of a conventional gate bus;
fig. 2 is a schematic structural diagram of an IGBT gate bus structure provided by an embodiment of the present invention in one state;
fig. 3 is a schematic structural diagram of an IGBT gate bus structure according to an embodiment of the present invention in another state.
In the figure: 1-field oxide layer, 2-grid polycrystalline silicon, 3-grid metal, 4-grid contact hole, 5-dielectric layer, 6-conductor, 7-active region groove grid, 8-grid oxide layer, 9-groove polycrystalline silicon and 10-substrate.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 2 and fig. 3, the IGBT gate bus structure according to an embodiment of the present invention includes a substrate 10, a field oxide layer 1 and a gate polysilicon 2 sequentially disposed from outside to inside along an end of an upper surface of the substrate 10, and a gap is left between the field oxide layer 1 and the gate polysilicon 2;
the field oxide layer is characterized by further comprising a dielectric layer 5, the dielectric layer 5 covers the whole upper surface of the substrate 10 and the upper surfaces of the field oxide layer 1 and the grid polysilicon 2, and a grid contact hole 4 is formed in the dielectric layer 5 on the upper surface of the grid polysilicon 2.
An active region trench gate 7 is arranged on the upper surface of the substrate 10, one end of the active region trench gate 7 extends to the lower part of the grid polysilicon 2, the active region trench gate 7 is filled with trench polysilicon 9, the trench polysilicon 9 is connected with the grid polysilicon 2, and grid current is introduced.
The distance D between one end of the active region trench gate 7 close to the gate polysilicon 2 and one end of the gate contact hole 4 far away from the field oxide layer 1 is more than 0.
The field oxide layer 1 and the grid polysilicon 2 are parallel, and the active region trench gate 7 is vertical to the grid polysilicon 2.
A layer of gate oxide layer 8 is coated on the inner surface of the active region trench gate 7 and the whole upper surface of the substrate 10, and the gate oxide layer 8 is used for isolating trench polysilicon 8 filled in the active region trench gate 7 from the substrate 10 on one hand and isolating the substrate 10 from components arranged on the upper surface of the substrate 10 on the other hand.
The upper surface of the dielectric layer 5 is provided with a gate metal 3, a conductor 6 is filled in the gate contact hole 4, one end of the conductor 6 is connected with the gate polysilicon 2, and the other end is connected with the gate metal 3.
According to the IGBT grid bus structure provided by the invention, the grid contact hole 4 is formed in the dielectric layer 5 on the upper surface of the grid polysilicon 2, the field oxide layer 1 and the grid polysilicon 2 are sequentially arranged from outside to inside along one end of the upper surface of the substrate 10, and a gap is left between the field oxide layer 1 and the grid polysilicon 2, so that the upper surface of the grid polysilicon 2 is prevented from having steps and unevenness, when the grid contact hole 4 is etched in the dielectric layer 5 on the upper surface of the grid polysilicon 2, the influence of the unevenness of the upper surface of the grid polysilicon 2 is avoided, and the complete grid contact hole 4 can be etched.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Claims (6)

1. An IGBT gate bus structure, characterized by: the field oxide layer structure comprises a substrate (10), a field oxide layer (1) and grid polysilicon (2) which are sequentially arranged from outside to inside along one end of the upper surface of the substrate (10), and a gap is reserved between the field oxide layer (1) and the grid polysilicon (2);
the field oxide layer-silicon-based grid electrode structure is characterized by further comprising a dielectric layer (5), wherein the dielectric layer (5) covers the whole upper surface of the substrate (10) and the upper surfaces of the field oxide layer (1) and the grid electrode polycrystalline silicon (2), and a grid electrode contact hole (4) is formed in the dielectric layer (5) on the upper surface of the grid electrode polycrystalline silicon (2).
2. The IGBT gate bus structure of claim 1, wherein: an active area groove gate (7) is arranged on the upper surface of the substrate (10), one end of the active area groove gate (7) extends to the lower portion of the grid polycrystalline silicon (2), groove polycrystalline silicon (9) is filled in the active area groove gate (7), and the groove polycrystalline silicon (9) is connected with the grid polycrystalline silicon (2).
3. The IGBT gate bus structure of claim 2, wherein: the distance D between one end of the active region trench gate (7) close to the grid polysilicon (2) and one end of the grid contact hole (4) far away from the field oxide layer (1) is larger than 0.
4. The IGBT gate bus structure of claim 2, wherein: the field oxide layer (1) and the grid polycrystalline silicon (2) are parallel, and the active region trench gate (7) is vertical to the grid polycrystalline silicon (2).
5. The IGBT gate bus structure of claim 2, wherein: and a gate oxide layer (8) is coated on the inner surface of the active region trench gate (7) and the whole upper surface of the substrate (10).
6. The IGBT gate bus structure of claim 1, wherein: the upper surface of the dielectric layer (5) is provided with gate metal (3), the gate contact hole (4) is filled with a conductor (6), one end of the conductor (6) is connected with the gate polysilicon (2), and the other end of the conductor is connected with the gate metal (3).
CN202010557347.1A 2020-06-18 2020-06-18 IGBT grid bus structure Active CN111916496B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010557347.1A CN111916496B (en) 2020-06-18 2020-06-18 IGBT grid bus structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010557347.1A CN111916496B (en) 2020-06-18 2020-06-18 IGBT grid bus structure

Publications (2)

Publication Number Publication Date
CN111916496A true CN111916496A (en) 2020-11-10
CN111916496B CN111916496B (en) 2022-02-11

Family

ID=73237731

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010557347.1A Active CN111916496B (en) 2020-06-18 2020-06-18 IGBT grid bus structure

Country Status (1)

Country Link
CN (1) CN111916496B (en)

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0429885A2 (en) * 1989-12-01 1991-06-05 Texas Instruments Incorporated Method of in-situ doping of deposited silicon
KR930009023A (en) * 1991-10-21 1993-05-22 정몽헌 Contact filling method by two-step deposition of selective tungsten thin film
TW468200B (en) * 2000-02-25 2001-12-11 United Microelectronics Corp Manufacturing method of semiconductor device with high isolation technique
US20070063307A1 (en) * 2003-12-18 2007-03-22 Kazutoshi Nakamura Semiconductor device including power MOS field-effect transistor and driver circuit driving thereof
CN101312192A (en) * 2007-05-25 2008-11-26 三菱电机株式会社 Semiconductor device
CN101419981A (en) * 2008-12-04 2009-04-29 电子科技大学 Trench gate SOI LIGBT device
KR20110078946A (en) * 2009-12-31 2011-07-07 주식회사 동부하이텍 Semiconductor device and method for manufacturing the same
CN103700648A (en) * 2013-12-18 2014-04-02 无锡中微晶园电子有限公司 Metal interconnecting structure for high-temperature circuit and preparing method of metal interconnecting structure
CN104282622A (en) * 2013-07-12 2015-01-14 北大方正集团有限公司 Manufacturing method of contact holes of integrated circuit
CN106684128A (en) * 2017-01-04 2017-05-17 上海华虹宏力半导体制造有限公司 Planar gate groove-type super junction device and manufacturing method thereof
WO2017219755A1 (en) * 2016-06-22 2017-12-28 无锡华润上华半导体有限公司 Trench gate structure and manufacturing method therefor

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0429885A2 (en) * 1989-12-01 1991-06-05 Texas Instruments Incorporated Method of in-situ doping of deposited silicon
KR930009023A (en) * 1991-10-21 1993-05-22 정몽헌 Contact filling method by two-step deposition of selective tungsten thin film
TW468200B (en) * 2000-02-25 2001-12-11 United Microelectronics Corp Manufacturing method of semiconductor device with high isolation technique
US20070063307A1 (en) * 2003-12-18 2007-03-22 Kazutoshi Nakamura Semiconductor device including power MOS field-effect transistor and driver circuit driving thereof
CN101312192A (en) * 2007-05-25 2008-11-26 三菱电机株式会社 Semiconductor device
CN102569372A (en) * 2007-05-25 2012-07-11 三菱电机株式会社 Semiconductor device
CN101419981A (en) * 2008-12-04 2009-04-29 电子科技大学 Trench gate SOI LIGBT device
KR20110078946A (en) * 2009-12-31 2011-07-07 주식회사 동부하이텍 Semiconductor device and method for manufacturing the same
CN104282622A (en) * 2013-07-12 2015-01-14 北大方正集团有限公司 Manufacturing method of contact holes of integrated circuit
CN103700648A (en) * 2013-12-18 2014-04-02 无锡中微晶园电子有限公司 Metal interconnecting structure for high-temperature circuit and preparing method of metal interconnecting structure
WO2017219755A1 (en) * 2016-06-22 2017-12-28 无锡华润上华半导体有限公司 Trench gate structure and manufacturing method therefor
CN106684128A (en) * 2017-01-04 2017-05-17 上海华虹宏力半导体制造有限公司 Planar gate groove-type super junction device and manufacturing method thereof

Also Published As

Publication number Publication date
CN111916496B (en) 2022-02-11

Similar Documents

Publication Publication Date Title
US20050208722A1 (en) Trench-gate semiconductor device and method of manufacturing
CN203242629U (en) Electrode contact structure
CN108682624B (en) Manufacturing method of IGBT chip with composite gate
CN105679816A (en) Trench gate charge storage type IGBT and manufacturing method thereof
KR20120068701A (en) Semiconductor device
CN113471279B (en) Power transistor structure for reducing on-resistance
JP2001358338A (en) Trench gate type semiconductor device
CN105161491A (en) Integrated gate driver transistor (IGDT) power device and manufacturing method thereof
CN114141621A (en) Carrier storage groove gate bipolar transistor with split gate and preparation method thereof
CN112164652B (en) Diagonal through-current square cell IGBT and manufacturing method thereof
CN111916496B (en) IGBT grid bus structure
CN219286406U (en) High electrostatic protection split gate MOSFET device
CN108039366A (en) A kind of insulated gate bipolar transistor transoid MOS transition plot structures and preparation method thereof
CN114582965B (en) Low-switching-loss power device structure and manufacturing method thereof
CN208422922U (en) A kind of groove grid super node semiconductor devices optimizing switching speed
CN108447904B (en) Manufacturing method of transverse IGBT
CN107256865B (en) Low-loss semiconductor power device
CN111916495B (en) Groove type IGBT chip active area edge structure
CN111261702A (en) Trench type power device and forming method thereof
CN211455694U (en) Planar VDMOS device
KR20040111710A (en) Trench-gate semiconductor device and method of manufacturing
CN113571412A (en) Power device structure and manufacturing method thereof
CN111146280A (en) Grid structure for improving voltage resistance and switching time performance of power device
CN219513109U (en) Medium-high voltage shielding grid power MOSFET layout
CN214012944U (en) IGBT trench gate arrangement structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant