CN111916491B - High electron mobility transistor with annular gate structure - Google Patents

High electron mobility transistor with annular gate structure Download PDF

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CN111916491B
CN111916491B CN202010640079.XA CN202010640079A CN111916491B CN 111916491 B CN111916491 B CN 111916491B CN 202010640079 A CN202010640079 A CN 202010640079A CN 111916491 B CN111916491 B CN 111916491B
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electrode
grid
drain
source
gate
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CN111916491A (en
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吴少兵
张亦斌
陈韬
刘世郑
陈堂胜
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CETC 55 Research Institute
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
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    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
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    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
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    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

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Abstract

The invention discloses a high electron mobility transistor with an annular grid structure, which comprises a source electrode, a drain electrode and a grid electrode, wherein the grid electrode is of the annular structure, and the high electron mobility transistor comprises two basic structures: the first basic structure is that the source electrode is a circular structure, the drain electrode is an annular structure, the source electrode is positioned at the inner ring of the grid electrode, the drain electrode is positioned at the outer ring of the grid electrode, and gaps are respectively formed between the source electrode and the drain electrode and the grid electrode; the second basic structure is that the drain electrode is in a circular structure, the source electrode is in an annular structure, the drain electrode is positioned at the inner ring of the grid electrode, the source electrode is positioned at the outer ring of the drain electrode, and gaps are respectively reserved between the source electrode and the drain electrode and the grid electrode. The grid electrode is changed into an annular structure from a linear type, so that the structure of the grid electrode is stable, and the stability and low parasitic capacitance of the device are guaranteed.

Description

High electron mobility transistor with annular gate structure
Technical Field
The invention belongs to the field of microwave and millimeter wave devices, and particularly relates to a high electron mobility transistor.
Background
The third generation semiconductor has wide application prospect in the high frequency field of the microwave millimeter wave chip. Millimeter wave and terahertz High Electron Mobility Transistor (HEMT) devices are core components of systems such as millimeter wave communication, millimeter wave radar, terahertz imaging, terahertz detection and the like. One of the major process bottlenecks that has been limiting the development of high frequency devices is the parasitic and structural stability problems associated with small-sized gates. At present, the gate process of the millimeter wave HEMT device is generally a T-shaped gate or a Y-shaped gate based on electron beam direct writing, and the structure is generally that one side is a source electrode, the other side is a drain electrode, the middle is a grid electrode, and the grid electrode is a line parallel to the source electrode and the drain electrode. The gate process for preparing the T-shaped gate or the Y-shaped gate is generally a bare gate process. The bare gate process refers to that no medium grows before gate metal is evaporated, an adhesive type is obtained on an epitaxial material directly through electron beam direct writing or deep ultraviolet lithography, after the gate metal is evaporated, the adhesive type is converted into a gate type, and a metal gate is obtained through stripping. For high-frequency devices, the structural stability of the gate is difficult to realize by adopting a bare gate process for the gate with small size, and the parasitic capacitance of the device is increased by excessive medium assistance or passivation, which is not favorable for the high-frequency characteristics of the device. Because the grid size is less, the straight line type grid structure of upper portion wide narrow down, bottom adhesive force is limited, and both sides are very easily uneven simultaneously, so the easy grid risk that falls appears. In addition, another dielectric auxiliary gate process is adopted for devices with larger line width. The dielectric auxiliary gate process means that before the gate pin graph is photoetched, a dielectric grows at the bottom of the epitaxial material, the gate pin is etched by means of etching, and therefore the stability of the gate pin graph can be enhanced by dielectric support when the subsequent gate metal is evaporated. For the dielectric auxiliary gate type, the defects are as follows: the thicker dielectric brings larger parasitic capacitance, and simultaneously, dielectric etching has the problems of line width loss, alignment and the like, so that the forming preparation of the dielectric auxiliary gate cannot be finished. For a millimeter wave HEMT device, the most critical process is the stability of a grid structure when the grid size is reduced, and the straight-line grid is T-shaped, so that the risk of grid inversion exists in the structure.
In summary, for the HEMT device with the small-sized gate, when the gate size is reduced, the linear T-shaped gate or Y-shaped gate structure has instability of physical structure, and gate inversion is easy. Therefore, for a high-frequency device, it is necessary to optimize the current device structure, and a device structure with small-sized gate stability and low parasitic capacitance not only helps to improve the performance of the high-frequency device, but also helps to improve the yield and reliability of the small-sized gate.
Disclosure of Invention
In order to solve the technical problems mentioned in the background art, the present invention provides a high electron mobility transistor with a ring-shaped gate structure.
In order to achieve the technical purpose, the technical scheme of the invention is as follows:
a high electron mobility transistor of a ring-shaped gate structure comprises a source electrode, a drain electrode and a gate electrode, wherein the gate electrode is of a ring-shaped structure, and the high electron mobility transistor comprises two basic structures: the first basic structure is that the source electrode is a circular structure, the drain electrode is an annular structure, the source electrode is positioned at the inner ring of the grid electrode, the drain electrode is positioned at the outer ring of the grid electrode, and gaps are respectively reserved between the source electrode and the drain electrode and the grid electrode; the second basic structure is that the drain electrode is of a circular structure, the source electrode is of an annular structure, the drain electrode is located on the inner ring of the grid electrode, the source electrode is located on the outer ring of the drain electrode, and gaps are respectively reserved between the source electrode and the drain electrode and the grid electrode.
Further, the grid electrode is led out to a grid electrode voltage pole block through an air bridge structure.
Further, for the first basic structure, the source electrode is grounded through an etching back hole, and the drain electrode is led out to a drain electrode voltage electrode block through an air bridge structure.
Further, for the first basic structure, a source-gate-drain-gate-source multilayer nested structure is formed from inside to outside by arranging a plurality of gates and ensuring that the inner circle and the outer circle of each gate are surrounded by the gate and the drain.
Further, all the grids are connected together through an air bridge structure and led out to a grid electrode pressing block.
Further, all the sources are connected together through an air bridge structure and grounded through a source back hole in the center; all the drains are connected together by an air bridge structure and led out to a drain voltage pole block.
Further, for the second basic structure, the drain-source electrode is grounded through an etching back hole, and the source electrode is led out to the source electrode voltage electrode block through the air bridge structure.
Further, for the second basic structure, a plurality of gates are arranged and the inner circle and the outer circle of each gate are ensured to be surrounded by the gate and the drain, so that a drain-gate-source-gate-drain multi-layer nested structure is formed from inside to outside.
Further, all the grids are connected together through an air bridge structure and led out to a grid electrode pressing block.
Further, all the drains are connected together by an air bridge structure and grounded through a drain back hole in the center; all the sources are connected together through an air bridge structure and led out to a source voltage pole block.
Adopt the beneficial effect that above-mentioned technical scheme brought:
(1) compared with the traditional linear grid structure, the annular grid structure designed by the invention can enable the fine grids to be connected end to end and mutually supported, so that the stability and low parasitic capacitance of the fine grid structure can be effectively enhanced;
(2) compared with the traditional linear grid structure, the invention can realize the nested design of a plurality of devices through one back hole, effectively increase the grid perimeter of the devices, namely increase the equivalent grid width of the devices, thereby obtaining higher output power.
Drawings
FIG. 1 is a schematic diagram of an embodiment of a method for fabricating a ring-shaped source and drain on an HEMT epitaxial layer;
FIG. 2 is a schematic diagram of an embodiment in which an active region is implemented by an isolation process;
FIG. 3 is a schematic diagram of an annular grid structure and an extraction electrode pressing block thereof in the embodiment;
FIG. 4 is a schematic diagram of a drain opening and its extraction electrode block in an embodiment;
FIG. 5 is a schematic diagram of a source back hole structure and a complete ring gate device in an embodiment;
fig. 6 is a schematic diagram of a HEMT device with a two-time nested ring-shaped gate structure.
Detailed Description
The technical scheme of the invention is explained in detail in the following with the accompanying drawings.
The AlGaN/GaN HEMT structure material is taken as an example, and the first basic structure is taken as an example. As shown in fig. 1, a source 101 and a drain 102 are first prepared on an AlGaN/GaN HEMT structure material, the source and drain metals of which can be TiAuNiAu, by electron beam evaporation and lift-off, and ohmic contact is formed through high temperature alloy. The source 101 is circular and the drain 102 is a closed ring structure. The GaN HEMT epitaxial structure itself includes a substrate SiC, a buffer layer, a channel layer GaN, a barrier layer AlGaN, and the like, and the structure is mature and is not described herein. And after the source and drain metal is prepared, the SiN medium is grown for passivation protection, so that the source and drain metal is prevented from being corroded or oxidized.
As shown in fig. 2, to isolate GaN transistors from each other and from passive structures, an active region 201 is defined by a photolithography isolation region, and the structure is a circular structure. And forming a high-resistance state region in the region except the circular pattern by a plasma injection process, thereby achieving the effect of isolating the transistor from an external element.
As shown in fig. 3, a gate trench to be prepared is etched by a gate foot and etching process, and then an annular gate structure 301 is prepared between the drain and the source of the active region by a gate cap and gate metal evaporation and stripping process to form a schottky contact. Before photoetching a gate cap, photoresist can be used as a sacrificial layer to prepare a bridge structure 302, and gate metal is evaporated, so that the gate 301 can be led out to a gate handle substructure 303. The gate metal can be realized by adopting the gate metal NiAu of a common GaN HEMT device, and the total thickness of the metal can be controlled to be 500 nm. And after the gate is prepared, SiN medium is grown by Plasma Enhanced Chemical Vapor Deposition (PECVD) for passivation protection.
Further, as shown in fig. 4, to thicken the drain metal, the region of the drain 102 is metalized and thickened, as shown at 405 in fig. 4. The metallization can be prepared separately or simultaneously with the metal wiring process. In addition, the gate handle 303 is etched and opened to form a gate opening 401; an etch opening 402 is performed to the thickened drain region 405. The gate electrode compact 403 and the drain electrode compact 404 are formed by an electroplating or electron beam evaporation metal process.
Further, as shown in fig. 5, in order to ground the source, the wafer is thinned, for example, to 80 um. And forming a back hole by photoetching the back hole and a back hole etching process, and realizing interconnection of the back Au and the front source electrode structure by adopting an Au electroplating process. That is, the connection of the front source 101 to the back metal is achieved through the back hole 501. Therefore, the GaN high electron mobility transistor with the annular gate structure realizes the preparation of the basic structures of the source, the drain and the gate. In this embodiment, a PECVD is used to grow SiN dielectric, photolithography is used to etch gate pins, gate caps and various openings, electron beam evaporation and lift-off techniques, metal plating, wafer thinning, back hole etching, back metal preparation and other processes are generally mature, so detailed descriptions are omitted here.
Further, in order to increase the total perimeter of the gate, thereby increasing the effective gate width, and increasing the output power of the device, a nestable annular gate structure device needs to be implemented. As shown in fig. 6, the present invention proposes a plurality of annular grid nesting structures. Where 101 is the source of the first inner-wrap transistor, 502 is the drain of the nested transistor, and 503 is the source of the second nested transistor. The source 503 of the second nested transistor is connected to the inner ring of sources 101 through an air bridge structure 507. The air bridge structure 507 needs to cross over the drain 502 without contacting it. 301 is the gate of a first nested transistor, 504 is the gate of a second nested transistor, and in order to connect the two gates, photoresist is used as a separation between the piers 505 and 506, 505 and 506 when preparing the ring-shaped gate structure, so that the gate 301 of the first nested transistor can be connected with the gate 504 of the second nested transistor and a gate handle is formed outside 503. An etching opening 401 is made on the gate handle, and a gate electrode compact 403 is prepared by metallization processes such as electroplating. The drain 502 is extracted similarly to fig. 4, and is etched to form the opening 402, and then the drain electrode compact 404 is prepared by a metallization process such as electroplating. Similarly, a source back hole 501 is made to allow back metal to interconnect the first transistor source 101 and the second transistor source 503.
The device structure with the ring-shaped gate is adopted in the above figures, and the device structure comprises a circular source electrode, a circular ring-shaped drain electrode and a ring-shaped gate electrode which is connected end to end, which is the key point of the invention. The epitaxial material system structure can be adjusted according to actual use requirements, such as a GaN HEMT structure, a GaAsP HEMT structure or an InP HEMT structure, or a HEMT structure made of graphene and other materials. In addition, the nesting number of the nestable annular grids can be adjusted according to the application characteristics of the actual device. In addition, the source described in the above embodiments may be replaced with a drain according to device design characteristics, and the drain may be replaced with a source. The dielectric thickness, the material selection of the gate metal system, the material and thickness of the passivation layer, and the like can be modified according to actual conditions, which is not described herein again.
The embodiments are only for illustrating the technical idea of the present invention, and the technical idea of the present invention is not limited thereto, and any modifications made on the basis of the technical scheme according to the technical idea of the present invention fall within the scope of the present invention.

Claims (5)

1. A high electron mobility transistor of a ring-shaped gate structure comprises a source electrode, a drain electrode and a gate electrode, and is characterized in that: the gate electrode is of a ring structure, and the high electron mobility transistor comprises two basic structures: the first basic structure is that the source electrode is a circular structure, the drain electrode is an annular structure, the source electrode is positioned at the inner ring of the grid electrode, the drain electrode is positioned at the outer ring of the grid electrode, and gaps are respectively reserved between the source electrode and the drain electrode and the grid electrode; the second basic structure is that the drain electrode is of a circular structure, the source electrode is of an annular structure, the drain electrode is positioned at the inner ring of the grid electrode, the source electrode is positioned at the outer ring of the drain electrode, and gaps are respectively reserved between the source electrode and the drain electrode and the grid electrode;
for the first basic structure, the source electrode is grounded through an etching back hole, and the drain electrode is led out to a drain electrode voltage electrode block through an air bridge structure;
aiming at the first basic structure, a plurality of grids are arranged, and the inner ring and the outer ring of each grid are ensured to be surrounded by the grid and a drain, so that a source electrode-grid electrode-drain electrode-grid electrode-source electrode multilayer nested structure is formed from inside to outside;
for the second basic structure, the drain electrode is grounded through an etching back hole, and the source electrode is led out to a source electrode voltage pole block through an air bridge structure;
aiming at the second basic structure, a plurality of grids are arranged, and the inner circle and the outer circle of each grid are ensured to be surrounded by the grid and the drain, so that a drain-grid-source-grid-drain multi-layer nested structure is formed from inside to outside.
2. The ring-shaped gate structure hemt of claim 1, wherein: the grid is led out to a grid voltage pole block through an air bridge structure.
3. The ring-shaped gate structured HEMT of claim 1, wherein: all the grid electrodes are connected together through an air bridge structure and led out to a grid electrode pressing block.
4. The ring-shaped gate structured HEMT of claim 1, wherein: all the source electrodes are connected together through an air bridge structure and grounded through a source electrode back hole in the center; all the drains are connected together by an air bridge structure and led out to a drain voltage pole block.
5. The ring-shaped gate structure hemt of claim 1, wherein: all the drain electrodes are connected together through an air bridge structure and grounded through a drain electrode back hole in the center; all the sources are connected together through an air bridge structure and led out to a source voltage pole block.
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CN112420826B (en) * 2020-11-20 2022-09-20 成都挚信电子技术有限责任公司 Vertical pHEMT transistor structure and switch chip
CN112838120B (en) * 2021-01-21 2023-04-11 西安电子科技大学 Ring-gate enhanced AlGaN/GaN power HEMT device and preparation method thereof
CN113161239A (en) * 2021-04-15 2021-07-23 北京工业大学 Enhanced GaN HEMT annular gate lower etching device and preparation method thereof

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CN105810728A (en) * 2016-05-06 2016-07-27 西安电子科技大学 Enhanced fin-type insulated gate high-electronic mobility transistor
CN106684151A (en) * 2016-12-08 2017-05-17 中国电子科技集团公司第五十五研究所 GaN side wall insulated gate fin-type high-electron mobility transistor and manufacturing method thereof
CN107623030A (en) * 2017-08-02 2018-01-23 北京大学深圳研究生院 The manufacture method and HEMT of HEMT
CN109285880A (en) * 2017-07-19 2019-01-29 吴绍飞 Enhanced fin insulation gate transistor with high electron mobility

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105810728A (en) * 2016-05-06 2016-07-27 西安电子科技大学 Enhanced fin-type insulated gate high-electronic mobility transistor
CN106684151A (en) * 2016-12-08 2017-05-17 中国电子科技集团公司第五十五研究所 GaN side wall insulated gate fin-type high-electron mobility transistor and manufacturing method thereof
CN109285880A (en) * 2017-07-19 2019-01-29 吴绍飞 Enhanced fin insulation gate transistor with high electron mobility
CN107623030A (en) * 2017-08-02 2018-01-23 北京大学深圳研究生院 The manufacture method and HEMT of HEMT

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