CN116705798A - Integrated CMOS device structure and manufacturing method - Google Patents
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Abstract
The invention relates to an integrated CMOS device structure and a manufacturing method thereof, wherein the structure comprises: the first device, the second device, the electrical isolation layer, the first connection metal and the second connection metal; the electric isolation layer covers the surfaces of the source electrode, the drain electrode and the grid electrode of the first device; the second device is flip-chip bonded on the electrical isolation layer; the first connecting metal penetrates through the electrical isolation layer to connect the grid electrode of the first device and the grid electrode of the second device; the second connecting metal penetrates through the electrical isolation layer to connect the drain electrode of the first device with the drain electrode of the second device; the source electrode of the first device is led out from the substrate side of the first device through a metal electrode; the source electrode, the drain electrode and the grid electrode of the second device are led out from the substrate side of the second device through metal electrodes; the source electrode of the second device is used for being connected with a power supply end, the grid electrode is used for being used as an input end, and the drain electrode is used for being used as an output end. The invention realizes that the single substrate has high electron and hole movement speeds at the same time, and simultaneously saves the chip area.
Description
Technical Field
The invention belongs to the technical field of radio frequency application, and particularly relates to an integrated CMOS device structure and a manufacturing method thereof.
Background
The second generation and third generation semiconductors such as GaN, gaAs, inP and the like of the III-V compound semiconductor have the advantages of high electron mobility, wide forbidden bandwidth, large continuous modulation range, good uniformity of large-size crystals, good lattice matching performance, low energy consumption, simpler preparation process and the like. However, in the latter molar age, the semiconductor industry is faced with enormous technical and engineering challenges and the information society age is increasingly demanding data computing and storage capabilities. Therefore, the semiconductor field is also focusing more and more on new materials and devices while the silicon-based technology is hard to develop, thereby expanding moore's law. Among the structures of many new materials, carbon Nanotubes (CNTs) are also receiving a great deal of attention due to their unique quasi-one-dimensional structure and excellent electrical characteristics.
The existing single semiconductor material is difficult to realize high electron and hole movement speeds at the same time, so that the development of semiconductor logic units and digital chips to higher speeds is restricted. Because the traditional silicon-based III-V compound semiconductor device such as GaN HEMT is mostly used for manufacturing the N-channel nmos device of the P-type substrate, the mobility of the device is high, and therefore the frequency characteristic is higher, and the device can be applied to the high-frequency high-power field. And the carbon-based material has more advantages in realizing the P-channel pmos device with the N-type substrate. Therefore, the fusion and heterogeneous integration technology of the III-V semiconductor and the carbon-based material can simultaneously realize an N-channel device and a P-channel device with higher switching speed, and is an excellent choice for realizing a high-speed anti-irradiation digital circuit.
The existing methods for implementing the carbon nanotube CMOS integrated circuit mainly comprise the following steps. In 2009 Peng Lian spear research group, a non-doping method is realized on the same Si substrate, a P-type transistor is realized by Pd contact, an N-type transistor is realized by Sc contact, and performances of the P-type and the N-type are symmetrically matched, so that a CMOS integrated circuit is transversely realized on the substrate. Another method for realizing the carbon nano tube CMOS circuit is to realize a P-type transistor by using Pt contact and Ti contact through metal contacts with different work functionsAn N-type transistor; and electrically doping the channel with SiO x Realizing P-type doping by using HfO x And N-type doping is realized.
The hole mobility of the GaN material is higher than that of the carbon nanotube, so although the GaN material can also be used to fabricate the pmos transistor, the advantage of the GaN material cannot be fully exerted on the pmos transistor because the hole mobility of the pmos transistor is relatively low. Thus, if it is desired to fabricate pmos transistors, other materials, such as silicon or carbon nanotubes, are typically used. However, the existing CMOS devices cannot have both N-channel and P-channel devices with high switching speed, but the chip area is larger and the performance is lower by the conventional integration method.
In summary, it is difficult for existing single semiconductor materials to achieve high electron and hole movement speeds simultaneously in the same device, thereby reducing the saturated drain current level of the device, as well as affecting the switching speed of the device.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides an integrated CMOS device structure and a method for manufacturing the same. The technical problems to be solved by the invention are realized by the following technical scheme:
the embodiment of the invention provides an integrated CMOS device structure, which comprises: a first device, a second device, an electrical isolation layer, a first connection metal, and a second connection metal, wherein,
the first device comprises a III-V compound high electron mobility transistor and the second device comprises a carbon nanotube device;
the electrical isolation layer covers the surfaces of the source electrode, the drain electrode and the grid electrode of the first device;
the second device is flip-chip bonded on the electrical isolation layer;
the first connection metal penetrates through the electrical isolation layer to connect the grid electrode of the first device and the grid electrode of the second device;
the second connection metal penetrates through the electrical isolation layer to connect the drain electrode of the first device and the drain electrode of the second device;
The source electrode of the first device is led out from the substrate side of the first device through a metal electrode; the source electrode of the first device is used for being connected with a grounding end;
the source electrode, the drain electrode and the grid electrode of the second device are led out from the substrate side of the second device through metal electrodes; the source electrode of the second device is used for being connected with a power supply end, the grid electrode is used for being used as an input end, and the drain electrode is used for being used as an output end.
In one embodiment of the present invention, the high electron mobility transistor includes a first substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, a first source electrode, a first drain electrode, a first gate electrode, and a passivation layer, wherein,
the first substrate, the nucleation layer and the buffer layer are sequentially laminated; the first source electrode is positioned at one end of the surface of the buffer layer; the first drain electrode is positioned at the other end of the surface of the buffer layer; the channel layer and the barrier layer are stacked on the buffer layer between the first source electrode and the first drain electrode; the passivation layer covers the barrier layer, the first source electrode and the surface of the first drain electrode; the first gate is located between the first source and the first drain, and is located on a surface of the barrier layer and a surface of the passivation layer.
In one embodiment of the present invention, the carbon nanotube device includes a second substrate, a substrate base plate, a carbon nanotube array, a second source electrode, a second drain electrode, a dielectric layer, and a second gate electrode, wherein,
the second substrate and the substrate are sequentially laminated, and the carbon nanotube arrays are distributed on the substrate in an array manner; the second source electrode is positioned at one end of the surface of the carbon nano tube array; the second drain electrode is positioned at the other end of the surface of the carbon nano tube array; the dielectric layer covers a part of the surface of the second source electrode, a part of the surface of the second drain electrode and the surface of the carbon nano tube array between the second source electrode and the second drain electrode; the second grid electrode is positioned on the surface of the dielectric layer between the second source electrode and the second drain electrode.
In one embodiment of the invention, the material of the electrical isolation layer comprises SiO 2 Or Al 2 O 3 The thickness is 2-5 μm.
Another embodiment of the present invention provides a method for fabricating an integrated CMOS device structure, comprising the steps of:
preparing a first device, wherein the first device comprises a III-V compound high electron mobility transistor;
Preparing an electrical isolation layer on the first device, so that the electrical isolation layer covers the surfaces of a source electrode, a drain electrode and a grid electrode of the first device;
etching the electrical isolation layer at the gate position of the first device to form a first through hole, and etching the electrical isolation layer at the drain position of the first device to form a second through hole;
preparing a second device, wherein the second device comprises a carbon nanotube device;
preparing a first connection metal in the first through hole and preparing a second connection metal in the second through hole;
inversely bonding the second device on the electrical isolation layer, so that the first connection metal is connected with the grid electrode of the first device and the grid electrode of the second device, and the second connection metal is connected with the drain electrode of the first device and the drain electrode of the second device;
etching a third through hole from the substrate side of the first device to the source electrode of the first device, etching a fourth through hole from the substrate side of the second device to the source electrode of the second device, etching a fifth through hole to the drain electrode of the second device, and etching a sixth through hole to the gate electrode of the second device;
preparing a metal electrode in the third through hole to lead out a source electrode of the first device, wherein the source electrode of the first device is used for connecting a grounding end; and preparing metal electrodes in the fourth through hole, the fifth through hole and the sixth through hole to lead out a source electrode, a drain electrode and a grid electrode of the second device, wherein the source electrode of the second device is used for being connected with a power supply end, the grid electrode is used as an input end, and the drain electrode is used as an output end.
In one embodiment of the invention, preparing the first device comprises the steps of:
providing a first substrate, wherein the first substrate comprises a first substrate, a nucleation layer, a buffer layer, a channel layer and a barrier layer which are sequentially laminated;
preparing a first source electrode at one end of the buffer layer and preparing a first drain electrode at the other end of the buffer layer, so that the channel layer and the barrier layer are positioned between the first source electrode and the first drain electrode;
making an electrical isolation of the active region;
preparing passivation layers on the surfaces of the barrier layer, the first source electrode and the first drain electrode;
a first gate electrode is prepared between the first source electrode and the first drain electrode such that the first gate electrode is located on a surface of the barrier layer and a surface of the passivation layer.
In one embodiment of the present invention, preparing an electrical isolation layer on the first device such that the electrical isolation layer covers surfaces of a source, a drain, and a gate of the first device, includes:
depositing SiO on the first device by using a plasma enhanced chemical vapor deposition process 2 A medium having a thickness of 2 to 5 μm such that SiO 2 And dielectric covers the surfaces of the source electrode, the drain electrode and the grid electrode of the first device to form the electrical isolation layer.
In one embodiment of the present invention, preparing an electrical isolation layer on the first device such that the electrical isolation layer covers surfaces of a source, a drain, and a gate of the first device, includes:
depositing Al on the first device by using a plasma atomic layer deposition process 2 O 3 A medium having a thickness of 2 to 5 μm such that Al 2 O 3 And dielectric covers the surfaces of the source electrode, the drain electrode and the grid electrode of the first device to form the electrical isolation layer.
In one embodiment of the invention, preparing the second device comprises the steps of:
providing a second substrate, wherein the second substrate comprises a second substrate and a substrate base plate which are sequentially laminated;
providing carbon nanotubes free of impurities and amorphous carbon;
adopting an electrophoresis method to enable the carbon nano tube to form a carbon nano tube array on the substrate base plate;
preparing a second source electrode at one end of the carbon nanotube array, and preparing a second drain electrode at the other end of the carbon nanotube array;
preparing a dielectric layer on a part of the surface of the second source electrode, a part of the surface of the second drain electrode and the surface of the carbon nanotube array between the second source electrode and the second drain electrode;
and preparing a second grid electrode on the surface of the dielectric layer between the second source electrode and the second drain electrode.
In one embodiment of the present invention, an electrophoresis method is adopted to enable the carbon nanotubes to form a carbon nanotube array on the substrate base plate, and the method comprises the following steps:
manufacturing an array pattern on the substrate;
preparing an electrode on a substrate having an arrayed pattern;
immersing the device in a function generator with a carbon nanotube suspension, and applying voltage to prepare a carbon nanotube array;
and wet etching the electrophoresis electrode to enable the carbon nano tube array to be attached to the substrate.
Compared with the prior art, the invention has the beneficial effects that:
the integrated CMOS device structure integrates the high electron mobility transistor and the carbon nano tube device in the vertical direction, an electrical isolation layer is arranged between the high electron mobility transistor and the carbon nano tube device, the high electron mobility transistor is connected with the grid electrode and the grid electrode of the carbon nano tube device in a metal connection mode, the drain electrode is connected with the drain electrode, the nmos transistor is realized by the high electron mobility transistor, the pmos transistor is realized by the carbon nano tube device, the heterogeneous integrated structure realizes the high electron and hole movement speed on a single substrate, an N channel device and a P channel device with higher switching speed are obtained, and the chip area is greatly saved by the vertical integration, so that the integrated CMOS device structure can realize a small-size high-speed anti-radiation digital logic circuit.
Drawings
Fig. 1 is a schematic diagram of an integrated CMOS device structure according to an embodiment of the present invention;
FIG. 2 is a logic diagram of a CMOS device according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a high electron mobility transistor according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a carbon nanotube device according to an embodiment of the present invention;
fig. 5 is a schematic flow chart of a method for manufacturing an integrated CMOS device structure according to an embodiment of the present invention;
fig. 6 is a schematic process diagram of a method for fabricating an integrated CMOS device structure according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
Example 1
Referring to fig. 1, fig. 1 is a schematic diagram of an integrated CMOS device structure according to an embodiment of the invention.
The integrated CMOS device structure comprises a first device 1, a second device 2, an electrical isolation layer 3, a first connection metal 4 and a second connection metal 5. Wherein the first device 1 comprises a iii-v compound high electron mobility transistor and the second device 2 comprises a carbon nanotube device. The electrical isolation layer 3 covers the surfaces of the source, drain and gate of the first device 1. The second device 2 is flip-chip bonded to the electrical isolation layer 3. The first connection metal 4 penetrates the electrical isolation layer 3 to connect the gate of the first device 1 with the gate of the second device 2. The second connection metal 5 penetrates the electrical isolation layer 3 to connect the drain of the first device 1 with the drain of the second device 2. The source electrode of the first device 1 is led out from the substrate side of the first device 1 through a metal electrode; the source of the first device 1 is connected to ground. The source, drain and gate of the second device 2 are all led out from the substrate side of the second device 2 through metal electrodes. The source of the second device 2 is connected to a power supply terminal, the gate is used as an input terminal, and the drain is used as an output terminal.
Specifically, the first device 1 is an nmos transistor having a source, a drain, and a gate, including but not limited to a III-V compound high electron mobility transistor. The second device 2 is a pmos transistor having a source, a drain and a gate, including but not limited to a carbon nanotube device. The electrical isolation layer 3 is located between the source, drain, gate and source, drain and gate of the first device 1 and the second device, thereby vertically bonding the first device 1 and the second device 2 together and achieving electrical isolation between the first device 1 and the second device 2, forming a CMOS device having both an N channel and a P channel with a high switching speed.
Referring to fig. 2, fig. 2 is a logic diagram of a CMOS device according to an embodiment of the invention. In fig. 2, the CMOS device is composed of two MOS devices, with an N-channel nmos transistor above and a P-channel pmos transistor below. The grid electrodes of the two MOS tubes are connected together to serve as an input end Ain; the drains of the two MOS transistors are connected together to serve as an output end Yout; the source electrode of the nmos transistor is connected with the power supply end VDD; the source of the pmos transistor is connected to ground GND.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a high electron mobility transistor according to an embodiment of the present invention. In fig. 3, the high electron mobility transistor includes a first substrate 101, a nucleation layer 102, a buffer layer 103, a channel layer 104, a barrier layer 105, a first source 106, a first drain 107, a first gate 108, and a passivation layer 109.
Wherein the first substrate 101, the nucleation layer 102, and the buffer layer 103 are sequentially stacked. The first source electrode 106 is located at one end of the surface of the buffer layer 103; the first drain electrode 107 is located at the other end of the surface of the buffer layer 103. The channel layer 104 and the barrier layer 105 are stacked on the buffer layer 103 between the first source electrode 106 and the first drain electrode 107. The passivation layer 109 covers the surfaces of the barrier layer 105, the first source electrode 106, and the first drain electrode 107. The first gate electrode 108 is located between the first source electrode 106 and the first drain electrode 107, and is located on the surface of the barrier layer 105 and the surface of the passivation layer 109.
Specifically, the first gate 108 is a T-shaped gate structure, and includes a gate foot and a gate cap, where the gate foot penetrates the passivation layer 109 to the surface of the barrier layer 105, and the gate cap is located on the surface of the passivation layer 109 and the surface of the gate cap.
Specifically, the material of the first substrate 101 includes one or more of Si, siC, and sapphire substrates; the material of nucleation layer 102 comprises AlN; the material of the buffer layer 103 includes GaN; the material of the channel layer 104 includes one or more of GaN, gaAs, inP; the material of the barrier layer 105 includes one or more of AlN, alGaN, inAlN; the materials of the first source electrode 106 and the first drain electrode 107 include Ti, al, N, and Au, which are laminated; the material of the first gate 108 includes Ni and Au stacked; the material of the passivation layer 109 includes SiN.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a carbon nanotube device according to an embodiment of the present invention. In fig. 4, the carbon nanotube device includes a second substrate 201, a substrate base 202, a carbon nanotube array 203, a second source 204, a second drain 205, a dielectric layer 206, and a second gate 207.
The second substrate 201 and the substrate 202 are sequentially stacked, and the carbon nanotube array 203 is distributed on the substrate 202 in an array. The second source 204 is located at one end of the surface of the carbon nanotube array 203; the second drain electrode 205 is located at the other end of the surface of the carbon nanotube array 203. The dielectric layer 206 covers a portion of the surface of the second source electrode 204, a portion of the surface of the second drain electrode 205, and the surface of the carbon nanotube array 203 between the second source electrode 204 and the second drain electrode 205. The second gate 207 is located on the surface of the dielectric layer 206 between the second source 204 and the second drain 205.
Specifically, the material of the second substrate 201 includes one or more of Si, siC, and sapphire substrates; the material of the substrate base 202 includes SiO 2 The method comprises the steps of carrying out a first treatment on the surface of the The materials of the second source electrode 204 and the second drain electrode 205 include laminated Ti, al, ni, and Au; the material of dielectric layer 206 includes H f O 2 、Al 2 O 3 One or more of the following; the material of the second gate electrode 207 includes Ni and Au stacked.
In a specific embodiment, the material of the electrical isolation layer 3 comprises SiO 2 Or Al 2 O 3 The thickness is 2-5 μm.
The integrated CMOS device structure integrates the high electron mobility transistor and the carbon nano tube device in the vertical direction, an electrical isolation layer is arranged between the high electron mobility transistor and the carbon nano tube device, the high electron mobility transistor is connected with the grid electrode and the grid electrode of the carbon nano tube device in a metal connection mode, the drain electrode is connected with the drain electrode, the nmos transistor is realized by the high electron mobility transistor, the pmos transistor is realized by the carbon nano tube device, the heterogeneous integrated structure fully plays the advantages of the nmos transistor and the pmos transistor, the high electron and hole movement speed is realized on a single substrate, the N channel device and the P channel device with higher switching speed are obtained, and the chip area is greatly saved by the vertical direction integration.
Example two
Referring to fig. 5 and fig. 6, fig. 5 is a schematic flow chart of a method for manufacturing an integrated CMOS device structure according to an embodiment of the present invention, and fig. 6 is a schematic flow chart of a method for manufacturing an integrated CMOS device structure according to an embodiment of the present invention.
The preparation method of the integrated CMOS device structure comprises the following steps:
s1, preparing a first device 1, wherein the first device 1 comprises a III-V compound high electron mobility transistor.
S2, preparing an electrical isolation layer 3 on the first device 1, so that the electrical isolation layer 3 covers the surfaces of the source electrode, the drain electrode and the gate electrode of the first device 1.
In particular, a plasma enhanced chemical vapor deposition process may be utilized to deposit SiO on the first device 1 2 A medium having a thickness of 2 to 5 μm such that SiO 2 The medium covers the surfaces of the source electrode, the drain electrode and the grid electrode of the first device 1 to form an electrical isolation layer 3; al may also be deposited on the first device 1 by means of a plasma atomic layer deposition process 2 O 3 A medium having a thickness of 2 to 5 μm such that Al 2 O 3 The dielectric covers the surfaces of the source, drain and gate of the first device 1 forming an electrical isolation layer 3.
S3, etching the electrical isolation layer 3 at the gate position of the first device 1 to form a first through hole, and etching the electrical isolation layer 3 at the drain position of the first device 1 to form a second through hole.
S4, preparing a second device 2, wherein the second device 2 comprises a carbon nano tube device.
S5, preparing a first connecting metal 4 in the first through hole, and preparing a second connecting metal 5 in the second through hole.
S6, reversely bonding the second device 2 on the electrical isolation layer 3, so that the first connection metal 4 is connected with the grid electrode of the first device 1 and the grid electrode of the second device 2, and the second connection metal 5 is connected with the drain electrode of the first device 1 and the drain electrode of the second device 2.
And S7, etching a third through hole from the substrate side of the first device 1 to the source electrode of the first device 1, and preparing a metal electrode in the third through hole to lead out the source electrode of the first device 1, wherein the source electrode of the first device 1 is used for being connected with a grounding terminal.
S8, etching a fourth through hole from the substrate side of the second device 2 to the source electrode of the second device 2, etching a fifth through hole to the drain electrode of the second device 2, etching a sixth through hole to the gate electrode of the second device 2, and preparing metal electrodes in the fourth through hole, the fifth through hole and the sixth through hole to lead out the source electrode, the drain electrode and the gate electrode of the second device 2, wherein the source electrode of the second device 2 is used for being connected with a power supply end, the gate electrode is used as an input end, and the drain electrode is used as an output end.
The CMOS device with the N channel and the P channel with high switching speed is obtained through the steps.
In one embodiment, a High Electron Mobility Transistor (HEMT) with a barrier layer of AlN is prepared and then SiO is grown on the surface of the HEMT by PECVD 2 Performing electrical isolation, etching the corresponding positions of the drain electrode and the grid electrode of the HEMT by adopting Inductively Coupled Plasma (ICP), and leading out a through hole to prepare a connecting metal; and finally, carrying out flip-chip bonding on the prepared carbon nanotube device and the HEMT, and respectively corresponding the grid drain electrode of the carbon nanotube device with the grid drain electrode of the HEMT to obtain an N channel and a P channel with high switching speed at the same timeFor example, the preparation method of the integrated CMOS device structure specifically comprises the following steps:
s1, preparing a first device 1. The method specifically comprises the following steps:
s11, providing a first substrate, wherein the first substrate includes a first substrate 101, a nucleation layer 102, a buffer layer 103, a channel layer 104, and a barrier layer 105, which are sequentially stacked.
Specifically, a first substrate including, in order from bottom to top, a Si substrate 101, an AlN nucleation layer 102, a GaN buffer layer 103, a GaN channel layer 104, and an AlN barrier layer 105 is obtained by purchasing.
S12, a first source electrode 106 is prepared at one end of the buffer layer 103, and a first drain electrode 107 is prepared at the other end, such that the channel layer 104 and the barrier layer 105 are located between the first source electrode 106 and the first drain electrode 107. The method specifically comprises the following steps:
s121, the first source 106 region and the first drain 107 region are lithographically formed on the AlN barrier layer 105.
Firstly, placing a first substrate on a hot plate at 200 ℃ for baking for 5min; then, the AlN barrier layer 105 is coated with stripping adhesive and whirl adhesive, and the sample is put on a hot plate at 200 ℃ for baking for 5min; then, photoresist coating and photoresist throwing are carried out on the stripping adhesive, and the sample is put on a hot plate at 900 ℃ for baking for 1min; and placing the sample with the glue spreading and throwing glue into a photoetching machine to expose the glued surface, placing the exposed sample into a developing solution to remove the photoresist and the stripping glue, and then performing ultrapure water flushing and nitrogen blowing on the sample to form a first source electrode 106 area and a first drain electrode 107 area.
S122, evaporation source electrode 6 and drain electrode 7 are formed on AlN barrier layer 105 in first source 106 region and first drain 107 region, and on the photoresist outside first source 106 region and first drain 107 region.
Firstly, placing a sample with a first source electrode 106 and a first drain electrode 107 photoetching patterns into a plasma photoresist remover for carrying out bottom film treatment for 5min; then placing the sample into an electron beam evaporation table, and when the vacuum degree of the reaction chamber of the electron beam evaporation table reaches 2×10 -6 After Torr, A in the first source 106 region and the first drain 107 region Evaporating ohmic metal on the lN barrier layer 105 and on the photoresist outside the first source 106 region and the first drain 107 region to form a first source 106 and a first drain 107, wherein the ohmic metal is a metal stack structure composed of four layers of metals of Ti, al, ni and Au sequentially from bottom to top; after the ohmic metal is evaporated, a stripping process is performed on the sample to remove the ohmic metal, photoresist and stripper off-glue outside the first source 106 and the first drain 107, and the sample is rinsed with ultra pure water and dried with nitrogen gas.
S123, placing a sample subjected to ohmic metal evaporation and stripping into a rapid thermal annealing furnace for annealing treatment, wherein the annealing process comprises the following steps: under nitrogen, the annealing temperature is 830 ℃ and the annealing time is 30s, so that the ohmic metal on the AlN barrier layer 105 in the first source 106 and the first drain 107 is extended down to the surface of the buffer layer 103, thereby forming ohmic contact between the metal and the heterojunction channel.
S13, manufacturing electric isolation of the active region.
Specifically, the electrical isolation of the active region of the device may be made using an ICP process, or may be made using an ion implantation process.
Taking an example of manufacturing the electric isolation of the active region of the device by utilizing the ICP process, the method specifically comprises the following steps:
S131, electrically isolated regions are lithographically formed on AlN barrier layer 105.
Firstly, placing a sample on a hot plate at 200 ℃ for baking for 5min; performing photoresist coating and spin coating on the sample, and baking the sample on a hot plate at 900 ℃ for 1min; and (3) placing the sample into a photoetching machine to expose the photoresist in the electric isolation area, placing the exposed sample into a developing solution to remove the photoresist in the electric isolation area, and performing ultrapure water flushing and nitrogen blow-drying on the sample to form the electric isolation area.
S132, electrically isolating the active region is fabricated on the AlN barrier layer 105.
Firstly, sequentially etching an AlN barrier layer 105, a GaN channel layer 104 and a GaN buffer layer 103 of an electric isolation region by utilizing an ICP process to realize mesa isolation of an active region; specifically, the etching depth may be 100nm. And then, sequentially placing the sample into an acetone solution, a stripping solution, an acetone solution and an isopropanol solution for cleaning to remove photoresist outside the electric isolation area, and finally flushing the sample with ultrapure water and drying with nitrogen to realize electric isolation of the active area.
S14, a passivation layer 109 is prepared on the surfaces of the barrier layer 105, the first source electrode 106, and the first drain electrode 107. The method specifically comprises the following steps:
And S141, carrying out surface cleaning on the sample with the electrically isolated active region.
Specifically, the cleaning process includes: placing the sample into an acetone solution for ultrasonic cleaning for 3 mm, wherein the ultrasonic intensity is 2.5; placing the sample into stripping solution with the temperature of 60 ℃ and heating for 5min in a water bath; sequentially placing the samples into an acetone solution for ultrasonic cleaning for 3min, wherein the ultrasonic intensity is 2.5; sequentially placing the samples into isopropanol solution for ultrasonic cleaning for 3min, wherein the ultrasonic intensity is 2.5; the sample was rinsed with ultrapure water and dried with nitrogen.
S142, growing a SiN passivation layer 109 with a thickness of 120nm on the AlN barrier layer 105 of the first source 106 and the first drain 107 and the active region by using a PECVD process, wherein the growth process conditions are as follows: by NH 3 And SiH 4 As a reaction gas, the substrate temperature was 250 ℃, the reaction chamber pressure was 600mtorr, and the rf power was 22W.
S15, a first gate electrode 108 is prepared between the first source electrode 106 and the first drain electrode 107 such that the first gate electrode 108 is located on the surface of the barrier layer 105 and the surface of the passivation layer 109. The method specifically comprises the following steps:
and S151, photoetching a GRSS region on the SiN passivation layer 109 to serve as a gate pin region, and etching the SiN passivation layer 109 in the GRSS region by utilizing an ICP process.
First, a GRSS region is lithographically etched on the SiN passivation layer 109. The method specifically comprises the following steps: placing the sample on a hot plate at 200 ℃ for baking; performing photoresist coating and spin coating, and placing the sample on a hot plate at 900 ℃ for baking for 1min; placing the sample into a photoetching machine to expose the photoresist in the GRSS area; and (3) placing the exposed sample into a developing solution to remove photoresist in the GRSS region, and performing ultrapure water flushing and nitrogen blow-drying on the sample to form the GRSS region.
Then, the cleaning is finishedAnd etching and removing the material of the SiN passivation layer 109 in the GRSS region by utilizing an ICP process to form a gate groove. The etching conditions of the SiN passivation layer 109 include: the reaction gas being CF 4 And O 2 The pressure of the reaction chamber is 10mTorr, the radio frequency power of the upper electrode and the lower electrode is 100W and 10W respectively, and the etching depth is 125nm. Then, the sample is sequentially put into an acetone solution, a stripping solution, an acetone solution and an isopropanol solution for cleaning.
S152, forming a first gate 108 on the passivation layer 109 in the gate cap region of the grating electrode by using an electron beam evaporation process.
First, a double photoresist lithography technique is used to form a grating cap region of the grating electrode on the passivation layer 109. The method specifically comprises the following steps: baking the sample on a hot plate at 200 ℃ for 5min; coating a first photoresist on the sample until the first photoresist completely covers the upper surface of the SiN passivation layer 109; coating a second layer of glue on the sample, so that the second layer of glue completely covers the first layer of glue; performing secondary exposure on the glued sample; and placing the exposed sample into a developing solution to remove the photoresist of the T-shaped gate region, and flushing the sample with ultrapure water and blowing the sample with nitrogen to form a gate cap region.
Then, a metal is deposited to form the first gate 108 by electron beam evaporation. The method specifically comprises the following steps: placing the sample with the photoetching pattern in the gate electrode area into a plasma photoresist remover for carrying out bottom film treatment, wherein the treatment time is 5min; placing the cleaned sample into an electron beam evaporation table, and keeping the vacuum degree of the reaction chamber of the electron beam evaporation table to 2×10 -6 After Torr, evaporating gate metal on the photoresist in the gate electrode region and outside the gate electrode region, wherein the gate metal is a metal stack structure composed of three layers of Ni, au and Ni sequentially from bottom to top, so as to obtain the first gate 108.
Through the steps, the high electron mobility transistor is obtained.
S2, preparing an electrical isolation layer 3 on the first device 1, so that the electrical isolation layer 3 covers the surfaces of the source electrode, the drain electrode and the gate electrode of the first device 1. The method specifically comprises the following steps:
s21, surface cleaning is conducted on the high electron mobility transistor. The specific cleaning method comprises the following steps: placing the sample into an acetone solution for ultrasonic cleaning for 3 mm, wherein the ultrasonic intensity is 2.5; placing the sample into stripping solution with the temperature of 60 ℃ and heating for 5min in a water bath; sequentially placing the samples into an acetone solution for ultrasonic cleaning for 3min, wherein the ultrasonic intensity is 2.5; sequentially placing the samples into isopropanol solution for ultrasonic cleaning for 3min, wherein the ultrasonic intensity is 2.5; the sample was rinsed with ultrapure water and dried with nitrogen.
S22, growing SiO with thickness of 800nm on the first source electrode 106, the first drain electrode 107, the AlN barrier layer 105 of the active region and the SiN passivation layer 109 by utilizing PECVD process 2 An isolation layer forming an electrical isolation layer 3; siO (SiO) 2 The process conditions for the growth of the isolation layer are as follows: using N 2 O and SiN 4 As a reaction gas, the substrate temperature was 300 ℃, the reaction chamber pressure was 900mTorr, and the RF power was 70W.
S3, etching the electrical isolation layer 3 at the gate position of the first device 1 to form a first through hole, and etching the electrical isolation layer 3 at the drain position of the first device 1 to form a second through hole.
Specifically, in SiO 2 And photoetching a through hole opening area on the electric isolation layer 3, and etching the electric isolation layer 3 of the interconnection opening area by utilizing an ICP process to form a first through hole and a second through hole. The method specifically comprises the following steps:
s31 at SiO 2 The first connection metal opening region and the second connection metal opening region are lithographically formed on the electrical isolation layer 3.
The photoetching method comprises the following steps: baking the sample on a hot plate at 200 ℃ for 5min; performing photoresist coating and spin coating, wherein the spin coating rotating speed is 3500 rpm, and placing the sample on a hot plate at 90 ℃ for baking for 1min; placing the sample into a photoetching machine to expose the photoresist in the area of the connecting metal opening; and placing the exposed sample into a developing solution to remove the photoresist in the interconnection opening area, and flushing the photoresist with ultrapure water and blowing the photoresist with nitrogen to form a first connection metal opening area at the gate position of the first device 1 and a second connection metal opening area at the drain position of the first device 1.
S32, using ICP etching process to make the reaction gas CF 4 And O 2 Reaction chamberRemoving SiO connecting the first connection metal open pore region and the second connection metal open pore region under the condition that the pressure is 10mTorr and the radio frequency power of the upper electrode and the lower electrode is 100W and 10W respectively 2 And an electrical isolation layer 3 forming a first via and a second via.
S4, preparing a second device 2, wherein the second device 2 comprises a carbon nano tube device. The method specifically comprises the following steps:
s41, providing a second substrate, wherein the second substrate comprises a second substrate 201 and a substrate 202 which are sequentially stacked.
Specifically, the second substrate is obtained by purchasing, and the second substrate comprises a Si second substrate 201 and SiO from bottom to top 2 A substrate 202.
S42, providing the carbon nano tube without impurities and amorphous carbon.
Specifically, the semiconductor type carbon nanotube having a purity higher than 99% is separated twice to obtain a carbon nanotube free of impurities and amorphous carbon.
The specific method comprises the following steps: the single-walled carbon nanotubes obtained by purchase were prepared according to 1:1 and poly 9- (1-octyl nonyl) -9H-carbazole PCz for catalysis; adding 25ml toluene solution into the above solution, soaking in ice water bath at 0deg.C, and placing in VCX500 cell disrupter for full contact for 30min; pre-ultracentrifugation for 30min under 20000g centrifugation at 4deg.C to obtain 90% supernatant; and (3) performing a second step of centrifugation under 20000g of centrifugation for 2 hours at a temperature of 4 ℃ and taking 90% of supernatant to obtain the carbon nanotube free of impurities and amorphous carbon.
S43, an electrophoresis method is adopted, so that the carbon nanotubes form a carbon nanotube array 203 on the substrate 202. The method specifically comprises the following steps:
s431, an arrayed pattern is formed on the substrate 202.
Specifically, lithography is used to produce a resist pattern on SiO 2 The substrate 202 is lithographically patterned.
S432, electrodes are prepared on the substrate 202 having the array pattern.
Specifically, the sample is put on a hot plate at 200 ℃ and baked for 5min; carrying out photoresist coating and spin coating on the prepared sample under a yellow light, and placing the sample on a hot plate at 900 ℃ for baking for 1min; placing the sample with the glue spreading and throwing glue into a photoetching machine to expose the glued surface, and placing the sample with the exposed glue into a developing solution to remove the photoresist; cr/Au was plated on the substrate base plate 202 having the array pattern using a magnetron sputtering process to a thickness of about 400nm to prepare an electrode.
S433, soaking the device in a function generator with carbon nanotube suspension, and applying voltage to prepare the carbon nanotube array 203.
Specifically, the device was immersed in a function generator having a carbon nanotube suspension, and electrodes were connected to the function generator, and electrophoresis was performed at 100kHz and 10V, so that the carbon nanotube suspension formed a carbon nanotube array 203 on the electrode surface.
S434, wet etching the electrode, so that the carbon nanotube array 203 is attached to the substrate base 202.
Specifically, the BOE solution is used to perform wet etching to remove the electrode metal under the carbon nanotube array 203, and at this time, the carbon nanotube array 203 is attached to the substrate 202, so as to form the carbon nanotube array 203 on the substrate 202.
And S44, preparing a second source electrode 204 at one end of the carbon nanotube array 203, and preparing a second drain electrode 205 at the other end. The method specifically comprises the following steps:
s441, the second source 204 region and the second drain 205 region are lithographically etched on the carbon nanotube array 203.
The specific photoetching method comprises the following steps: placing the epitaxial substrate on a hot plate at 200 ℃ for baking for 5min; in SiO 2 Coating and throwing the stripping adhesive on the layer 11, and baking the sample on a hot plate at 200 ℃ for 5min; photoresist is coated and whirled on the stripping adhesive, and the sample is put on a hot plate at 900 ℃ for baking for 1min; placing the sample with the glue coating and the spin coating into a photoetching machine to expose the glued surface, placing the exposed sample into a developing solution to remove the photoresist and the stripping glue, and then performing ultrapure water flushing and nitrogen blowing to form a second source 204 region and a second drain A pole 205 region.
S442 SiO in the second source 204 region and the second drain 205 region 2 The second source 204 and the second drain 205 are evaporated on the substrate 202 and on the photoresist outside the second source 204 and second drain 205 regions.
The specific method comprises the following steps: placing the sample with the second source electrode 204 area and the second drain electrode 205 area into a plasma photoresist remover for carrying out bottom film treatment for 5min; placing the sample into an electron beam evaporation table, and until the vacuum degree of the reaction chamber of the electron beam evaporation table reaches 2×10 -6 After Torr, siO in the second source 204 region and second drain 205 region 2 Evaporating ohmic metal on the substrate 202 and the photoresist outside the second source 204 region and the second drain 205 region to form a second source 204 and a second drain 205, wherein the ohmic metal is a metal stack structure composed of four layers of metals of Ti, al, ni and Au in sequence from bottom to top; after the source-drain metal is evaporated, a stripping process is performed on the sample to remove the metal, photoresist and stripping glue outside the second source 204 and the second drain 205, and then the sample is rinsed with ultrapure water and dried with nitrogen gas to form the second source 204 at one end of the carbon nanotube array 203 and the second drain 205 at the other end.
S45, preparing a dielectric layer 206 on a part of the surface of the second source 204, a part of the surface of the second drain 205, and the surface of the carbon nanotube array 203 between the second source 204 and the second drain 205.
Specifically, H with a thickness of 10nm is grown in the middle of the second source 204 and the second drain 205, and in a partial region above the second source 204 and a partial region above the second drain 205 by using a thermal Atomic Layer Deposition (ALD) process f O 2 The growth process conditions of the high-k dielectric layer 206 are: the reaction precursor source is O 3 And TEMAH, the substrate temperature is 300 ℃, the reaction chamber pressure is 0.3Torr, and the dielectric layer 206 is formed.
S46, preparing a second gate 207 on the surface of the dielectric layer 206 between the second source 204 and the second drain 205.
First, at H f O 2 A gate electrode region is lithographically formed on dielectric layer 206. The specific method comprises the following steps: placing the sample at 200deg.CBaking on a hot plate for 5min; spin coating photoresist on the sample, and exposing the coated sample; and (3) placing the exposed sample into a developing solution to remove photoresist in the gate region, and performing ultrapure water flushing and nitrogen blow-drying to form the gate electrode region.
Then, a metal is deposited to form the second gate electrode 207 by electron beam evaporation. The specific method comprises the following steps: placing the sample with the photoetching pattern in the gate electrode area into a plasma photoresist remover for carrying out bottom film treatment for 5min; placing the cleaned sample into an electron beam evaporation table, and keeping the vacuum degree of the reaction chamber of the electron beam evaporation table to 2×10 -6 After Torr, evaporating gate metal on the photoresist in the gate electrode region and outside the gate electrode region, wherein the gate metal is a metal stack structure composed of three layers of Ni, au and Ni sequentially from bottom to top, thereby forming a second gate 207.
The second device is prepared through the steps.
S5, preparing a first connecting metal 4 in the first through hole, and preparing a second connecting metal 5 in the second through hole.
S6, reversely bonding the second device 2 on the electrical isolation layer 3, so that the first connection metal 4 is connected with the grid electrode of the first device 1 and the grid electrode of the second device 2, and the second connection metal 5 is connected with the drain electrode of the first device 1 and the drain electrode of the second device 2.
S7, etching a third through hole from the substrate side of the first device 1 to the source electrode of the first device 1, etching a fourth through hole from the substrate side of the second device 2 to the source electrode of the second device 2, etching a fifth through hole to the drain electrode of the second device 2, and etching a sixth through hole to the gate electrode of the second device 2.
Specifically, the ICP process is used to etch the third via from the substrate side of the first device 1 to the source of the first device 1, the fourth via from the substrate side of the second device 2 to the source of the second device 2, the fifth via to the drain of the second device 2, and the sixth via to the gate of the second device 2.
S8, preparing a metal electrode in the third through hole to lead out a source electrode of the first device 1, wherein the source electrode of the first device 1 is used for being connected with a grounding end; metal electrodes are prepared in the fourth, fifth and sixth through holes to lead out the source, drain and gate of the second device 2, the source of the second device 2 being used for connecting to a power supply terminal, the gate being used as an input terminal, and the drain being used as an output terminal.
Specifically, ni/Au metal electrodes are prepared in the fourth through hole, the fifth through hole and the sixth through hole, and the source electrode, the drain electrode and the grid electrode of the second device 2 are led out; a Cu or Au metal electrode is prepared in the third via hole to draw out the source of the first device 1.
And finally, flushing the device with ultrapure water to obtain a sample, and drying with nitrogen to obtain the integrated CMOS device structure.
The method comprises the steps of preparing a transistor with high electron mobility, depositing an electrical isolation layer, etching the corresponding positions of a drain electrode and a grid electrode of the HEMT by inductively coupled plasma etching, and leading out a through hole to prepare a connecting metal; and finally, carrying out flip-chip bonding on the prepared carbon nanotube and the carbon nanotube, and respectively corresponding the grid drain electrode of the carbon nanotube with the grid drain electrode of the HEMT to obtain the CMOS device with the N channel and the P channel with high switching speed. In summary, the embodiment adopts the III-V semiconductor and carbon-based material fusion and heterogeneous integration technology to realize the N-channel and P-channel devices with higher switching speed, and simultaneously the vertical integration saves the chip area, so that the small-size high-speed anti-irradiation digital logic circuit can be realized.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (10)
1. An integrated CMOS device structure comprising: a first device (1), a second device (2), an electrical isolation layer (3), a first connection metal (4) and a second connection metal (5), wherein,
-the first device (1) comprises a iii-v compound high electron mobility transistor and the second device (2) comprises a carbon nanotube device;
the electrical isolation layer (3) covers the surfaces of the source electrode, the drain electrode and the gate electrode of the first device (1);
the second device (2) is flip-chip bonded on the electrical isolation layer (3);
the first connection metal (4) penetrates through the electrical isolation layer (3) to connect the gate of the first device (1) with the gate of the second device (2);
the second connection metal (5) penetrates through the electrical isolation layer (3) to connect the drain of the first device (1) with the drain of the second device (2);
The source electrode of the first device (1) is led out from the substrate side of the first device (1) through a metal electrode; the source electrode of the first device (1) is used for being connected with a grounding end;
the source electrode, the drain electrode and the grid electrode of the second device (2) are led out from the substrate side of the second device (2) through metal electrodes; the source electrode of the second device (2) is used for being connected with a power supply end, the grid electrode is used for being used as an input end, and the drain electrode is used for being used as an output end.
2. The integrated CMOS device structure of claim 1, wherein the high electron mobility transistor comprises a first substrate (101), a nucleation layer (102), a buffer layer (103), a channel layer (104), a barrier layer (105), a first source (106), a first drain (107), a first gate (108), and a passivation layer (109), wherein,
the first substrate (101), the nucleation layer (102), and the buffer layer (103) are laminated in this order; the first source electrode (106) is positioned at one end of the surface of the buffer layer (103); the first drain electrode (107) is positioned at the other end of the surface of the buffer layer (103); the channel layer (104) and the barrier layer (105) are stacked on the buffer layer (103) between the first source electrode (106) and the first drain electrode (107); -the passivation layer (109) covers the barrier layer (105), the first source (106) and the surface of the first drain (107); the first gate (108) is located between the first source (106) and the first drain (107) and is located at a surface of the barrier layer (105) and a surface of the passivation layer (109).
3. The integrated CMOS device structure of claim 1, wherein the carbon nanotube device comprises a second substrate (201), a substrate base (202), a carbon nanotube array (203), a second source (204), a second drain (205), a dielectric layer (206), and a second gate (207), wherein,
the second substrate (201) and the substrate base plate (202) are sequentially laminated, and the carbon nanotube arrays (203) are distributed on the substrate base plate (202) in an array manner; the second source electrode (204) is positioned at one end of the surface of the carbon nanotube array (203); the second drain electrode (205) is positioned at the other end of the surface of the carbon nano tube array (203); the dielectric layer (206) covers a portion of the surface of the second source electrode (204), a portion of the surface of the second drain electrode (205), and the surface of the carbon nanotube array (203) between the second source electrode (204) and the second drain electrode (205); the second gate (207) is located on the surface of the dielectric layer (206) between the second source (204) and the second drain (205).
4. An integrated CMOS device structure according to claim 1, characterized in that the material of the electrical isolation layer (3) comprises SiO 2 Or Al 2 O 3 The thickness is 2-5 μm.
5. A method of fabricating an integrated CMOS device structure comprising the steps of:
preparing a first device (1), wherein the first device (1) comprises a III-V compound high electron mobility transistor;
preparing an electrical isolation layer (3) on the first device (1) such that the electrical isolation layer (3) covers the surfaces of the source, drain and gate of the first device (1);
etching the electrical isolation layer (3) at the gate position of the first device (1) to form a first through hole, and etching the electrical isolation layer (3) at the drain position of the first device (1) to form a second through hole;
preparing a second device (2), wherein the second device (2) comprises a carbon nanotube device;
preparing a first connection metal (4) in the first through hole and preparing a second connection metal (5) in the second through hole;
-inversely bonding the second device (2) on the electrical isolation layer (3) such that the first connection metal (4) connects the gate of the first device (1) and the gate of the second device (2), the second connection metal (5) connects the drain of the first device (1) and the drain of the second device (2);
etching a third through hole from the substrate side of the first device (1) to the source electrode of the first device (1), etching a fourth through hole from the substrate side of the second device (2) to the source electrode of the second device (2), etching a fifth through hole to the drain electrode of the second device (2), and etching a sixth through hole to the gate electrode of the second device (2);
Preparing a metal electrode in the third through hole to lead out a source electrode of the first device (1), wherein the source electrode of the first device (1) is used for being connected with a grounding end; and preparing metal electrodes in the fourth through hole, the fifth through hole and the sixth through hole to lead out a source electrode, a drain electrode and a grid electrode of the second device (2), wherein the source electrode of the second device (2) is used for being connected with a power supply end, the grid electrode is used as an input end, and the drain electrode is used as an output end.
6. The method of manufacturing an integrated CMOS device structure according to claim 5, wherein the step of manufacturing the first device (1) comprises the steps of:
providing a first substrate, wherein the first substrate comprises a first substrate (101), a nucleation layer (102), a buffer layer (103), a channel layer (104) and a barrier layer (105) which are sequentially stacked;
preparing a first source electrode (106) at one end of the buffer layer (103) and preparing a first drain electrode (107) at the other end, so that the channel layer (104) and the barrier layer (105) are positioned between the first source electrode (106) and the first drain electrode (107);
making an electrical isolation of the active region;
preparing a passivation layer (109) on the surfaces of the barrier layer (105), the first source electrode (106) and the first drain electrode (107);
-preparing a first gate (108) between the first source (106) and the first drain (107) such that the first gate (108) is located at a surface of the barrier layer (105) and at a surface of the passivation layer (109).
7. The method of manufacturing an integrated CMOS device structure according to claim 5, characterized in that an electrical isolation layer (3) is manufactured on the first device (1) such that the electrical isolation layer (3) covers the surfaces of the source, drain and gate of the first device (1), comprising:
depositing SiO on said first device (1) by means of a plasma-enhanced chemical vapor deposition process 2 A medium having a thickness of 2 to 5 μm such that SiO 2 Dielectric covers the surfaces of the source electrode, the drain electrode and the grid electrode of the first device (1) to form the electrical isolation layer (3).
8. The method of manufacturing an integrated CMOS device structure according to claim 5, characterized in that an electrical isolation layer (3) is manufactured on the first device (1) such that the electrical isolation layer (3) covers the surfaces of the source, drain and gate of the first device (1), comprising:
depositing Al on the first device (1) by means of a plasma atomic layer deposition process 2 O 3 A medium having a thickness of 2 to 5 μm such that Al 2 O 3 Dielectric covers the surfaces of the source electrode, the drain electrode and the grid electrode of the first device (1) to form the electrical isolation layer (3).
9. A method of fabricating an integrated CMOS device structure according to claim 6, wherein fabricating the second device (2) comprises the steps of:
providing a second substrate, wherein the second substrate comprises a second substrate (201) and a substrate base plate (202) which are sequentially stacked;
providing carbon nanotubes free of impurities and amorphous carbon;
forming a carbon nanotube array (203) on the substrate base plate (202) by adopting an electrophoresis method;
preparing a second source electrode (204) at one end of the carbon nanotube array (203), and preparing a second drain electrode (205) at the other end;
preparing a dielectric layer (206) on a part of the surface of the second source electrode (204), a part of the surface of the second drain electrode (205) and the surface of the carbon nanotube array (203) between the second source electrode (204) and the second drain electrode (205);
-preparing a second gate (207) at the surface of the dielectric layer (206) between the second source (204) and the second drain (205).
10. The method of manufacturing an integrated CMOS device structure according to claim 9, wherein the forming the carbon nanotubes of the carbon nanotube array (203) on the substrate (202) by electrophoresis comprises the steps of:
-making an arrayed pattern on the substrate base plate (202);
preparing an electrode on a substrate board (202) having an arrayed pattern;
immersing the device in a function generator with a carbon nanotube suspension, and applying a voltage to prepare a carbon nanotube array (203);
the electrodes are wet etched such that the carbon nanotube array (203) is attached to the substrate base plate (202).
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