CN111883425A - Etching method applied to HBT device manufacturing - Google Patents
Etching method applied to HBT device manufacturing Download PDFInfo
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- CN111883425A CN111883425A CN202010686032.7A CN202010686032A CN111883425A CN 111883425 A CN111883425 A CN 111883425A CN 202010686032 A CN202010686032 A CN 202010686032A CN 111883425 A CN111883425 A CN 111883425A
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- 238000005530 etching Methods 0.000 title claims abstract description 76
- 238000000034 method Methods 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 48
- 229920005591 polysilicon Polymers 0.000 claims abstract description 30
- 238000002955 isolation Methods 0.000 claims abstract description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000001259 photo etching Methods 0.000 claims abstract description 3
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 claims description 11
- 239000012495 reaction gas Substances 0.000 claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 229910000042 hydrogen bromide Inorganic materials 0.000 claims description 5
- 239000000460 chlorine Substances 0.000 claims description 4
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 4
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052801 chlorine Inorganic materials 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims 3
- 239000000376 reactant Substances 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 150000002500 ions Chemical class 0.000 description 10
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66242—Heterojunction transistors [HBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
- H01L21/30608—Anisotropic liquid etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
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Abstract
The application discloses an etching method applied to HBT device manufacturing, which comprises the following steps: providing a substrate, wherein a base region is formed on a collector region of the substrate, a first dielectric layer is formed on the base region, a polycrystalline silicon layer is formed on the first dielectric layer and the base region, the polycrystalline silicon layer is provided with a protruding structure above the first dielectric layer, a second dielectric layer is formed on the polycrystalline silicon layer, and a third dielectric layer is formed on the second dielectric layer; covering the photoresist on the third medium layer except the target region by a photoetching process, wherein the target region is positioned in the outer edge of the isolation layer; etching the third dielectric layer and the second dielectric layer in the target area to expose the protrusion structure; carrying out isotropic etching on the polycrystalline silicon layer; removing the polysilicon layer above the first dielectric layer by anisotropic etching; and removing the photoresist. The method and the device sequentially perform isotropic etching, etching and anisotropic etching on the polycrystalline silicon layer, reduce the influence of sharp corners on the device and improve the stability of the device.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to an etching method applied to manufacturing of Heterojunction Bipolar Transistor (HBT) devices.
Background
The HBT device, especially a germanium-silicon (GeSi) HBT device, is widely used in the ultra-high frequency field due to the characteristics of high current amplification factor, high characteristic frequency and compatibility with silicon process. To obtain HBT devices for use in higher frequency ranges, the HBT devices are typically provided in a self-aligned configuration, requiring the use of sacrificial polysilicon during fabrication of the self-aligned HBT devices.
Referring to fig. 1, there is shown a schematic partial cross-sectional view of an HBT device provided in the related art after etching of sacrificial polysilicon. As shown in fig. 1, after etching the sacrificial polysilicon (not shown in fig. 1) in the window of the emitter region of the HBT device, a sharp corner (spring) 101 is formed after etching due to the influence of other thin film layers during the etching process.
Since the manufacturing method of the HBT device provided in the related art has a high probability of forming sharp corners in the window region of the emission region, the stability and manufacturing yield of the device are reduced.
Disclosure of Invention
The application provides an etching method applied to HBT device manufacturing, which can solve the problems of poor device stability and low manufacturing yield caused by the fact that a sharp corner is formed on an emitting region window of an HBT device by the etching method provided in the related technology.
In one aspect, an embodiment of the present application provides an etching method, where the method is applied to manufacture an HBT device, and the method includes:
providing a substrate, wherein a collector region is formed in the substrate, a surrounding isolation layer is formed in the collector region, a base region is formed on the collector region, a first dielectric layer is formed in a region, located in the isolation layer, of the base region, a polycrystalline silicon layer is formed on the first dielectric layer and the base region, a protruding structure is formed on the polycrystalline silicon layer above the first dielectric layer, a second dielectric layer is formed on the polycrystalline silicon layer, and a third dielectric layer is formed on the second dielectric layer;
covering photoresist on the third medium layer in other areas except the target area by a photoetching process, wherein the target area is positioned in the outer edge of the isolation layer;
etching the third dielectric layer and the second dielectric layer in the target area, and removing the third dielectric layer in the target area;
carrying out isotropic etching on the polycrystalline silicon layer;
removing the polysilicon layer above the first dielectric layer by anisotropic etching;
and removing the photoresist.
Optionally, after the isotropic etching is performed on the polysilicon layer, the thickness of the polysilicon layer above the first dielectric layer is 200 angstroms
To 400 angstroms.
Optionally, the power of the isotropic etching is 500 watts (W) to 900W.
Optionally, the reaction gas for the isotropic etching includes oxygen (O)2) And/or carbon tetrafluoride (CF)4)。
Optionally, the pressure of the isotropic etching is 0.25 Torr (Torr) to 0.75 Torr.
Optionally, the anisotropic etching includes a main etch (main etch) and an over etch (over etch), and an etch selectivity to the medium in the over etch is greater than an etch selectivity to the medium in the main etch.
Optionally, the power of the main etching is 400 w to 800 w.
Optionally, the reaction gas of the main etching includes chlorine (Cl)2) And/or hydrogen bromide (HBr).
Optionally, the main etch pressure is 3 mTorr to 9 mTorr.
Optionally, the power of the over-etching is 200 w to 600 w.
Optionally, the reaction gas for over-etching includes oxygen and/or hydrogen bromide.
Optionally, the over-etching pressure is 25 mtorr to 75 mtorr.
The technical scheme at least comprises the following advantages:
in the manufacturing process of the HBT device, polycrystalline silicon with thin thickness at the position of an emitter region window is reserved through isotropic etching, a sharp corner can be removed or the height of the sharp corner is controlled within an allowable range, and the polycrystalline silicon remained at the position of the emitter region window is etched completely through anisotropic etching, so that the deposition and etching can be smoothly completed by a side wall formed in the subsequent inner manufacturing step, the influence of the sharp corner on the device is reduced, and the stability and the manufacturing yield of the device are improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Figure 1 is a schematic partial cross-sectional view of an HBT device provided in the related art after etching of sacrificial polysilicon;
FIG. 2 is a flow chart of an etching method provided by an exemplary embodiment of the present application;
fig. 3 to 6 are schematic views of an etching process according to an exemplary embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 2, a flow chart of an etching method provided by an exemplary embodiment of the present application is shown, the method is applicable to the manufacture of HBT devices, especially germanium-silicon HBT devices, and the method includes:
Referring to fig. 3, a cross-sectional view of a photoresist overlying a third dielectric layer by a photolithography process is shown. As shown in fig. 3, a collector region 301 is formed in a substrate 310, a surrounding isolation layer 320 is formed in the collector region 301, a base region 330 is formed on the collector region 301, a first dielectric layer 341 is formed on the base region 330 in a region located in the isolation layer 320, a polysilicon layer 351 is formed on the first dielectric layer 341 and the base region 330, the polysilicon layer 351 has a protruding structure (as shown by a dotted line in fig. 3, the protruding structure can be used as sacrificial polysilicon) above the first dielectric layer 341, a second dielectric layer 342 is formed on the polysilicon layer 351, and a third dielectric layer 343 is formed on the second dielectric layer 342.
Wherein the target area is an area located within the outer edge of the isolation layer 320.
Optionally, the material of the first dielectric layer 341 and the second dielectric layer 342 includes silicon oxide (e.g., silicon dioxide SiO)2)。
Alternatively, in the embodiment of the present application, the isolation layer 320 may be a Shallow Trench Isolation (STI) or a local oxidation of silicon (LOCOS), and the isolation layer 320 may be made of silicon oxide (e.g., silicon dioxide).
Optionally, in this embodiment of the application, a buried layer 302 is further formed in the substrate 310, and the buried layer 302 is formed below the collector region 301 and is in contact with the collector region 301; optionally, a heavily doped region 303 is formed at the bottom of the collector region 301, and the doped region 303 is in contact with the buried layer 302 and is doped with the first type of ions.
Optionally, in this embodiment, a fourth dielectric layer 344 is formed on the isolation layer 320, a bottom end of the fourth dielectric layer 344 is in contact with the isolation layer 320, and a top end of the fourth dielectric layer 344 is in contact with the base region 330. The fourth dielectric layer 344 is made of silicon oxide (e.g., silicon dioxide).
Optionally, in this embodiment of the application, the base region 330 includes a germanium-silicon epitaxial layer, and the germanium-silicon epitaxial layer is doped with the second type of ions.
In the embodiment of the present application, when the first type ions are P-type ions, the second type ions are N-type ions; when the first type of ions are N-type ions, the second type of ions are P-type ions.
Referring to fig. 4, a cross-sectional view of etching the third dielectric layer and the second dielectric layer in the target area is shown. Illustratively, as shown in fig. 4, the third dielectric layer 343 and the second dielectric layer 342 in the target region may be removed by a wet etching process.
And step 204, carrying out isotropic etching on the polysilicon layer.
Referring to fig. 5, a cross-sectional view of a polysilicon layer after isotropic etching is shown. As shown in fig. 5, after isotropic etching is performed on the polysilicon layer 351, a thinner polysilicon layer 351 remains above the first dielectric layer 341, so that sharp corners can be removed or the height of the sharp corners can be controlled within an allowable range.
Optionally, in step 204, isotropic etching may be performed on the polysilicon layer 251 through a dry etching process, and after the isotropic etching is performed on the polysilicon layer 251, the thickness of the protrusion structure is 200 angstroms to 400 angstroms.
Optionally, in step 204, the power of the isotropic etching is 500 w to 900 w (for example, may be 700 w); optionally, the reaction gas for isotropic etching includes oxygen and/or carbon tetrafluoride; alternatively, the pressure of the isotropic etch may be 0.25 torr to 0.75 torr (e.g., may be 0.5 torr).
Referring to fig. 6, a cross-sectional view of a polysilicon layer after anisotropic etching is shown. As shown in fig. 6, after the polysilicon layer 351 is anisotropically etched, the first dielectric layer 241 is exposed.
Optionally, in step 205, the polysilicon layer 251 may be anisotropically etched by a dry etching process, and after the polysilicon layer 251 is anisotropically etched, the first dielectric layer 241 is exposed. The anisotropic etching may include two etching steps of main etching and over-etching, and an etching selection ratio of the medium (for example, silicon dioxide) in the over-etching is greater than that of the medium in the main etching.
Optionally, in step 205, the power of the main etching is 400 w to 800 w (for example, 600 w may be used); optionally, the reaction gas for the main etching includes chlorine and/or hydrogen bromide; optionally, the main etch pressure is 3 mtorr to 9 mtorr (e.g., may be 6 mtorr).
Optionally, in step 205, the power of the over-etching is 200 w to 600 w (for example, may be 400 w); optionally, the reaction gas of the main etching includes oxygen and/or hydrogen bromide; optionally, the main etch pressure is 25 mtorr to 75 mtorr (e.g., may be 50 mtorr).
In step 206, the photoresist is removed.
Illustratively, photoresist and post-etch reaction byproducts may be removed by an ashing process and/or a reactive agent. Optionally, after step 206, a sidewall spacer may be formed on an inner sidewall of the surrounding structure formed by the polysilicon layer 251 and the second dielectric layer 242, where the sidewall spacer may be made of silicon nitride (SiN).
To sum up, in the embodiment of the application, through dividing two steps in the manufacturing process of HBT device and etching the polycrystalline silicon layer, remain the polycrystalline silicon that emitter window department thickness is thinner through isotropic etching, can get rid of the closed angle or make the altitude control of closed angle in the allowed range, it is clean to remain polycrystalline silicon sculpture through anisotropic etching with emitter window department, so that deposit and sculpture can be accomplished smoothly to the side wall that forms in the follow-up interior manufacturing step, the influence of closed angle to the device has been reduced, the stability of device and the manufacturing yield of manufacturing yield have been improved
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (12)
1. An etching method, which is applied to manufacture of HBT devices, and comprises the following steps:
providing a substrate, wherein a collector region is formed in the substrate, a surrounding isolation layer is formed in the collector region, a base region is formed on the collector region, a first dielectric layer is formed in a region, located in the isolation layer, of the base region, a polycrystalline silicon layer is formed on the first dielectric layer and the base region, a protruding structure is formed on the polycrystalline silicon layer above the first dielectric layer, a second dielectric layer is formed on the polycrystalline silicon layer, and a third dielectric layer is formed on the second dielectric layer;
covering photoresist on the third medium layer in other areas except the target area by a photoetching process, wherein the target area is positioned in the outer edge of the isolation layer;
etching the third dielectric layer and the second dielectric layer in the target area, and removing the third dielectric layer in the target area;
carrying out isotropic etching on the polycrystalline silicon layer;
removing the polysilicon layer above the first dielectric layer by anisotropic etching;
and removing the photoresist.
2. The method of claim 1, wherein after the isotropic etching of the polysilicon layer, the polysilicon layer over the first dielectric layer has a thickness of 200 to 400 angstroms.
3. The method of claim 2, wherein the isotropic etch has a power of 500 to 900 watts.
4. The method of claim 3, wherein the reactive gas for the isotropic etching comprises oxygen and/or carbon tetrafluoride.
5. The method of claim 4, wherein the isotropic etching has a gas pressure of 0.25 torr to 0.75 torr.
6. The method of claim 1, wherein the anisotropic etching comprises main etching and over-etching, and an etching selection ratio of the medium in the over-etching is greater than that of the medium in the main etching.
7. The method of claim 6, wherein the power of the main etch is 400 watts to 800 watts.
8. The method of claim 7, wherein the reaction gas of the main etch comprises chlorine and/or hydrogen bromide.
9. The method of claim 8, wherein the main etch has a pressure of 3 mtorr to 9 mtorr.
10. The method of any of claims 6 to 9, wherein the power of the over-etching is 200 to 600 watts.
11. The method of claim 10, wherein the over-etched reactant gas comprises oxygen and/or hydrogen bromide.
12. The method of claim 11, wherein the over-etch is performed at a pressure of 25 mtorr to 75 mtorr.
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| CN202010686032.7A CN111883425B (en) | 2020-07-16 | 2020-07-16 | Etching method applied to HBT device manufacturing |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112736024A (en) * | 2020-12-23 | 2021-04-30 | 华虹半导体(无锡)有限公司 | Etching method |
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| US20060148187A1 (en) * | 2004-12-31 | 2006-07-06 | Dongbuanam Semiconductor Inc. | Self-aligned bipolar semiconductor device and fabrication method thereof |
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| CN112736024B (en) * | 2020-12-23 | 2022-06-07 | 华虹半导体(无锡)有限公司 | Etching method |
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