WO2021196758A1

WO2021196758A1 - Semiconductor device and fabrication method therefor

Info

Publication number: WO2021196758A1
Application number: PCT/CN2020/137865
Authority: WO
Inventors: 许超奇; 陈淑娴; 林峰; 马春霞
Original assignee: 无锡华润上华科技有限公司
Priority date: 2020-04-03
Filing date: 2020-12-21
Publication date: 2021-10-07
Also published as: CN113496939A

Abstract

A semiconductor device and a fabrication method therefor. The method comprises: providing a semiconductor substrate (200), a well region (201) being formed in the semiconductor substrate (200), and a mask layer (202) being formed on the semiconductor substrate (200); etching the mask layer (202) and the semiconductor substrate (200), so as to form a groove (203) that surrounds the well region (201); forming a dielectric layer (204) on a sidewall of the groove (203); forming an injection region (205) in the semiconductor substrate (200) at the bottom portion of the groove (203); and filling a conductive material (206) within the groove (203), so as to form in the semiconductor substrate (200) an isolation structure composed of the dielectric layer (204) and the conductive material (206).

Description

Semiconductor device and manufacturing method thereof

Cross-references to related applications

This application claims the priority of a Chinese patent application filed with the Chinese Patent Office on April 3, 2020, the application number is 2020102606026, and the invention title is "a semiconductor device and its manufacturing method", the entire content of which is incorporated into this application by reference middle.

Technical field

This application relates to the field of semiconductor technology, in particular to a semiconductor device and a manufacturing method thereof.

Background technique

The statements here only provide background information related to this application, and do not necessarily constitute prior art.

With the continuous development of semiconductor technology, Lateral Double Diffused MOSFET (LDMOS) devices are widely used due to their good short channel characteristics. As a power switch device, LDMOS has the characteristics of relatively high working voltage, simple process, and easy process compatibility with low-voltage CMOS circuits.

In traditional LDMOS devices, the isolation ring separates the LDMOS from the substrate through a PN junction. This method is affected by the injection conditions and the size of the isolation terminal (ISO), and the lateral or vertical breakdown voltage (BV) and punch-through (Punch) are limited, making the isolation ring one of the main reasons for the limited breakdown voltage of LDMOS. At the same time, if the PN junction isolation method requires a larger withstand voltage, the size of the isolation end and the substrate end (p-sub) is often enlarged. For example, a traditional 30V PN junction isolation ring requires an isolation ring with a width of 6um. Make the area of the whole LDMOS very large.

Therefore, it is necessary to propose a new semiconductor device and a manufacturing method thereof to solve the above-mentioned problems.

Summary of the invention

According to various embodiments of the present application, a semiconductor device and a manufacturing method thereof are provided.

A method for manufacturing a semiconductor device includes:

Providing a semiconductor substrate, a well region is formed in the semiconductor substrate, and a mask layer is formed on the semiconductor substrate;

Etching the mask layer and the semiconductor substrate to form a groove surrounding the well region;

Forming a dielectric layer on the sidewall of the groove;

Forming an injection region in the semiconductor substrate at the bottom of the groove; and

A conductive material is filled in the groove to form an isolation structure composed of the dielectric layer and the conductive material in the semiconductor substrate.

A semiconductor device including:

A semiconductor substrate, in which a well region and a groove arranged around the well region are formed, and the sidewalls of the groove are vertical sidewalls;

An injection region, the injection region is located in the semiconductor substrate at the bottom of the groove; and

The isolation structure includes a conductive material filling the groove and a dielectric layer between the conductive material and the sidewall of the groove.

The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, purposes and advantages of this application will become apparent from the description, drawings and claims.

Description of the drawings

In order to more clearly describe the technical solutions in the embodiments or exemplary technologies of the present application, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments or exemplary technologies. Obviously, the accompanying drawings in the following description are merely These are some embodiments of the present application. For those of ordinary skill in the art, without creative work, the drawings of other embodiments can also be obtained based on these drawings.

FIG. 1 is a schematic flowchart of a manufacturing method of a semiconductor device in an embodiment.

2A-2F are schematic cross-sectional views of semiconductor devices respectively obtained according to the steps sequentially implemented in the manufacturing method shown in FIG. 1.

Detailed ways

1 and 2A-2F, wherein FIG. 1 shows a flow chart of a method for manufacturing a semiconductor device in an embodiment of the present application, and FIGS. 2A-2F show the steps performed in sequence according to the manufacturing method shown in FIG. 1 Schematic cross-sectional views of the semiconductor devices respectively obtained.

The present application provides a manufacturing method of a semiconductor device. As shown in FIG. 1, the manufacturing method includes:

Step S101: Provide a semiconductor substrate, a well region is formed in the semiconductor substrate, and a mask layer is formed on the semiconductor substrate.

Step S102: etching the mask layer and the semiconductor substrate to form a groove surrounding the well region.

Step S103: forming a dielectric layer on the sidewall of the groove.

Step S104: forming an implantation area in the semiconductor substrate at the bottom of the groove. as well as

Step S105: Fill the groove with a conductive material to form an isolation structure composed of the dielectric layer and the conductive material in the semiconductor substrate.

According to the embodiment of the present application, the manufacturing method of the semiconductor device of the present application specifically includes the following steps:

As shown in FIG. 2A, first, step S101 is performed to provide a semiconductor substrate 200 in which a well region 201 is formed, and a mask layer 202 is formed on the semiconductor substrate 200.

In one of the embodiments, the semiconductor device includes an LDMOS device.

In one of the embodiments, the semiconductor substrate 200 may be at least one of the following materials: single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc. In this embodiment, the semiconductor substrate 200 is a P-type silicon substrate (P-sub), and its specific doping concentration is not limited by this application. The semiconductor substrate 200 can be formed by epitaxial growth or a wafer substrate. end.

In one of the embodiments, a well region 201 is formed in the semiconductor substrate 200.

In one of the embodiments, a well implantation process is used to form a well region 201 in the semiconductor substrate 200, and the well region 201 has a different doping type from the semiconductor substrate 200.

In one of the embodiments, the semiconductor substrate 200 can be an N-type substrate. For example, a person skilled in the art selects an N-type substrate commonly used in the art as the semiconductor substrate 200. Next, a P-type well region is formed in the N-type substrate. Specifically, first, a P-well window is formed on the N-type substrate, and P-type impurity ion implantation is performed in the P-well window; then, The annealing step is performed to advance P-type impurity ions to form a P-type well region.

In one of the embodiments, the semiconductor substrate 200 can also be a P-type substrate. For example, a person skilled in the art selects a P-type substrate commonly used in the art as the semiconductor substrate 200, and then forms the semiconductor substrate 200 in the P-type substrate. The N-type well region, specifically, first, an N-well window is formed on the P-type substrate, and N-type impurity ions are implanted in the N-well window; then, an annealing step is performed to advance the N-type impurity ions to form N-type well region.

In one of the embodiments, the semiconductor substrate 200 is a P-type silicon substrate (P-sub), and the well region 201 is an N-type well region.

In one of the embodiments, a mask layer 202 is formed on the semiconductor substrate 200.

In one of the embodiments, the mask layer 202 includes a hard mask layer, and the hard mask layer includes one of an oxide layer, a nitride layer, or a stacked structure of the two, so as to be used in a semiconductor device ( For example, LDMOS devices), the upper surface of the semiconductor substrate 200 is protected during the manufacturing process.

Continuing to refer to FIG. 2A, step S102 is performed to obtain a cross-sectional view of the semiconductor device as shown in FIG. 2A. The mask layer 202 and the semiconductor substrate 200 are etched to form a groove 203 surrounding the well region 201.

In one of the embodiments, the depth of the groove 203 is greater than the depth of the well region 201.

In one of the embodiments, the groove 203 is a groove with a high aspect ratio, and the ratio of the depth to the width of the groove 203 is greater than 5:1. Specifically, the width of the groove 203 is 0.8 μm-3μm, the depth of the groove 203 ranges from 8μm-15μm, including the end value.

In one of the embodiments, the groove 203 is formed by a deep reactive ion etching (Deep Reactive Ion Etching, DRIE) process. Specifically, the deep reactive ion etching process selects silicon hexafluoride (SF6/C4F8) gas as the process gas of the etching process, and then applies radio frequency power to make the silicon hexafluoride react to form high ionization. In the etching step: pressure Control at 15mT～45mT, source power at 400W～600W, bias power (BIAS) at -180V～-240V, flow rate of etching gas SF6 at 50 standard ml/min～70 standard ml Per minute (sccm), the flow rate of O2 is controlled between 60 standard milliliters/minute and 85 standard milliliters/minute (sccm), and the flow rate of HE is controlled between 100 standard milliliters/minute and 400 standard milliliters/minute (sccm) to ensure all directions The need for heterosexual etching. The deep reactive ion etching system used in the deep reactive ion etching process can select equipment commonly used in the art, and is not limited to a certain model.

In one of the embodiments, the sidewalls of the groove 203 need to be ensured to be vertical sidewalls, that is, the sidewalls of the groove 203 are perpendicular to the plane where the semiconductor substrate 200 is located. The topography of the vertical sidewall facilitates self-aligned injection when the injection region at the bottom of the groove 203 is subsequently formed.

In one of the embodiments, between step S102 and step S103, it further includes: a step of forming a sacrificial layer in the groove 203, and a step of removing the sacrificial layer through a wet etching process.

In one of the embodiments, a heat treatment process is performed to form a sacrificial layer in the groove 203. Specifically, a furnace tube process is used to grow a layer of silicon oxide as a sacrificial layer in the groove 203, and the thickness of the sacrificial layer ranges from 20 angstroms to 110 angstroms.

In one of the embodiments, the etching solvent of the wet etching process includes a hydrofluoric acid solution. For example, the etching solvent of the wet etching process is a buffer oxide etchant (BOE) or hydrofluoric acid. Buffer solution (buffer solution of hydrofluoric acid (BHF)).

By growing a layer of silicon oxide as a sacrificial layer in the groove 203, and then using a wet etching process to remove the sacrificial layer, the surface damage caused by deep trench etching can be reduced, and the gate oxide integrity of the sidewall can be improved. Integrity, GOI) capabilities.

Referring to FIGS. 2B and 2C, step S103 is performed to form a dielectric layer 204 on the sidewall of the groove 203 to obtain a cross-sectional view of the semiconductor device as shown in FIG. 2C.

Step S103 specifically includes:

In the first step, a heat treatment process is performed to form a dielectric layer film 204' on the mask layer 202 and the inner wall of the groove 203. The cross-sectional view of the semiconductor device is shown in FIG. 2B.

In one of the embodiments, the dielectric layer film 204' is a gate oxide film. A furnace tube process is used to grow a silicon oxide layer on the mask layer 202 and the inner wall of the groove 203 as the dielectric layer film 204'. The thickness of the dielectric layer film 204' ranges from 200 angstroms to 1000 angstroms. . Specifically, the wet oxidation process is performed by passing water vapor into the furnace tube. Compared with the dry oxidation process without passing water vapor into the furnace tube, the wet oxidation process has a faster oxidation speed and is more conducive to the formation of a thicker dielectric layer film. .

In the second step, self-aligned etching is performed, and the dielectric layer film 204' on the mask layer 202 and the bottom of the groove 203 is removed by an anisotropic etching process to obtain a dielectric layer on the sidewall of the groove 203 The cross-sectional view of the dielectric layer 204 formed by the thin film 204' and the semiconductor device is shown in FIG. 2C.

In one of the embodiments, a dry etching process may be used to remove the dielectric layer film 204' on the mask layer 202 and the bottom of the groove 203. Exemplarily, the dry etching process includes but is not limited to: a reactive ion etching (RIE) process, an ion beam etching process, a plasma etching process, a laser ablation process, or any combination of these processes. A single etching process may also be used to remove the dielectric layer film 204' on the mask layer 202 and the bottom of the groove 203, or more than one etching process may be used to remove the mask layer 202 and The dielectric layer film 204' at the bottom of the groove 203. The etching gas of the dry etching process includes at least one of a chlorine-containing chemical gas (such as HCL), a bromine-containing chemical gas (such as HBr), and a fluorine-based gas (such as CF4). Among them, the chlorine-containing chemical gas and the bromine-containing gas The chemical gas has a good selection ratio to silicon oxide while producing anisotropic etching.

Next, step S104 is performed to form an implanted region 205 in the semiconductor substrate at the bottom of the groove 203, and a cross-sectional view of the semiconductor device as shown in FIG. 2D is obtained.

Using the mask layer 202 as a mask, a self-aligned ion implantation is performed into the semiconductor substrate 200 at the bottom of the groove 203 to form a self-aligned implantation region 205 in the semiconductor substrate 200.

In one of the embodiments, the semiconductor substrate 200 is a P-type substrate, and the implantation region 205 is a P-type ion implantation region, that is, the conductivity type of the implantation region 205 and the conductivity of the semiconductor substrate 200 Same type.

By self-aligned ion implantation, only a P-type ion implantation area is formed in the semiconductor substrate 200 at the bottom of the groove 203, and other locations of the semiconductor substrate 200 cannot be implanted due to the barrier of the mask layer 202 and the dielectric layer 204, so There is no need to add a new photolithography plate to define the ion implantation area, which reduces the process steps and saves costs.

Next, step S105 is performed to fill the conductive material 206 in the groove 203 to form an isolation structure composed of the dielectric layer 204 and the conductive material 206 in the semiconductor substrate 200, and a cross-sectional view is obtained as shown in FIG. The semiconductor device shown in 2F.

In one of the embodiments, step S105 includes:

In the first step, the furnace tube grows a conductive material film 206', the conductive material film 206' covers the mask layer 202, and the conductive material film 206' is filled in the groove 203, the The upper surface of the conductive material film 206' is higher than the upper surface of the mask layer 202. At this time, the cross-sectional view of the semiconductor device is shown in FIG. 2E.

In one of the embodiments, the conductive material film 206' includes a polysilicon film. A low-pressure chemical vapor deposition (LPCVD) process can be used to form a polysilicon film.

The process conditions for forming the polysilicon thin film include: the reaction gas is silane (SiH4), and the flow rate of the silane can range from 350 standard milliliters per minute to 450 standard milliliters per minute (sccm), such as 400 sccm; the temperature range in the reaction chamber can be The temperature is 500 to 600 degrees Celsius; the pressure in the reaction chamber can be 300 millitorr to 400 millitorr (mTorr), such as 350 mTorr; the reaction gas can also include a buffer gas, and the buffer gas can be helium or nitrogen. The flow range of the helium and nitrogen can be 5 standard liters per minute to 20 standard liters per minute (slm), such as 8 slm, 10 slm, and 15 slm.

Compared with directly filling the groove 203 by chemical vapor deposition (CVD), first forming a dielectric layer on the sidewall of the groove 203 and then using low pressure chemical vapor deposition (LPCVD) to grow polysilicon can obtain a better deep groove filling effect. At the same time, by filling the groove 203 with polysilicon, the bottom of the polysilicon is connected to the silicon substrate at the bottom of the groove 203, and the implanted area 205 of the semiconductor substrate is led out by using polysilicon as a conductor to form a substrate on the surface of the semiconductor substrate ( The sub) electrode does not need to add a new area as the lead-out area of the sub electrode, which reduces the area of the semiconductor substrate. Furthermore, the polysilicon in the groove 203 can also become a longitudinal field plate, so as to increase the average electric field in the longitudinal drift region and reduce the peak value of the electric field, thereby achieving the purpose of suppressing the hot carrier effect and increasing the breakdown voltage, and further improving the performance of the LDMOS. performance. Specifically, ordinary furnace tubes are used to form the dielectric layer 204 and the conductive material 206, and there are no voids in the dielectric layer 204 and the conductive material 206, that is, the preparation method of the present application is used to obtain a better deep groove only by using ordinary furnace tubes. Filling effect.

The second step is to remove the conductive material film 206' on the mask layer and part of the conductive material film 206' in the groove 203 to obtain the conductive material 206 composed of the remaining conductive material film 206' in the groove 203. The conductive material 206 The upper surface of the semiconductor substrate 200 is flush with the upper surface of the semiconductor substrate 200.

In one of the embodiments, first, using the mask layer 202 as a barrier layer, the conductive material film 206' on the mask layer 202 and part of the conductive material in the groove 203 are etched away The thin film 206 ′, so that the upper surface of the conductive material thin film 206 ′ remaining in the groove 203 is flush with the upper surface of the semiconductor substrate 200.

In one of the embodiments, a dry etching process is used to remove the polysilicon film on the mask layer 202 and part of the polysilicon film in the groove 203. The dry etching process includes but is not limited to: a reactive ion etching (RIE) process, an ion beam etching process, a plasma etching process, or a laser cutting process.

In one of the embodiments, dry etching is performed through one RIE step or multiple RIE steps.

In one of the embodiments, the dry etching process is a plasma etching process, and the etching gas may be an etching gas based on nitrogen.

Specifically, low radio frequency energy is used to generate low-pressure and high-density plasma gas to realize the dry etching process of polysilicon. The etching gas of the dry etching process is a nitrogen-based process gas, and the flow rate of the etching gas is: 100 standard liters/minute to 200 standard liters/minute (sccm); the pressure in the reaction chamber can be 30mTorr-50mTorr, The etching time is 10 seconds to 15 seconds, the etching power is 30W to 80W, and the bias power is 0W.

The third step is to remove the mask layer 202 on the semiconductor substrate 200 and part of the dielectric layer 204 in the groove 203, and the upper surface of the remaining dielectric layer 204 in the groove 203 and The upper surface of the conductive material 206 in the groove 203 is flush, and the dielectric layer 204 and the conductive material 206 in the groove 203 constitute the isolation structure. At this time, a cross-sectional view of the semiconductor device is shown in FIG. 2F Shown. That is, after removing the mask layer 202 on the semiconductor substrate 200 and part of the dielectric layer 204 in the groove 203, the upper surface of the semiconductor substrate 200 and the inside of the groove 203 The upper surface of the dielectric layer 204 and the upper surface of the conductive material 206 in the groove 203 are on the same plane.

In one of the embodiments, the mask layer 202 and a part of the dielectric layer 204 may be removed by at least one etching process of a dry etching process, a wet etching process, and a grinding process. The dry etching process includes, but is not limited to: a reactive ion etching (RIE) process, an ion beam etching process, a plasma etching process, a laser ablation process, or any combination of these etching processes. A single etching process can be used to form the isolation structure composed of the dielectric layer 204 and the conductive material 206 in the semiconductor substrate 200, or more than one etching process can be used to form the isolation structure composed of the dielectric layer 204 and the conductive material in the semiconductor substrate 200. Isolation structure composed of material 206. The etching gas of the dry etching process may include HBr and/or CF4 gas.

In one of the embodiments, the mask layer 202, part of the conductive material film 206' and part of the dielectric layer 204 on the semiconductor substrate 200 can be removed by chemical mechanical polishing (CMP) to expose all The semiconductor substrate 200 and the isolation structure.

In one of the embodiments, the method for manufacturing the semiconductor device further includes the step of preparing other structures of the semiconductor device in the well region 201.

The structure of the semiconductor device provided in the embodiment of the present application will be described below with reference to FIG. 2F. The semiconductor device includes:

A semiconductor substrate 200 in which a well region 201 and a groove arranged around the well region 201 are formed;

An implantation area 205, the implantation area 205 is located in the semiconductor substrate 200 at the bottom of the groove; and

The isolation structure includes a conductive material 206 filling the groove and a dielectric layer 204 between the conductive material 206 and the sidewall of the groove.

In one of the embodiments, the semiconductor device includes an LDMOS device.

In one of the embodiments, the semiconductor substrate 200 may be at least one of the following materials: single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc. In this embodiment, the semiconductor substrate 200 is a P-type silicon substrate (P-sub), and its specific doping concentration is not limited by this application. The semiconductor substrate 200 can be formed by epitaxial growth or a crystal. Round substrate.

In one of the embodiments, a well region 201 is formed in the semiconductor substrate 200, and the well region 201 has a different doping type from the semiconductor substrate 200. In this embodiment, the semiconductor substrate 200 is a P-type silicon substrate (P-sub), and the well region 201 is an N-type well region.

In one of the embodiments, a mask layer is formed on the semiconductor substrate 200. The mask layer includes an oxide layer, a nitride layer, or a stacked structure of both.

In one of the embodiments, the depth of the groove is greater than the depth of the well region 201.

In one of the embodiments, the groove is a groove with a high aspect ratio, and the ratio of the depth to the width of the groove is greater than 5:1. Specifically, the width of the groove ranges from 0.8 μm to 3 μm. , The depth of the groove is in the range of 8 μm-15 μm, including the end value.

In one of the embodiments, the sidewalls of the groove are vertical sidewalls, that is, the sidewalls of the groove are perpendicular to the plane where the semiconductor substrate 200 is located. The topography of the vertical sidewall facilitates subsequent implementation of self-aligned implantation of the implantation area at the bottom of the groove.

In one of the embodiments, the semiconductor substrate 200 at the bottom of the groove is formed with an implanted region 205, the implanted region 205 is a self-aligned implanted region, and the implanted region 205 is a P-type ion implanted region, that is, The conductivity type of the implanted region 205 is the same as the conductivity type of the semiconductor substrate 200.

In one of the embodiments, an isolation structure is formed in the groove. The isolation structure includes a conductive material 206 filling the groove and a dielectric layer 204 between the conductive material 206 and the sidewall of the groove.

In one of the embodiments, the dielectric layer 204 includes a silicon oxide layer, and the thickness of the dielectric layer 204 ranges from 200 angstroms to 1000 angstroms.

In one of the embodiments, the conductive material includes polysilicon, and the conductive material is electrically connected to the substrate electrode on the surface of the semiconductor substrate.

By filling the groove with polysilicon, the bottom of the polysilicon is connected to the silicon substrate at the bottom of the groove, and the injection area 205 of the semiconductor substrate is led out by using polysilicon as a conductor, and a sub electrode is formed on the surface of the semiconductor substrate without additional area As the sub-electrode lead-out area, the area of the semiconductor substrate is reduced. Furthermore, the polysilicon in the groove can also become a vertical field plate to increase the average electric field in the vertical drift zone and reduce the peak value of the electric field, so as to achieve the purpose of suppressing the hot carrier effect, increasing the breakdown voltage, and further improving the performance of LDMOS. .

This application has been described by the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of example and description, and are not intended to limit the present application to the scope of the described embodiments. In addition, those skilled in the art can understand that this application is not limited to the above-mentioned embodiments, and more variations and modifications can be made according to the teachings of this application, and these variations and modifications fall within the scope of what is claimed in this application. Within the range. The protection scope of this application is defined by the appended claims and their equivalent scope.

Claims

A method for manufacturing a semiconductor device includes:

Providing a semiconductor substrate, a well region is formed in the semiconductor substrate, and a mask layer is formed on the semiconductor substrate;

Etching the mask layer and the semiconductor substrate to form a groove surrounding the well region;

Forming a dielectric layer on the sidewall of the groove;

Forming an injection region in the semiconductor substrate at the bottom of the groove; and

A conductive material is filled in the groove to form an isolation structure composed of the dielectric layer and the conductive material in the semiconductor substrate.
The manufacturing method according to claim 1, wherein after said etching said mask layer and said semiconductor substrate to form a groove surrounding said well region, before forming a dielectric layer on the sidewall of said groove ,Also includes:

Performing a heat treatment process to form a sacrificial layer in the groove; and

The sacrificial layer is removed by a wet etching process.
The manufacturing method according to claim 1, wherein the step of forming the dielectric layer on the sidewall of the groove further comprises:

Performing a heat treatment process to form a dielectric layer film on the mask layer and the inner wall of the groove; and

Perform self-aligned etching, and remove the dielectric layer film on the mask layer and the bottom of the groove through an anisotropic etching process to obtain a dielectric layer composed of the dielectric layer film on the sidewall of the groove. The dielectric layer film is a gate oxide film.
The manufacturing method of claim 1, wherein the step of filling a conductive material in the groove to form an isolation structure composed of the dielectric layer and the conductive material in the semiconductor substrate comprises:

The furnace tube grows a conductive material film, the conductive material film is covered on the mask layer, and the conductive material film is filled in the groove, and the upper surface of the conductive material film is higher than the mask The upper surface of the layer;

The conductive material film on the mask layer and a part of the conductive material film in the groove are removed to obtain the conductive material composed of the conductive material film remaining in the groove. The upper surface is flush with the upper surface of the semiconductor substrate; and

Removing the mask layer on the semiconductor substrate and part of the dielectric layer in the groove, and the upper surface of the remaining dielectric layer in the groove is flush with the upper surface of the conductive material, The dielectric layer and the conductive material in the groove constitute the isolation structure.
The manufacturing method of claim 1, wherein the depth of the groove is greater than the depth of the well region.
The manufacturing method of claim 1, wherein the ratio of the depth of the groove to the width of the groove is greater than 5:1.
8. The manufacturing method of claim 1, wherein the thickness of the dielectric layer ranges from 200 angstroms to 1000 angstroms.
8. The manufacturing method of claim 1, wherein a deep reactive ion etching process is performed to form the groove, and the sidewalls of the groove are vertical sidewalls.
8. The manufacturing method of claim 1, wherein self-aligned ion implantation is performed to form the implanted region, and the implanted region is a self-aligned implanted region.
A semiconductor device including:

A semiconductor substrate, in which a well region and a groove arranged around the well region are formed, and the sidewalls of the groove are vertical sidewalls;

An injection region, the injection region is located in the semiconductor substrate at the bottom of the groove; and

The isolation structure includes a conductive material filling the groove and a dielectric layer between the conductive material and the sidewall of the groove.
The semiconductor device according to claim 10, wherein the depth of the groove is greater than the depth of the well region.
The semiconductor device according to claim 10, wherein the ratio of the depth of the groove to the width of the groove is greater than 5:1.
The semiconductor device according to claim 10, wherein the thickness of the dielectric layer is in the range of 200 angstroms to 1000 angstroms.
11. The semiconductor device of claim 10, wherein the sidewalls of the groove are vertical sidewalls, and the implantation region is a self-aligned implantation region.
The semiconductor device according to claim 10, wherein the conductive material is electrically connected to the substrate electrode on the surface of the semiconductor substrate.