CN111865615A - APUF circuit with detectable reliability and working method - Google Patents
APUF circuit with detectable reliability and working method Download PDFInfo
- Publication number
- CN111865615A CN111865615A CN202010748501.3A CN202010748501A CN111865615A CN 111865615 A CN111865615 A CN 111865615A CN 202010748501 A CN202010748501 A CN 202010748501A CN 111865615 A CN111865615 A CN 111865615A
- Authority
- CN
- China
- Prior art keywords
- selector
- signal
- inverter
- input
- delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
- H04L9/3271—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response
- H04L9/3278—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response using physically unclonable functions [PUF]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
Landscapes
- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Manipulation Of Pulses (AREA)
Abstract
The invention provides an APUF circuit with detectable reliability and a working method, and belongs to the technical field of information security. According to the invention, the inverter and the selector are inserted into the APUF circuit, so that the time delay of a link is increased by the inverter; and a latch circuit based on an inverter is inserted, so that the state of the circuit under the current excitation can be captured, and the delay difference is quantized in each stage of basic delay unit, so that the delay difference generated by the current excitation is judged, and the relative reliability of APUF under the current excitation is further judged. The method has the advantage of light weight, does not need an external complex special circuit for detection, and has a certain application prospect.
Description
Technical Field
The invention belongs to the technical field of information security, and particularly relates to an APUF circuit with detectable reliability and a working method.
Background
Physical Unclonable Functions (PUFs), an emerging hardware security mechanism, are of great interest because of their unique unclonable/unpredictable properties. The method utilizes the manufacturing difference of nanometer scale in the manufacturing process of the integrated circuit, is widely applied to the fields of key generation, security authentication and the like, and particularly has wide application scenes in low-cost IoT equipment.
APUF is the most widely studied string PUF that uses the line delay differences generated during integrated circuit fabrication to generate a unique output. Wherein, by secondaryThe clipper judges the arrival sequence of the rising edge signals in the upper and lower delay lines and extracts the response value. This has the advantage that exponential excitation-Response Pairs (CRPs) can be generated, for example in an APUF with 64 basic delay units of 64 stages, with a Challenge signal of 64-bits and an excitation Response pair of 264。
However, under some excitation, the time difference between the two delay chains is so small that the delay difference is easily covered by noise or cannot be captured by the arbiter, resulting in reliability problems at the output (response). Therefore, judging the delay difference of the excitation, extracting the excitation with larger delay difference for application is one of the methods for improving the reliability of the APUF.
However, the existing APUF structure detects the arrival sequence of the delay link through a D trigger to generate a response, and cannot detect the delay difference of the delay link. And the response reliability generated by smaller delay difference is poor, which affects the practical application of the APUF circuit. In order to detect the reliability of the APUF circuit, an external special detection circuit is required to be designed, which results in a complex circuit structure. Therefore, the APUF circuit and the detection method for detecting the reliability without an external complex special circuit are researched, and the APUF circuit and the detection method have a high application prospect.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides an APUF circuit with detectable reliability and a working method thereof, wherein an inverter and a selector are inserted into an APUF link, and the inverter makes the delay of the link larger; and a latch circuit based on an inverter is inserted, so that the state of the circuit under the current excitation can be captured, and the delay difference is quantized in each stage of basic delay unit, so that the delay difference generated by the current excitation is judged, and the relative reliability of APUF under the current excitation is further judged. The method has the advantage of light weight, does not need an external complex special circuit for detection, and has a certain application prospect.
In order to solve the technical problems, the invention provides the following technical scheme:
the invention provides an APUF circuit with detectable reliability, which comprises: the pulse generator, n stages of basic delay units connected in series and the D trigger. The basic delay units of each stage have the same structure and are provided with four input signal ends, two control signal ends and two output signal ends.
The first input signal end, the second input signal end, the third input signal end and the fourth input signal end of the first-stage basic delay unit are connected with the output end of the pulse generator, the first output signal end of the first-stage basic delay unit is connected with the first input signal end and the fourth input signal end of the second-stage basic delay unit, and the second output signal end of the first-stage basic delay unit is connected with the second input signal end and the third input signal end of the second-stage basic delay unit; the first output signal end of the second-stage basic delay unit is connected with the first input signal end and the fourth input signal end of the third-stage basic delay unit, and the second output signal end of the second-stage basic delay unit is connected with the second input signal end and the third input signal end of the third-stage basic delay unit; by analogy, a first output signal end of the n-1 th-level basic delay unit is connected with a first input signal end and a fourth input signal end of the n-level basic delay unit, and a second output signal end of the n-1 th-level basic delay unit is connected with a second input signal end and a third input signal end of the n-level basic delay unit; and a first output signal end of the nth stage basic delay unit is connected with a data end of the D trigger, and a second output signal end of the nth stage basic delay unit is connected with a clock pulse end of the D trigger. When the transmission speed of the output signal of the second output signal end of the nth stage basic delay unit is higher than the propagation speed of the output signal of the first output signal end of the nth stage basic delay unit, the output end of the D trigger outputs 0, otherwise, 1.
The first control signal ends of all stages of basic delay units are all connected with the latch signal. The latch signal is a 1-bit signal, so that the basic delay units of each stage share the 1-bit latch signal. The second control signal ends of all levels of basic delay units are all connected with excitation signals, the excitation signals are n-bit signals, therefore, all levels of basic delay units use 1-bit signals therein as the excitation signals in sequence, namely, the first level of basic delay units use the 1-bit excitation signals on the first bit, the second level of basic delay units use the 1-bit excitation signals on the second bit, and so on, the nth level of basic delay units use the 1-bit excitation signals on the nth bit.
The basic delay unit includes: the first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter, the eighth inverter, the first selector, the second selector, the third selector, the fourth selector, the fifth selector and the sixth selector.
Further, the first selector, the second selector, the third selector, the fourth selector, the fifth selector, and the sixth selector are all two-out-of-one selectors, and have two gating states: gating an external input state and gating a feedback signal state.
One input end of the first selector is connected with the output end of the first inverter, the other input end of the first selector is connected with the first input signal end of the basic delay unit, the output end of the first selector is connected with the input end of the second inverter, and the control end of the first selector is connected with the first control signal end, namely the latch signal; one input end of the second selector is connected with the second input signal end, the other input end of the second selector is connected with the output end of the fourth inverter, the output end of the second selector is connected with the input end of the third inverter, and the control end of the second selector is connected with the first control signal end, namely, the latch signal; one input end of the third selector is connected with the output end of the second phase inverter, the other input end of the third selector is connected with the output end of the third phase inverter, the output end of the third selector is connected with the input end of the first phase inverter, the input end of the fourth phase inverter and the first output signal end, and the control end of the third selector is connected with the second control signal end, namely connected with the excitation signal. Furthermore, the first selector, the second selector, the third selector, the first inverter, the second inverter, the third inverter and the fourth inverter form an upper delay link.
One input end of the fourth selector is connected with the output end of the fifth inverter, the other input end of the fourth selector is connected with the third input signal end, the output end of the fourth selector is connected with the input end of the sixth inverter, and the control end of the fourth selector is connected with the first control signal end, namely, the fourth selector is connected with the latch signal; one input end of the fifth selector is connected with the fourth input signal end, the other input end of the fifth selector is connected with the output end of the eighth inverter, the output end of the fifth selector is connected with the input end of the seventh inverter, and the control end of the fifth selector is connected with the first control signal end, namely, the latch signal; one input end of the sixth selector is connected with the output end of the sixth inverter, the other input end of the sixth selector is connected with the output end of the seventh inverter, the output end of the sixth selector is connected with the input end of the fifth inverter, the input end of the eighth inverter and the second output signal end, and the control end of the sixth selector is connected with the second control signal end, namely connected with the excitation signal. Further, a fourth selector, a fifth selector, a sixth selector, a fifth inverter, a sixth inverter, a seventh inverter, and an eighth inverter form a lower delay chain.
The APUF circuit with the detectable reliability has two working modes, namely an APUF circuit mode and a reliability detection mode.
In the APUF mode, the pulse signal accurately generated by the pulse generator is a rising edge signal; the first selector and the second selector in the upper delay chain and the fourth selector and the fifth selector in the lower delay chain are controlled to be in a gating external input state by the latch signal, so that an external signal can be input into the basic delay unit of the stage, and the output of the basic delay unit of the stage is input into the basic delay unit of the next stage. At this time, the excitation signal simultaneously controls the third selector in the upper delay chain and the sixth selector in the lower delay chain, so as to select one input signal of the third selector as the output signal of the first output signal terminal and one input signal of the sixth selector as the output signal of the second output signal terminal, that is, to implement the cross or parallel transmission of signals, thereby implementing the basic function of the APUF.
Further, in the APUF mode, only the second inverter and the third inverter in the upper delay chain are in working state, and only the sixth inverter and the seventh inverter in the lower delay chain are in working state.
In the reliability detection mode, the pulse signal precisely generated by the pulse generator is a hold signal with a length t 1; the latch signal controls the first selector and the second selector in the upper delay link and the fourth selector and the fifth selector in the lower delay link to be in a gating feedback signal state, so that the internal signal is latched in the basic delay unit of the current stage and cannot be transmitted to the basic delay unit of the next stage, the function of recording the circuit state at the moment can be realized, and the delay difference between the upper delay link and the lower delay link under the current excitation signal is further judged.
Further, in the reliability detection mode, the first inverter and the second inverter in the upper delay link jointly form a state latch circuit, the third inverter and the fourth inverter jointly form a state latch circuit, and the fifth inverter and the sixth inverter in the lower delay link jointly form a state latch circuit, and the seventh inverter and the eighth inverter jointly form a state latch circuit.
The APUF circuit with the detectable reliability adopts a plurality of inverters to form a circuit state latch circuit, so that a circuit state latch function is added into the APUF circuit, the circuit can detect the delay characteristic of a specific excitation signal, and the excitation signal with high reliability is selected for application.
The invention provides an operating method of an APUF circuit with detectable reliability, which comprises an operating method in an APUF mode and an operating method in a reliability detection mode.
The working method under the APUF mode comprises the following specific steps:
step A1: configuring an excitation signal;
step A2: the latch signal gates the external input;
step A3: the pulse generator generates a rising edge signal;
step A4: and reading the output signal of the D flip-flop.
The working method under the reliability detection mode comprises the following specific steps:
step B1: configuring an excitation signal Challenge;
step B2: latching signal Lock strobes external input;
step B3: the pulse generator generates a hold signal of length t 1;
step B4: the latch signal Lock gates the feedback signal, namely, the feedback signal enters a latch state;
step B5: reading the latched values of the upper delay link and the lower delay link in each level of basic delay units;
step B6: the delay difference Δ t between the upper delay link and the lower delay link is calculated.
Compared with the prior art, the APUF circuit with the detectable reliability and the working method thereof have the following benefits:
1. and a latch circuit based on an inverter is inserted, so that the state of the circuit under the current excitation can be captured, and the delay difference is quantized in each stage of basic delay unit, so that the delay difference generated by the current excitation is judged, and the relative reliability of APUF under the current excitation is further judged.
2. The method has the advantage of light weight, and for n-level APUF, the delay difference can be quantized only by adding 4n inverters and 4n alternative selectors, and no external complex special circuit is required for detection.
3. The method is also applicable to other PUF circuit structures based on time delay.
Drawings
Fig. 1 is a schematic circuit diagram of an apdu circuit with detectable reliability according to the present invention;
fig. 2 is a schematic diagram of a circuit structure of a single basic delay cell in an apdu circuit with detectable reliability according to the present invention;
FIG. 3 is a flow chart of the operation of an APUF circuit in APUF mode for which the present invention is capable of detecting reliability;
fig. 4 is a flowchart illustrating the operation of an apdu circuit with a detectable reliability in a reliability detection mode according to the present invention;
fig. 5 is a timing diagram of a system in which the APUF circuit capable of detecting reliability is in a reliability detection mode, and a first case of a delay difference between an upper delay link and a lower delay link is shown;
FIG. 6 is a timing diagram of a system in a reliability detection mode for a reliability-detectable APUF circuit, a second case of a delay difference between an upper delay link and a lower delay link;
fig. 7 is a third case of the system timing diagram, the delay difference between the upper delay link and the lower delay link of the reliability-detectable APUF circuit in the reliability detection mode according to the present invention;
fig. 8 is a fourth case of the system timing diagram, the delay difference between the upper delay link and the lower delay link of the reliability-detectable APUF circuit in the reliability detection mode.
Detailed Description
The present invention will be described in further detail with reference to examples.
Example 1. The invention provides an APUF circuit with the reliability detectable, and the circuit structure of the APUF circuit is shown as the attached figure 1. The reliability-detectable APUF circuit includes: the pulse generator, n stages of basic delay units connected in series and the D trigger. The basic delay units of each stage have the same structure and are provided with four input signal ends, two control signal ends and two output signal ends.
In the preferred embodiment, the number of the basic delay units connected in series is 64, and the schematic circuit structure of the basic delay units is shown in fig. 2 in detail. The electrical connection relationship between the basic delay units is described in detail with reference to fig. 1 and 2, and specifically as follows:
the first Input signal end Input1, the second Input signal end Input2, the third Input signal end Input3 and the fourth Input signal end Input4 of the first-stage basic delay unit 1 are all connected with the Output end of the pulse generator, the first Output signal end Output1 of the first-stage basic delay unit 1 is connected with the first Input signal end Input1 and the fourth Input signal end Input4 of the second-stage basic delay unit 2, and the second Output signal end Output2 of the first-stage basic delay unit 1 is connected with the second Input signal end Input2 and the third Input signal end Input3 of the second-stage basic delay unit 2; a first Output signal end Output1 of the second-stage basic delay unit 2 is connected with a first Input signal end Input1 and a fourth Input signal end Input4 of the third-stage basic delay unit 3, and a second Output signal end Output2 of the second-stage basic delay unit 2 is connected with a second Input signal end Input2 and a third Input signal end Input3 of the third-stage basic delay unit 3; by analogy, a first Output signal terminal Output1 of the 64 th-stage basic delay unit 64 is connected to the data terminal D of the D flip-flop, and a second Output signal terminal Output2 of the 64 th-stage basic delay unit 64 is connected to the clock pulse terminal CLK of the D flip-flop. When the transmission speed of the Output signal of the second Output signal terminal Output2 of the 64 th stage basic delay unit 64 is faster than the propagation speed of the Output signal of the first Output signal terminal Output1, the Output terminal of the D flip-flop outputs 0, otherwise outputs 1.
The first control signal ends of all levels of basic delay units are all connected with a latch signal Lock, and the second control signal ends of all levels of basic delay units are all connected with an excitation signal Challenge.
The latch signal Lock is a 1-bit signal, so that the n groups of basic delay units share the 1-bit latch signal Lock. The excitation signal Challenge is an n-bit signal, so that n groups of basic delay units sequentially use 1-bit signals in the n groups of basic delay units as the excitation signal Challenge; in the preferred embodiment, the excitation signal Challenge is a 64-bit signal, the first-stage basic delay unit uses a 1-bit excitation signal on the first bit, the second-stage basic delay unit uses a 1-bit excitation signal on the second bit, and so on, and the 64 th-stage basic delay unit uses a 1-bit excitation signal on the 64 th bit.
Example 2. The circuit structure of the basic delay unit is shown in fig. 2, and the basic delay unit includes: a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, an eighth inverter INV8, a first selector Mux1, a second selector Mux2, a third selector Mux3, a fourth selector Mux4, a fifth selector Mux5, a sixth selector Mux 6.
One Input end of the first selector Mux1 is connected to the output end of the first inverter INV1, the other Input end of the first selector Mux 3578 is connected to the first Input signal end Input1, the output end of the first selector Mux1 is connected to the Input end of the second inverter INV2, and the control end of the first selector Mux1 is connected to the first control signal end, that is, to the latch signal Lock; one Input end of the second selector Mux2 is connected to the second Input signal end Input2, the other Input end is connected to the output end of the fourth inverter INV4, the output end of the second selector Mux2 is connected to the Input end of the third inverter INV3, and the control end of the second selector Mux2 is connected to the first control signal end, that is, to the latch signal Lock; an input end of the third selector Mux3 is connected to the Output end of the second inverter INV2, another input end is connected to the Output end of the third inverter INV3, an Output end of the third selector Mux3 is connected to the input end of the first inverter INV1, the input end of the fourth inverter INV4 and the first Output signal end Output1, and a control end of the third selector Mux3 is connected to the second control signal end, that is, to the excitation signal change. Further, the first selector Mux1, the second selector Mux2, the third selector Mux3, the first inverter INV1, the second inverter INV2, the third inverter INV3, and the fourth inverter INV4 form an upper delay chain.
One Input end of the fourth selector Mux4 is connected to the output end of the fifth inverter INV5, the other Input end of the fourth selector Mux 3578 is connected to the third Input signal end Input3, the output end of the fourth selector Mux4 is connected to the Input end of the sixth inverter INV6, and the control end of the fourth selector Mux4 is connected to the first control signal end, that is, to the latch signal Lock; one Input end of the fifth selector Mux5 is connected to the fourth Input signal end Input4, the other Input end of the fifth selector Mux 3578 is connected to the output end of the eighth inverter INV8, the output end of the fifth selector Mux5 is connected to the Input end of the seventh inverter INV7, and the control end of the fifth selector Mux5 is connected to the first control signal end, that is, to the latch signal Lock; one input end of the sixth selector Mux6 is connected to the Output end of the sixth inverter INV6, the other input end of the sixth selector Mux 3578 is connected to the Output end of the seventh inverter INV7, the Output end of the sixth selector Mux6 is connected to the input end of the fifth inverter INV5, the input end of the eighth inverter INV8 and the second Output signal end Output2, and the control end of the sixth selector Mux6 is connected to the second control signal end, that is, to the excitation signal change. Further, a fourth selector Mux4, a fifth selector Mux5, a sixth selector Mux6, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, and an eighth inverter INV8 constitute a down-delay chain.
Example 3. The APUF circuit with the detectable reliability has two working modes, namely an APUF circuit mode and a reliability detection mode.
In the APUF mode, the pulse signal accurately generated by the pulse generator is a rising edge signal; in the reliability detection mode, the pulse signal precisely generated by the pulse generator is a hold signal of length t 1.
In an APUF mode, a basic delay module realizes cross or parallel transmission of input pulse signals; and in the reliability detection mode, the basic delay module latches the current circuit state.
The first selector Mux1, the second selector Mux2, the third selector Mux3, the fourth selector Mux4, the fifth selector Mux5, and the sixth selector Mux6 are all alternative selectors, and have two gating states: gating an external input state and gating a feedback signal state. The gating state of the selector is controlled by the latch signal Lock, which is as follows:
(1) in the APUF mode, the latch signal Lock controls the first and second selectors Mux1 and Mux2 in the up-delay link and the fourth and fifth selectors Mux4 and Mux5 in the down-delay link to be in the gated external input state, so that an external signal can be input into the basic delay unit of the current stage, and the output of the basic delay unit of the current stage will be input into the basic delay unit of the next stage. At this time, the excitation signal change simultaneously controls the third selector Mux3 in the upper delay link and the sixth selector Mux6 in the lower delay link, so as to select one input signal of the third selector Mux3 as the output signal of the first output signal terminal and one input signal of the sixth selector Mux6 as the output signal of the second output signal terminal, that is, to implement cross or parallel transmission of signals, thereby implementing the basic function of the APUF.
Further, in the APUF mode, only the second inverter INV2 and the third inverter INV3 in the upper delay link are in an operating state, and only the sixth inverter INV6 and the seventh inverter INV7 in the lower delay link are in an operating state.
(2) In the reliability detection mode, the latch signal Lock controls the first selector Mux1 and the second selector Mux2 in the upper delay link and the fourth selector Mux4 and the fifth selector Mux5 in the lower delay link to be in the state of gating feedback signals, so that the internal signal is latched in the basic delay unit of the current stage and cannot be transmitted to the basic delay unit of the next stage, and therefore, the function of recording the state of the circuit at the moment can be realized, and the delay difference between the upper delay link and the lower delay link under the current excitation signal Challenge is further judged.
Further, in the reliability detection mode, the first inverter INV1 and the second inverter INV2 in the upper delay link together form a state latch circuit, the third inverter INV3 and the fourth inverter INV4 together form a state latch circuit, the fifth inverter INV5 and the sixth inverter INV6 in the lower delay link together form a state latch circuit, and the seventh inverter INV7 and the eighth inverter INV8 together form a state latch circuit.
The APUF circuit with the detectable reliability, provided by the invention, adopts a plurality of inverters to form a circuit state latch circuit, so that a circuit state latch function is added into the APUF circuit, the circuit can detect the delay characteristic of a specific excitation signal Challenge, and the excitation signal Challenge with high reliability is selected for application.
Example 4. The invention provides an operating method of an APUF circuit with detectable reliability, which comprises an operating method in an APUF mode and an operating method in a reliability detection mode.
A flow chart of the working method in the APUF mode is shown in fig. 3, and the specific steps are as follows:
step A1: configuring an excitation signal Challenge;
the configured excitation signal is an n-bit signal, the third selector Mux3 and the fourth selector Mux4 in each stage of basic delay unit sequentially use the 1-bit signal as the excitation signal change, and the third selector Mux3 and the fourth selector Mux4 in the same stage of basic delay unit share the same excitation signal;
step A2: latching signal Lock strobes external input;
the latch signal Lock controls the first selector Mux1 and the second selector Mux2 in the up-delay link and the fourth selector Mux4 and the fifth selector Mux5 in the down-delay link to be in the gated external input state;
step A3: the pulse generator generates a rising edge signal;
the rising edge signal generated by the pulse generator is synchronously Input to a first Input end 1, a second Input end 2, a third Input end 3 and a fourth Input end 4 of the first-stage basic delay unit;
step A4: reading an output signal of the D trigger;
the output end Q of the D flip-flop outputs a response signal under the excitation signal Challenge currently.
A flowchart of the working method in the reliability detection mode is shown in fig. 4, and the specific steps are as follows:
step B1: configuring an excitation signal Challenge;
the configured excitation signal is an n-bit signal, the third selector Mux3 and the fourth selector Mux4 in each stage of basic delay unit sequentially use the 1-bit signal as the excitation signal change, and the third selector Mux3 and the fourth selector Mux4 in the same stage of basic delay unit share the same excitation signal;
step B2: latching signal Lock strobes external input;
the latch signal Lock controls the first selector Mux1 and the second selector Mux2 in the up-delay link and the fourth selector Mux4 and the fifth selector Mux5 in the down-delay link to be in the gated external input state;
step B3: the pulse generator generates a hold signal of length t 1;
a holding signal with the length of t1 generated by the pulse generator is synchronously Input to a first Input end 1, a second Input end 2, a third Input end 3 and a fourth Input end 4 of the first-stage basic delay unit;
further, the length t1 needs to be close to the delay of each delay link, and can be determined by means of back-end simulation and the like;
step B4: the latch signal Lock gates the feedback signal, namely, the feedback signal enters a latch state;
at this time, the latch signal Lock is reconfigured, the first selector Mux1 and the second selector Mux2 in the upper delay link and the fourth selector Mux4 and the fifth selector Mux5 in the lower delay link are controlled to be in the gating feedback signal state, at this time, the first inverter INV1 and the second inverter INV2 in the upper delay link together form a state latch circuit, the third inverter INV3 and the fourth inverter INV4 together form a state latch circuit, the fifth inverter INV5 and the sixth inverter INV6 in the lower delay link together form a state latch circuit, the seventh inverter INV7 and the eighth inverter INV8 together form a state latch circuit, that is, the basic delay units of each stage can latch the state of each stage at this moment;
step B5: reading the latched values of the upper delay link and the lower delay link in each level of basic delay units;
step B6: calculating the delay difference Δ t between the upper delay link and the lower delay link, which specifically includes the following four cases:
(1) the pull-up signals are transmitted in both the upper delay link and the lower delay link, and the delay difference is small, as shown in fig. 5, at this time, the delay difference Δ t of the upper delay link and the lower delay link is the difference between the rising edge and the falling edge, and the delay difference is two basic delay units through quantization;
(2) the pull-up signal is transmitted in both the upper delay link and the lower delay link, and the delay difference is large, as shown in fig. 6, at this time, the delay difference Δ t between the upper delay link and the lower delay link is the difference of the falling edges;
(3) the transmission of the pull-up signal in the upper delay link is completed, and the transmission of the pull-up signal in the lower delay link is still performed, as shown in fig. 7, at this time, the delay difference Δ t between the upper delay link and the lower delay link is greater than the length t1 of the hold signal generated by the pulse generator;
(4) the pull-up signals in the upper delay link and the lower delay link are latched into the same level of basic delay unit, at the moment, the delay time difference delta t of the upper delay link and the lower delay link cannot be calculated, and the current excitation signal can be judged to be the worst reliability.
The above embodiments and examples are specific supports for the technical ideas of the APUF circuit and the operating method with detectable reliability, and therefore, the protection scope of the present invention is not limited thereto, and any equivalent changes or equivalent modifications made on the basis of the technical solutions according to the technical ideas presented by the present invention still belong to the protection scope of the technical solutions provided by the present invention.
Claims (8)
1. A reliability-detectable APUF circuit, comprising: the pulse generator, n stages of basic delay units connected in series and the D trigger are connected in series;
the structure of each stage of basic delay unit is completely the same, and the basic delay units are provided with four input signal ends, two control signal ends and two output signal ends;
a first input signal end, a second input signal end, a third input signal end and a fourth input signal end of the first-stage basic delay unit are all connected with the output end of the pulse generator, a first output signal end of the first-stage basic delay unit is connected with a first input signal end and a fourth input signal end of the second-stage basic delay unit, and a second output signal end of the first-stage basic delay unit is connected with a second input signal end and a third input signal end of the second-stage basic delay unit; the first output signal end of the second-stage basic delay unit is connected with the first input signal end and the fourth input signal end of the third-stage basic delay unit, and the second output signal end of the second-stage basic delay unit is connected with the second input signal end and the third input signal end of the third-stage basic delay unit; by analogy, a first output signal end of the n-1 th-level basic delay unit is connected with a first input signal end and a fourth input signal end of the n-level basic delay unit, and a second output signal end of the n-1 th-level basic delay unit is connected with a second input signal end and a third input signal end of the n-level basic delay unit; and a first output signal end of the nth stage basic delay unit is connected with a data end of the D trigger, and a second output signal end of the nth stage basic delay unit is connected with a clock pulse end of the D trigger. When the transmission speed of the output signal of the second output signal end of the nth-stage basic delay unit is higher than the propagation speed of the output signal of the first output signal end of the nth-stage basic delay unit, the output end of the D trigger outputs 0, otherwise, 1 is output;
the first control signal end of each stage of basic delay unit is connected with a latch signal, and the second control signal end of each stage of basic delay unit is connected with an excitation signal;
the APUF circuit with the detectable reliability has two working modes: an APUF mode and a reliability detection mode;
in the APUF mode, the basic delay units of all levels are simultaneously controlled through a latch signal and an excitation signal, so that external signals are transmitted from the basic delay unit of the level to the basic delay unit of the next level;
in the reliability detection mode, the basic delay units at all levels are controlled by the latch signal, so that the internal signal is latched in the basic delay units at all levels and cannot be transmitted to the basic delay unit at the next level.
2. The APUF circuit and method of claim 1, wherein the APUF circuit and method of operation,
the basic delay unit includes: the first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter, the eighth inverter, the first selector, the second selector, the third selector, the fourth selector, the fifth selector and the sixth selector;
one input end of the first selector is connected with the output end of the first inverter, the other input end of the first selector is connected with the first input signal end of the basic delay unit, the output end of the first selector is connected with the input end of the second inverter, and the control end of the first selector is connected with the first control signal end, namely the latch signal; one input end of the second selector is connected with the second input signal end, the other input end of the second selector is connected with the output end of the fourth inverter, the output end of the second selector is connected with the input end of the third inverter, and the control end of the second selector is connected with the first control signal end, namely, the latch signal; one input end of the third selector is connected with the output end of the second phase inverter, the other input end of the third selector is connected with the output end of the third phase inverter, the output end of the third selector is connected with the input end of the first phase inverter, the input end of the fourth phase inverter and the first output signal end, and the control end of the third selector is connected with the second control signal end, namely connected with the excitation signal;
one input end of the fourth selector is connected with the output end of the fifth inverter, the other input end of the fourth selector is connected with the third input signal end, the output end of the fourth selector is connected with the input end of the sixth inverter, and the control end of the fourth selector is connected with the first control signal end, namely, the fourth selector is connected with the latch signal; one input end of the fifth selector is connected with the fourth input signal end, the other input end of the fifth selector is connected with the output end of the eighth inverter, the output end of the fifth selector is connected with the input end of the seventh inverter, and the control end of the fifth selector is connected with the first control signal end, namely, the latch signal; one input end of the sixth selector is connected with the output end of the sixth inverter, the other input end of the sixth selector is connected with the output end of the seventh inverter, the output end of the sixth selector is connected with the input end of the fifth inverter, the input end of the eighth inverter and the second output signal end, and the control end of the sixth selector is connected with the second control signal end, namely connected with the excitation signal;
the first selector, the second selector, the third selector, the first inverter, the second inverter, the third inverter and the fourth inverter form an upper delay link;
and the fourth selector, the fifth selector, the sixth selector, the fifth inverter, the sixth inverter, the seventh inverter and the eighth inverter form a lower delay chain.
3. The APUF circuit and method of claim 2, wherein the first, second, third, fourth, fifth, and sixth selectors are all two-out selectors having two gating states: gating an external input state and gating a feedback signal state;
in the APUF mode, the latch signal controls the first selector in an upper delay link, the second selector and the fourth selector and the fifth selector in a lower delay link to be in a gated external input state; the excitation signal simultaneously controls the third selector and the sixth selector to realize that one input signal of the third selector is selected as an output signal of a first output signal end and one input signal of the sixth selector is selected as an output signal of a second output signal end, namely, the cross or parallel transmission of signals is realized;
in the reliability detection mode, the latch signal controls the first selector in the upper delay link, the second selector and the fourth selector and the fifth selector in the lower delay link to be in the gating feedback signal state, so that the internal signal is latched in the current basic delay unit and cannot be transmitted to the next basic delay unit, the function of recording the circuit state at the moment can be realized, and the delay difference between the upper delay link and the lower delay link under the current excitation signal is further judged.
4. The APUF circuit and method of operation as claimed in claim 2, wherein the APUF circuit and method of operation,
in the APUF mode, only the second inverter and the third inverter in the upper delay link are in working states, and only the sixth inverter and the seventh inverter in the lower delay link are in working states;
under the reliability detection mode, a first inverter and a second inverter in the upper delay link jointly form a state latch circuit, a third inverter and a fourth inverter jointly form the state latch circuit, a fifth inverter and a sixth inverter in the lower delay link jointly form the state latch circuit, and a seventh inverter and an eighth inverter jointly form the state latch circuit.
5. The APUF circuit and operation method according to claim 1, wherein the latch signal is 1-bit, so that each stage of basic delay cells share 1-bit latch signal; the excitation signal is an n-bit signal, so that the basic delay units at all stages use 1-bit signals in the basic delay units as the excitation signal in sequence.
6. The APUF circuit and method of claim 1, wherein in APUF mode, the pulse signal generated by the pulse generator is a rising edge signal; in the reliability detection mode, the pulse signal precisely generated by the pulse generator is a hold signal with a length t 1.
7. An operation method of an APUF circuit with detectable reliability is characterized by comprising an operation method in an APUF mode and an operation method in a reliability detection mode;
the working method under the APUF mode comprises the following specific steps:
step A1: configuring an excitation signal;
step A2: the latch signal gates the external input;
step A3: the pulse generator generates a rising edge signal;
step A4: reading an output signal of the D trigger;
the working method under the reliability detection mode comprises the following specific steps:
step B1: configuring an excitation signal Challenge;
step B2: latching signal Lock strobes external input;
step B3: the pulse generator generates a hold signal of length t 1;
step B4: the latch signal Lock gates the feedback signal, namely, the feedback signal enters a latch state;
step B5: reading the latched values of the upper delay link and the lower delay link in each level of basic delay units;
step B6: the delay difference Δ t between the upper delay link and the lower delay link is calculated.
8. The method of claim 7, wherein the APUF circuit is configured to operate with a detectable reliability,
calculating the delay difference Δ t between the upper delay link and the lower delay link, which specifically includes the following four cases:
(1) the pull-up signals are transmitted in the upper delay link and the lower delay link, the delay difference is small, and the delay difference delta t of the upper delay link and the lower delay link is the difference value of a rising edge or a falling edge;
(2) the pull-up signals are transmitted in the upper delay link and the lower delay link, the delay difference is large, and the delay difference delta t of the upper delay link and the lower delay link is the difference of the falling edge;
(3) the pull-up signal in the upper delay link is transmitted completely, the pull-up signal is still transmitted in the lower delay link, and the delay difference delta t of the upper delay link and the lower delay link is larger than the length of the holding signal generated by the pulse generator;
(4) the pull-up signals in the upper delay link and the lower delay link are latched into the same level of basic delay unit, at the moment, the delay time difference delta t of the upper delay link and the lower delay link cannot be calculated, and the current excitation signal can be judged to be the worst reliability.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010748501.3A CN111865615B (en) | 2020-07-30 | 2020-07-30 | APUF circuit with detectable reliability and working method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010748501.3A CN111865615B (en) | 2020-07-30 | 2020-07-30 | APUF circuit with detectable reliability and working method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111865615A true CN111865615A (en) | 2020-10-30 |
| CN111865615B CN111865615B (en) | 2022-07-19 |
Family
ID=72946409
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010748501.3A Active CN111865615B (en) | 2020-07-30 | 2020-07-30 | APUF circuit with detectable reliability and working method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111865615B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106919764A (en) * | 2017-03-07 | 2017-07-04 | 合肥工业大学 | The reliability checking method of the ring oscillator physics unclonable function based on FPGA |
| CN107103144A (en) * | 2017-05-08 | 2017-08-29 | 北京化工大学 | The wiring delay deviation quick calibration method of arbitration type PUF based on FPGA |
| CN108768619A (en) * | 2018-06-08 | 2018-11-06 | 中国电子科技集团公司第五十八研究所 | A kind of strong PUF circuits and its working method based on ring oscillator |
| US20190165938A1 (en) * | 2017-11-14 | 2019-05-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for puf generation using variations in transistor threshold voltage and subthreshold leakage current |
| CN110048858A (en) * | 2019-04-30 | 2019-07-23 | 东南大学 | A kind of high-performance APUF circuit structure |
-
2020
- 2020-07-30 CN CN202010748501.3A patent/CN111865615B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106919764A (en) * | 2017-03-07 | 2017-07-04 | 合肥工业大学 | The reliability checking method of the ring oscillator physics unclonable function based on FPGA |
| CN107103144A (en) * | 2017-05-08 | 2017-08-29 | 北京化工大学 | The wiring delay deviation quick calibration method of arbitration type PUF based on FPGA |
| US20190165938A1 (en) * | 2017-11-14 | 2019-05-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for puf generation using variations in transistor threshold voltage and subthreshold leakage current |
| CN108768619A (en) * | 2018-06-08 | 2018-11-06 | 中国电子科技集团公司第五十八研究所 | A kind of strong PUF circuits and its working method based on ring oscillator |
| CN110048858A (en) * | 2019-04-30 | 2019-07-23 | 东南大学 | A kind of high-performance APUF circuit structure |
Non-Patent Citations (1)
| Title |
|---|
| 徐太忠等: "基于纠错码模糊提取器的SRAM-PUF设计方法", 《计算机科学》 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111865615B (en) | 2022-07-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103576082B (en) | Low-power sweep trigger unit | |
| CN104617957B (en) | Asynchronous gradual approaching A/D converter | |
| CN103645794B (en) | Chip and method for achieving sleep mode wake-up through edge detection circuit | |
| CN103299576B (en) | Bit generating apparatus and bit generation method | |
| CN109634089B (en) | Two-stage TDC circuit applied to process uncontrolled detection | |
| CN113297634B (en) | Physical unclonable function hardware circuit based on full spin logic and implementation method | |
| CN104333365A (en) | Three-segment time digital converter (TDC) circuit | |
| CN112667292B (en) | Asynchronous micro-pipeline controller | |
| He et al. | Reliable and efficient PUF‐based cryptographic key generator using bit self‐tests | |
| CN107463236A (en) | A kind of reset detection circuit and reset detection method | |
| CN107017889A (en) | A kind of successive approximation analog-digital converter | |
| CN104502750A (en) | Trigger unit single event upset effect experimental verification circuit | |
| CN111865615B (en) | APUF circuit with detectable reliability and working method | |
| CN114357539A (en) | Frequency-controllable PUF circuit based on ring oscillator | |
| CN103812472A (en) | Trigger resistant to single event transient effect | |
| CN107565936B (en) | Logic implementation device of input clock stabilizing circuit | |
| CN111651403A (en) | Clock tree, hash engine, computing chip, force plate and digital currency mining machine | |
| CN115373633A (en) | True random number generator and true random number generation method | |
| US5574896A (en) | Framing circuit that increases the pulse width of the byte clock signal after the byte clock signal is reset | |
| CN107196658A (en) | Analog-digital converter and data conversion method | |
| CN113497619A (en) | Trigger circuit, control circuit and chip | |
| CN220273668U (en) | Circuit for converting parallel signal into serial signal | |
| Yu-yun et al. | A 0.18 µm pipelined 8B10B encoder for a high-speed SerDes | |
| CN217060350U (en) | Single-particle multi-transient pulse width detection system | |
| CN104217746B (en) | Bias generator of reference storage cell and bias supply method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |