CN111837226A

CN111837226A - Visualization of three-dimensional semiconductor structures

Info

Publication number: CN111837226A
Application number: CN201980016475.0A
Authority: CN
Inventors: A·J·罗森贝格; J·伊洛雷塔; T·G·奇乌拉; A·吉里纽; 徐寅; 徐凯文; J·亨奇; A·贡德; A·韦尔德曼; 列-关·里奇·利; H·舒艾卜
Original assignee: KLA Tencor Corp
Current assignee: KLA Corp
Priority date: 2018-03-05
Filing date: 2019-03-04
Publication date: 2020-10-27
Anticipated expiration: 2039-03-04
Also published as: CN111837226B; JP7553533B2; JP2021516448A; TW201945691A; KR102468979B1; KR20200118905A; JP2023025174A; JP7189959B2; WO2019173170A1; TWI778239B

Abstract

A semiconductor metrology tool inspects a region of a semiconductor wafer. The inspected region includes a plurality of instances of a 3D semiconductor structure periodically arranged in at least one dimension. A computer system generates a model of a respective instance of the 3D semiconductor structure based on measurements collected during the inspection. The computer system renders an image of the model showing the 3D shape of the model and provides the image to a device for display.

Description

Visualization of three-dimensional semiconductor structures

Technical Field

The present invention relates to semiconductor metrology, and more particularly, to generating visualizations showing three-dimensional (3D) properties of semiconductor structures.

Background

Various types of metrology, such as different types of optical metrology and small angle x-ray scattering (SAXS), may be used to characterize three-dimensional semiconductor structures. However, insufficient visualization of the resulting measurements may cause the data to be overlooked or not fully understood. This data can be important for debugging semiconductor manufacturing processes, improving yield and reliability of the processes, or predicting performance of semiconductor devices. Insufficient visualization also makes comparison with reference data, such as data from critical dimension scanning electron microscopy (CD-SEM) and Transmission Electron Microscopy (TEM), difficult.

Disclosure of Invention

Accordingly, there is a need for improved techniques for visualizing 3D semiconductor structures. Examples of such structures include, but are not limited to, memory holes in 3D memory (e.g., 3D flash memory), finfets, and DRAM cells.

In some embodiments, a method of visualizing a semiconductor structure includes: in a semiconductor metrology tool, a region of a semiconductor wafer is inspected. The semiconductor die may include at least one of semiconductor logic circuitry or semiconductor memory circuitry. The inspected region includes a plurality of instances of a 3D semiconductor structure periodically arranged in at least one dimension. The method further comprises: in a computer system including one or more processors and memory storing instructions for execution by the one or more processors, a model of a respective instance of the 3D semiconductor structure is generated based on the inspection. The method further comprises: rendering an image of the model showing a 3D shape of the model in the computer system and providing the image to a device for display.

In some embodiments, a semiconductor inspection system includes a semiconductor metrology tool and a computer system having one or more processors and memory storing one or more programs for execution by the one or more processors. The one or more programs include instructions for performing all or a portion of the above methods. In some embodiments, a non-transitory computer readable storage medium stores one or more programs configured to be executed by a computer system. The one or more programs include instructions for performing all or a portion of the above methods.

Drawings

For a better understanding of the various described embodiments, reference should be made to the following detailed description taken in conjunction with the following drawings.

FIG. 1A shows a graph showing the variation of the CD profile of a memory hole along its depth.

FIG. 1B shows a graph showing the slope of a memory hole along its depth.

Fig. 2 shows a flow diagram of a method of semiconductor structure visualization, according to some embodiments.

Figure 3A shows an image that is an isometric projection of a modeled slice of a 3D semiconductor memory device having a plurality of memory holes, according to some embodiments.

Fig. 3B shows an image that is an isometric projection of modeled portions of two finfets, according to some embodiments.

Fig. 4A-4D show images of modeled memory holes presented from different perspectives, in accordance with some embodiments.

Fig. 5A and 5B show images that are perspective views of respective modeled memory holes, according to some embodiments.

FIG. 6 shows an image including perspective views of modeled memory holes along with cross-sections of the model at various depths, according to some embodiments.

7A-7C show architectural views of respective modeled memory holes, according to some embodiments.

Fig. 8A and 8B show opaque and semi-transparent images of a modeled volume in a semiconductor with memory holes, according to some embodiments.

FIG. 9 shows an image including a bottom surface of a modeled memory hole and a user-selectable cross-section, according to some embodiments.

FIG. 10 is a block diagram of a semiconductor inspection system according to some embodiments.

Like reference numerals designate corresponding parts throughout the drawings and the specification.

Detailed Description

Reference will now be made in detail to the various embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of various described embodiments. However, it will be apparent to one of ordinary skill in the art that the various described embodiments may be practiced without these specific details. In other instances, well-known methods, procedures, components, circuits, and networks have not been described in detail as not to unnecessarily obscure aspects of the embodiments.

Fig. 1A shows a graph 100 showing the variation of the Critical Dimension (CD) profile (e.g., diameter) of a memory hole along its depth. The memory hole extends vertically through a three-dimensional (3D) semiconductor memory structure, such as a 3D flash memory, where the vertical direction (in other figures, the z-axis) corresponds to depth. The CD profile is measured in nanometers (nm). Graph 100 corresponds to a vertical cross-section of a memory hole.

FIG. 1B shows a graph 110 of the slope of a memory hole along its depth. Ideally the slope should be zero so that the graph shows a straight vertical line. In practice, however, the memory holes at any given depth may have an offset relative to the holes at their surfaces. This shift, measured in nanometers, is a slope. The slope at a given depth may be determined by measuring the offset between a specified point on the surface of the memory hole (e.g., the center of the memory hole, a specific point on the circumference of the memory hole, etc.) and the corresponding point at that depth.

The low dimension of

charts

100 and 110, each showing variation of parameters along a single dimension, limits the information conveyed by the charts. Each of the

graphs

100 and 110 provides only a limited indication of the shape of the memory hole. A more robust visualization method that addresses this problem by providing sensing (sense) of the 3D shape of the memory hole or of another semiconductor structure will now be described.

Fig. 2 shows a flow diagram of a method 200 of semiconductor structure visualization, according to some embodiments. The method 200 generates images that show 3D shapes and thus avoid the drawbacks of the diagrams 100 and 110 (fig. 1A and 1B). The method 200 is described with reference to fig. 3A-8 which give examples of images showing 3D shapes of semiconductor structures. (technically, the image shows a model of a semiconductor structure, where the model is generated based on the results of semiconductor metrology, as described below). The steps in method 200 may be combined or separated.

In method 200, a region of a semiconductor wafer is inspected (202) using a semiconductor metrology tool (e.g., metrology tool 1032, FIG. 10). The semiconductor die includes at least one of a semiconductor logic circuit or a semiconductor memory circuit. The circuit may be manufactured only partially at the time of the inspection. The region under inspection includes multiple instances of the 3D semiconductor structure periodically arranged in at least one dimension (e.g., in only one dimension or in two dimensions). Optical metrology or small angle x-ray scattering (SAXS) can be performed (204) to inspect the region. Examples of optical metrology techniques that can be performed include spectral ellipsometry, single wavelength ellipsometry, beam profile reflectance measurement, single wavelength reflectance measurement, angle-resolved reflectance measurement, spectral reflectance measurement, scatterometry, and Raman (Raman) spectroscopy. Examples of SAXS techniques that may be performed include transmissive SAXS, reflective SAXS, and grazing incidence SAXS.

In some embodiments, the 3D semiconductor structure is a memory hole in a 3D memory (e.g., a 3D flash memory), a fin field effect transistor (finFET) or portion thereof, or a Dynamic Random Access Memory (DRAM) cell or portion thereof. The memory holes may be verified when they are empty (e.g., after etching but before filling), filled, or at some intermediate step between etching and completion of filling. Likewise, other structures may be inspected at various steps in their manufacture. The verified area may thus include (206) a periodic arrangement of memory holes in the 3D memory, a periodic arrangement of finfets, or a DRAM cell array. Alternatively, other 3D semiconductor structures may be inspected.

The steps following steps 202, 204, and/or 206 (i.e., step 208, etc.) are performed in a computer system (e.g., the computer system of semiconductor inspection system 1000, fig. 10) communicatively coupled with the metrology tool.

Based on the measurements collected during the inspection step 202, a model of the corresponding instance of the 3D semiconductor structure is generated (208). In some embodiments, the respective instance is or includes a respective memory hole, a respective finFET or portion thereof, or a respective DRAM cell or portion thereof, in accordance with step 206.

In some embodiments, to generate this model, a geometric model (i.e., a parameterized geometric model) of the 3D semiconductor structure having parameterized dimensions is obtained (210). The geometric model may also include information about material properties, and thus is a parameterized geometric/material model. The parameterized geometric model (e.g., geometric/material model) is typically formed in advance prior to the verification step 202. The measurements collected during the verification step 202 are used (212) to determine the value of the parameterized dimension. This determination may be made by performing a regression on the parameters of the geometric model (e.g., the geometric/material model). For example, this determination may be made using a machine learning model that is trained using a training set of measurements (actual and/or simulated) for which corresponding parameter values for a parameterized geometric model (e.g., a geometric/material model) have been determined.

In some other embodiments, to generate such a model, a set of measurements (actual and/or simulated) for different instances of the 3D semiconductor structure is obtained 214. Each group is labeled with a corresponding value for the size. Machine learning is performed using the set and the measurements collected during the verification step 202 to determine (216) a value for the dimension of the respective instance. A parameterized geometric model of the 3D semiconductor structure is not used.

An image of the model is rendered (218) showing the 3D shape of the model. The image may show a portion of the 3D shape of the model, for example, because one or more surfaces and/or sides are obscured or absent, and/or because the image includes a limited number of cross-sections. Alternatively, the image may show the full 3D shape of the model, for example, using augmented reality or virtual reality (AR/VR) or holography. The model and image may be voxelized such that they are built using voxels (volume elements, which are the 3D equivalent of pixels). The image is provided (224) to the device for display. In one example, the image is provided to a display screen (e.g., display 1008, fig. 10) of the computer system performing steps 208-224. In another example, the images are transmitted to a different electronic device (e.g., a client computer or mobile electronic device with a display, an AR/VR viewer, a 3D stereoscopic viewer, a holographic display system, etc.) for display. In yet another example, the image is transmitted to a 3D printer, which can additive-fabricate an object having the shape of the model, thereby displaying the 3D shape of the model.

In some embodiments, the image includes (220) a projection for two-dimensional (2D) display. For example, the projection may be an axonometric projection (e.g., an equiangular projection, a dihedral projection, or an unequal angular projection) showing multiple sides of the model. The dimensions of the projections may thus share a common scale or have different scales. When the projection is to be displayed in 2D, it shows the 3D shape of the model (but not the entire 3D shape according to some embodiments, as some sides and/or surfaces may be obscured by visible sides and/or surfaces).

Fig. 3A shows an image 300, the image 300 being an isometric projection of a modeled slice 304 of a 3D semiconductor memory device (e.g., a 3D flash memory) having a plurality of memory holes 302-1 to 302-7, according to some embodiments. The slice 304 may include multiple layers (e.g., a series of alternating oxides (SiO) through which the memory holes 302 extend vertically₂) And nitride (Si)₃N₄) Layers). Image 300 shows only the 2D top surface of memory holes 302-1, 302-4, and 302-7, but shows cross-sectional views of memory holes 302-2, 302-3, 302-5, and 302-6. The cross-sectional views of memory holes 302-3 and 302-6 show the 3D shape of their back halves relative to the plane through which they have been sliced. Image 300 is thus an example of the image of step 220. The 3D shape of memory holes 302-3 and 302-6 may be shown using contour lines (as in FIG. 3A), shading, coloring, or other suitable graphics techniques for 2D projection of 3D objects. Image 300 is thus an example of the image of step 220.

Fig. 3B shows an image 350 according to some embodiments, the image 350 being an isometric projection of modeled portions of two finfets. The first finFET has a channel 352-1 and the second finFET has a channel 352-2. The channel 352 is separated by a gap 354 separating the two finfets. With respect to memory holes 302-3 and 302-6 of FIG. 3A, the 3D shape of these structures may be shown using contour lines (as in FIG. 3B), shading, coloring, or other suitable graphics techniques. Image 350 is another example of the image of step 220.

As

images

300 and 350 show, the images of steps 218 and 224 may show 3D shapes of multiple instances of semiconductor structures or portions thereof (e.g., multiple instances of memory holes 302 or channels 352).

In some embodiments, the perspective of the image may be changed in response to user input 226. FIG. 4A shows an image 400A of a modeled memory hole presented from a first perspective, according to some embodiments. From the first perspective, image 400A shows a top surface 402 and a front side surface 404 of the memory hole. The 3D shape of the memory hole is shown using outlines (or shading, coloring, etc.): image 400A shows a 3D curvature of anterior surface 404. The bottom surface 406 and backside surface of the memory hole are obscured in this view. In response to receiving the user input 226 specifying a change in perspective, the computer system performing the method 400 renders (218) a

new image

400B, 400C, or 400D from the changed perspective and provides (224) the

new image

400B, 400C, or 400D to the user's device for display. (alternatively, the new image may have been presented and stored before user input 226 was received, and provided in response to user input 226). This process may be performed iteratively to allow a user to view the memory aperture from multiple perspectives (e.g., to view

images

400B, 400C, and/or 400D in sequence). For example, a user may rotate a view of a memory hole in a specified direction. Image 400B is a side view showing the 3D curvature of the anterior surface 404 but not showing the top surface 402, the bottom surface 406, or the posterior surface. Image 400C is a bottom view showing only the bottom surface 406. Image 400D is a top view showing only the top surface 402.

Images

400C and 400D are not examples of the image of step 218, as they do not show a 3D shape, but if they are rotated slightly to show a side surface or portion of a side surface, they will show a 3D shape.

In some embodiments, instead of changing the perspective from which the image is presented, the model itself may be changed in response to the user input 226 (e.g., so that the arrow labeled "user input 226" points back to step 208 instead of step 218), e.g., the user input 226 may specify a change in one or more dimensions (e.g., distance) or angles of the model of the respective example. The model is updated in response to user input 226 such that the model no longer corresponds to the measurements collected during the verification of step 202. The image of the updated model is then presented and sent to the user's device for display. This modification allows the user to explore how much margin the semiconductor structure has before reaching the point of failure (e.g., before the adjacent conductive structures are shorted). The image of the updated model may be annotated to indicate update(s) of the model (e.g., to indicate a change in size, a change in one or more angles, etc.). The annotation may be user-actuated (e.g., indicating a specified distance or angle according to the user input 226).

Fig. 5A shows an image 500, the image 500 being a perspective view of a modeled memory hole, according to some embodiments. Like image 400A (fig. 4A), image 500 shows 3D curvature of the top surface 502 and the front side surface 504 of the memory hole. But image 500 also shows a slope, while the memory holes of image 400A have no slope (i.e., the slope is substantially zero, such that the memory holes are substantially straight in the vertical direction). The top portion of the memory well in image 500 slopes downward at an oblique angle to a bend 506 in the middle portion of the memory well (where the memory well bends toward the vertical plane). The bottom portion of the reservoir well extends downward without significant slope. If the slope is defined as an offset from the top surface (as discussed with respect to fig. 1B), the slope of the bottom portion below the bend 506 is substantially constant.

FIG. 5B shows an image 550, according to some embodiments, the image 550 being a perspective view of a different modeled memory hole. As with images 400A (FIG. 4A) and 500 (FIG. 5), image 550 shows 3D curvature of the top surface 552 and the frontside surface 554 of the memory hole. Image 550 shows that top surface 552 is elliptical. The shape of the front side surface 554 implies that the memory hole maintains this oval shape as it extends downward.

In some embodiments, in which the respective instances of the 3D semiconductor structures are respective memory holes, the images show an elliptical shape of the memory holes for a plurality of cross-sections (e.g., horizontal cross-sections) of the respective memory holes. The image may also show, for a plurality of cross-sections, the helicity of the respective memory hole and/or the inclination of the memory hole. Helicity indicates the change in orientation of the elliptical shape and may be defined as the degree of rotation (e.g., as measured in degrees or radians) of the long (or equivalently, short) axis of the ellipse relative to the top surface. For example, FIG. 6 shows an image 600 that includes a perspective view (here, a side view 602) of a modeled memory hole along with cross-sections 606-1 to 606-6 of the memory hole at various depths, according to some embodiments. The arrows 604 between the side view 602 and the respective cross-sections 606 indicate the depth for the respective cross-sections 606. Cross-section 606 shows the dimensions (e.g., CD) and elliptical shape of the memory hole at various depths. Cross-section 606 also shows the helicity of the memory hole at various depths: the ellipse of cross-section 606 rotates with increasing depth. Although the memory hole in fig. 6 has a substantially zero slope, cross-section 606 may also show a slope (if it exists), for example, by having varying positions within its surrounding rectangle to demonstrate an offset relative to the top surface.

In some embodiments, the image highlights or otherwise indicates a deviation from the elliptical shape for the plurality of cross-sections. For example, the particular cross-section 606 may not be exactly elliptical. Portions of the cross-section that deviate from the ellipse (e.g., fall outside the ellipse or fail to reach the edge of the ellipse) may be highlighted (e.g., shown with a particular color, shading, or fill pattern). More generally, the image may highlight or otherwise indicate a deviation of the 3D shape or a portion thereof (e.g., a cross-section) from a nominal shape. Memory holes and ellipses are only examples of corresponding structures and nominal shapes for which such deviations may be shown. Other examples are possible.

In some embodiments, the cross-section may be shown such that it appears to be arranged along an axis (e.g., a z-axis corresponding to depth), where the axis appears to intersect the page at an inclination (e.g., at an oblique angle). In such an arrangement, the cross-sections may partially overlap (e.g., with the respective cross-sections partially obscuring the continuous cross-section).

In some embodiments, the image includes an architectural view of the model in which multiple cross-sections are connected by contour lines (e.g., the contour lines intersect corresponding points on the circumference of each cross-section). The architecture view shows the 3D shape of the model (but not the entire 3D shape, due to the limited number of cross-sections and contours), but will be displayed in 2D. Fig. 7A-

7C show images

700, 720, and 740 of architectural views of modeled memory holes, according to some embodiments.

In the image 700, the cross-sections 702-1 through 702-5 are connected by contour lines 704-1 and 704-2. The cross-section 702 is elliptical, as shown by the major and minor axes for the ellipse of the cross-section 702. The elliptical shape of the memory hole, as quantified by its ellipticity (e.g., the ratio of the lengths of the major and minor axes), remains constant as a function of depth, as does the memory hole CD and therefore its size. The reservoir wells are not helical: the ellipse of cross-section 702 does not rotate with depth. However, the memory holes do have a slope that varies with depth (as shown by the curvature of contour lines 704-1 and 704-2).

In image 720, cross-sections 722-1 through 722-5 are connected by contour lines 724-1 and 724-2. The elliptical shape and hence ellipticity varies with depth, with the minor axis increasing in length and becoming the major axis. The size of the memory hole, and thus its CD, varies significantly with depth. However, the ellipse does not rotate, indicating no helicity.

In image 740, cross-sections 742-1 to 742-4 are connected by contour lines 744-1 and 744-2. While the ellipticity and CD of cross-section 742 remain constant, the memory holes show helicity: the ellipse of cross-section 742 rotates with increasing depth. The axis of the ellipse can be seen to rotate.

The use of multiple cross-sections may thus provide extensive information about the 3D shape, as shown in fig. 6 and 7A-7C.

Fig. 8A and 8B show

images

800 and 810 of a modeled volume 802 in a semiconductor, according to some embodiments. Volume 802 includes memory holes 804-1, 804-2, and 804-3, which may be part of a periodic 2D arrangement of memory holes. In the image 800, the volume 802 is shown as opaque. Image 800 shows a top surface of memory hole 804-1, a portion of a top surface of memory hole 804-2, and a portion of a top surface of memory hole 804-3 along with a cross-sectional vertical profile of memory hole 804-3. In image 810, volume 802 is translucent and the 3D shape of all three memory holes 804-1, 804-2, and 804-3 is visible. Thus, both

images

800 and 810 show at least a portion of a 3D shape of at least one semiconductor structure (as modeled in step 208), but image 810 shows significantly more 3D information than image 800.

In some embodiments, the image includes at least one of a top surface or a bottom surface of the modeled respective instance of the 3D semiconductor structure and also includes a user-selectable cross-section (e.g., a horizontal cross-section perpendicular to a vertical z-axis) of the modeled respective instance of the 3D semiconductor structure between the top surface and the bottom surface. For example, FIG. 9 shows an image 900 including a bottom surface 902 of a modeled memory hole and a user-selectable cross-section 904, according to some embodiments. The user selectable cross section 904 may be translucent. The vertical position of the user-selectable cross-section 904 may change based on the user input 226 (e.g., in response to the user input 226 specifying a new vertical position, the computer performing method 200 repeats

steps

218 and 220 to present and provide a new image in which the user-selectable cross-section 904 is in the newly specified vertical position). By providing multiple cross-sections (i.e., top and/or bottom surfaces and user-selectable cross-sections), the image shows the 3D shape of the model (but not the entire 3D shape due to the limited number of cross-sections and contours), but the image can be used for a 2D display. In some embodiments, the image includes a plurality of user-selectable cross-sections, one or more (e.g., all) of which may be translucent.

In some embodiments, the image is or includes (222) an AR/VR image or a 3D stereoscopic image. The device to which the image is provided in step 224 may thus be an AR/VR viewing device (e.g., AR/VR goggles; AR glasses) or a 3D stereoscopic viewer.

For example, the AR/VR image is a first AR/VR image of the model rendered from a first perspective. The method 200 further includes, after sending the first AR/VR image to an AR/VR viewing device for display, receiving a user input 226 requesting a change in perspective. In response to the user input, step 222 is repeated such that a second AR/VR image of the model is presented from a second perspective. Each step 224 sends the second AR/VR image to an AR/VR viewing device for display. In this way, the user can effectively move around the image in the AR/VR.

In another example, the AR/VR image is a first AR/VR image of the model having an appearance corresponding to values of parameters of the model as determined based on measurements collected during the inspection of step 202. The method 200 further includes, after sending the first AR/VR image to an AR/VR viewing device for display, receiving a user input 226 requesting a change in the value of the parameter. In response to the user input, the values of the parameters for the model are changed and a second AR/VR image of the model having an appearance corresponding to the changed values is presented per step 222. Each step 224 sends the second AR/VR image to an AR/VR viewing device for display. In this way, a user may explore potential changes in the 3D shape of the semiconductor structure (e.g., explore how much margin the semiconductor structure has before reaching the failure point).

In some embodiments, the image generated according to method 200 exhibits (e.g., highlights) the uncertainty associated with the 3D shape of its model according to step 218. For example, to the extent there is uncertainty in the CD, the uncertainty region at the side of the example correlated modeled semiconductor structure (e.g., along the wall of the memory hole) may be different from the color, shading, or fill pattern representation of the rest of the example correlated modeled semiconductor structure, indicating uncertainty in the precise location of the side. Blurring (e.g., blurring of edges) or points may be used to indicate uncertainty. An animation may be shown in which the 3D shape is shown to change within a range of possibilities according to the uncertainty (e.g., the position of the edge changes). Other examples are possible.

The indicators described above, such as slope, ellipticity, deviation from a nominal shape (e.g., elliptical shape), and helicity, are merely examples of indicators that may be shown in an image generated using method 200. Other indicators (e.g., derivative indicators, indicators generated using fourier transforms, etc.) may also or alternatively be shown.

In some embodiments, the image generated according to method 200 includes an animation that continuously shows successive portions of the 3D shape. For example, the animation may continuously show continuous cross-sections (e.g., cross-sections of increasing or decreasing depth). In another example, the animation shows a rotation of the 3D shape, with successive portions rotating in and out of view.

In some embodiments, the data for the model may be superimposed on the image of the model such that the image provided to the user's device in step 224 includes the superimposed data. The data may include numbers that specify values for one or more parameters/metrics of the model. The data may include vectors specifying electric fields or strains. Other examples are possible.

The images shown in fig. 3A-8 are merely examples of 3D visualization techniques that may be used in method 200. Other examples are possible. In some embodiments, the image generated by the method 200 is used to predict the performance of a semiconductor device. In some embodiments, the image generated by the method 200 is for comparison to a reference image (e.g., a CD-SEM or TEM image). In some embodiments, the image generated by the method 200 is used to identify process or design variations.

Fig. 10 is a block diagram of a semiconductor inspection system 1000 according to some embodiments. The semiconductor inspection system 1000 includes a semiconductor metrology tool 1032 and a computer system having one or more processors 1002 (e.g., CPUs and/or GPUs), an optional user interface 1006, a memory 1010, and one or more communication buses 1004 interconnecting these components. The computer system may be communicatively coupled with a metrology tool 1032 over one or more networks 1030. The computer system may further include one or more network interfaces (wired and/or wireless, not shown) for communicating with the metrology tool 1032 and/or a remote computer system. In some embodiments, the metrology tool 1032 performs optical metrology and/or SAXS.

The user interface 1010 may include the display 1008 and/or one or more input devices (e.g., a keyboard, a mouse, a touch-sensitive surface of the display 1008, etc.). The display 1008 may display an image of the method 200 according to some embodiments.

The memory 1010 includes volatile and/or nonvolatile memory. Memory 1010 (e.g., non-volatile memory within memory 1010) includes non-transitory computer-readable storage media. Memory 1010 optionally includes one or more storage devices remotely located from processor 1002 and/or a non-transitory computer-readable storage medium removably insertable into a computer system. In some embodiments, memory 1010 (e.g., a non-transitory computer-readable storage medium of memory 1010) stores the following modules and data, or a subset or superset thereof: including an operating system 1012 for handling various basic system services and programs for performing hardware dependent tasks, a model generation module 1014, a model update module 1016, an image presentation module 1018, an image transmission module 1020, and a database 1022 of measurements collected from a metrology tool 1032.

The memory 1010 (e.g., a non-transitory computer-readable storage medium of the memory 1010) thus includes instructions for performing the method 200 (fig. 2) in conjunction with the metrology tool 1032. Each of the modules stored in memory 1010 corresponds to a set of instructions for performing one or more functions described herein. The separation module need not be implemented as a separation software program. Modules and various subsets of modules may be combined or otherwise rearranged. In some embodiments, memory 1010 stores a subset or superset of the modules and/or data structures identified above.

Fig. 10 is intended more as a functional description of the various features that may be present in a semiconductor inspection system rather than as a structural schematic. For example, the functionality of a computer system in the semiconductor inspection system 1000 may be divided among multiple devices. A portion of the modules stored in the memory 1010 may alternatively be stored in one or more other computer systems communicatively coupled with the computer system of the semiconductor inspection system 1000 over one or more networks.

The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the scope of the claims to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles underlying the claims and their practical application to thereby enable others skilled in the art to best utilize the embodiments with various modifications as are suited to the particular use contemplated.

Claims

1. A method of semiconductor structure visualization, comprising:

in a semiconductor metrology tool:

inspecting, on a semiconductor wafer comprising at least one of semiconductor logic circuits or semiconductor memory circuits, regions of the semiconductor wafer containing multiple instances of one three-dimensional, 3D, semiconductor structure periodically arranged in at least one dimension; and

in a computer system comprising one or more processors and memory storing instructions executed by the one or more processors:

generating a model of a respective instance of the 3D semiconductor structure based on the inspection;

presenting an image of the model showing a 3D shape of the model; and

the image is provided to a device for display.

2. The method of claim 1, wherein the image comprises a projection of the model to be displayed in two dimensions.

3. The method of claim 1, wherein the image comprises an architectural view of the model in which a plurality of cross-sections are connected by contour lines, wherein the architectural view is to be displayed in two dimensions.

4. The method of claim 1, wherein the image comprises:

at least one of a top surface or a bottom surface of the respective instance of the 3D semiconductor structure; and

a user-selectable semi-transparent cross-section of the respective instance of the 3D semiconductor structure between the top surface and the bottom surface.

5. The method of claim 1, wherein the image shows an uncertainty for the 3D shape in the model.

6. The method of claim 1, wherein the image indicates a deviation of the 3D shape or a cross-section of the 3D shape from a nominal shape.

7. The method of claim 1, wherein the image comprises an animation that continuously shows successive portions of the 3D shape.

8. The method of claim 1, wherein:

presenting the image comprises presenting an augmented reality or virtual reality AR/VR image; and is

Providing the image includes sending the AR/VR image to an AR/VR viewing device for display.

9. The method of claim 8, wherein the AR/VR image is a first AR/VR image of the model presented from a first perspective, the method further comprising, after sending the first AR/VR image to the AR/VR viewing device for display:

receiving a user input requesting a change in a perspective;

presenting, in response to the user input, a second AR/VR image of the model from a second perspective; and

sending the second AR/VR image to the AR/VR viewing device for display.

10. The method of claim 8, wherein the AR/VR image is a first AR/VR image of the model having an appearance corresponding to values of parameters of the model as determined based on measurements collected during the inspection, the method further comprising, after sending the first AR/VR image to the AR/VR viewing device for display:

receiving a user input requesting a change in the value of the parameter;

changing the values for the parameters of the model in response to the user input;

presenting a second AR/VR image of the model having an appearance corresponding to the change value; and

sending the second AR/VR image to the AR/VR viewing device for display.

11. The method of claim 1, wherein:

the image is a 3D stereoscopic image; and is

Providing the image includes sending the image to a 3D stereoscopic viewer.

12. The method of claim 1, wherein:

the plurality of examples of the 3D semiconductor structure include a periodic arrangement of memory holes in a 3D memory; and is

The respective examples of the 3D semiconductor structures include respective memory holes.

13. The method of claim 12, wherein the image shows an elliptical shape of the memory hole for a plurality of cross-sections of the respective memory hole.

14. The method of claim 13, wherein the image shows a helicity of the respective memory holes for the plurality of cross-sections, wherein the helicity indicates a change in orientation of the elliptical shape.

15. The method of claim 12, wherein the image indicates a deviation from an elliptical shape for the plurality of cross-sections.

16. The method of claim 12, wherein the image shows a slope of the respective memory hole.

17. The method of claim 1, wherein:

the plurality of instances of the 3D semiconductor structure include a periodic arrangement of finFETs; and is

The respective instance of the 3D semiconductor structure includes a respective finFET or a portion of a respective finFET.

18. The method of claim 1, wherein:

the multiple instances of the 3D semiconductor structure include an array of DRAM cells; and is

The respective example of the 3D semiconductor structure includes a respective DRAM cell or a portion of a respective DRAM cell.

19. The method of claim 1, wherein generating the model of the respective instance of the 3D semiconductor structure comprises:

obtaining a geometric model of the 3D semiconductor structure having parameterized dimensions; and

using measurements collected during the inspection to determine a value of the parameterized dimension.

20. The method of claim 1, wherein generating the model of the respective instance of the 3D semiconductor structure comprises:

obtaining sets of measurements for different instances of the 3D semiconductor structure, the sets being labeled with respective values of dimensions; and

performing machine learning using the set and measurements collected during the inspection to determine a value for the dimension of the respective instance,

wherein the generating is performed without using a parameterized geometric model of the 3D semiconductor structure.

21. The method of claim 1, wherein inspecting the region of the semiconductor wafer comprises performing an optical metrology technique selected from the group consisting of: spectroscopic ellipsometry, single wavelength ellipsometry, beam profile reflectometry, single wavelength reflectometry, angle resolved reflectometry, spectroscopic reflectometry, scatterometry, and raman spectroscopy.

22. The method of claim 1, wherein inspecting the region of the semiconductor wafer comprises performing small angle x-ray scattering.

23. A semiconductor inspection system, comprising:

a semiconductor metrology tool;

one or more processors; and

memory storing one or more programs for execution by the one or more processors, the one or more programs comprising instructions for:

generating a model of a respective instance of a three-dimensional, 3D, semiconductor structure based on inspection of a region of a semiconductor wafer containing multiple instances of the 3D semiconductor structure by the semiconductor metrology tool;

presenting an image of the model showing a 3D shape of the model; and

the image is provided to a device for display.

24. A non-transitory computer-readable storage medium storing one or more programs for execution by one or more processors of a computer system, the one or more programs including instructions for:

generating a model of a respective instance of a three-dimensional, 3D, semiconductor structure based on inspection of a region of a semiconductor wafer containing multiple instances of the 3D semiconductor structure by a semiconductor metrology tool;

presenting an image of the model showing a 3D shape of the model; and

the image is provided to a device for display.