WO2019173170A1 - Visualization of three-dimensional semiconductor structures - Google Patents

Visualization of three-dimensional semiconductor structures Download PDF

Info

Publication number
WO2019173170A1
WO2019173170A1 PCT/US2019/020470 US2019020470W WO2019173170A1 WO 2019173170 A1 WO2019173170 A1 WO 2019173170A1 US 2019020470 W US2019020470 W US 2019020470W WO 2019173170 A1 WO2019173170 A1 WO 2019173170A1
Authority
WO
WIPO (PCT)
Prior art keywords
image
model
semiconductor
semiconductor structure
memory
Prior art date
Application number
PCT/US2019/020470
Other languages
French (fr)
Inventor
Aaron J. ROSENBERG
Jonathan Iloreta
Thaddeus Gerard DZIURA
Antonio GELLINEAU
Yin Xu
Kaiwen XU
John Hench
Abhi GUNDE
Andrei Veldman
Lie-Quan Rich LEE
Houssam Chouaib
Original Assignee
Kla-Tencor Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US16/283,690 external-priority patent/US10794839B2/en
Application filed by Kla-Tencor Corporation filed Critical Kla-Tencor Corporation
Priority to CN201980016475.0A priority Critical patent/CN111837226B/en
Priority to KR1020207028527A priority patent/KR102468979B1/en
Priority to JP2020546171A priority patent/JP7189959B2/en
Publication of WO2019173170A1 publication Critical patent/WO2019173170A1/en
Priority to JP2022193365A priority patent/JP2023025174A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B11/00—Measuring arrangements characterised by the use of optical techniques
    • G01B11/24—Measuring arrangements characterised by the use of optical techniques for measuring contours or curvatures
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B15/00—Measuring arrangements characterised by the use of electromagnetic waves or particle radiation, e.g. by the use of microwaves, X-rays, gamma rays or electrons
    • G01B15/04—Measuring arrangements characterised by the use of electromagnetic waves or particle radiation, e.g. by the use of microwaves, X-rays, gamma rays or electrons for measuring contours or curvatures
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B21/00—Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant
    • G01B21/20—Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant for measuring contours or curvatures, e.g. determining profile
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N23/00—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00
    • G01N23/20—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by using diffraction of the radiation by the materials, e.g. for investigating crystal structure; by using scattering of the radiation by the materials, e.g. for investigating non-crystalline materials; by using reflection of the radiation by the materials
    • G01N23/201—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by using diffraction of the radiation by the materials, e.g. for investigating crystal structure; by using scattering of the radiation by the materials, e.g. for investigating non-crystalline materials; by using reflection of the radiation by the materials by measuring small-angle scattering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B2210/00—Aspects not specifically covered by any group under G01B, e.g. of wheel alignment, caliper-like sensors
    • G01B2210/56—Measuring geometric parameters of semiconductor structures, e.g. profile, critical dimensions or trench depth

Definitions

  • This disclosure relates to semiconductor metrology, and more specifically to generating visualizations that show the three-dimensional (3D) nature of semiconductor structures.
  • Three-dimensional semiconductor structures may be characterized using various types of metrology, such as different types of optical metrology and small-angle x-ray scattering (SAXS).
  • SAXS small-angle x-ray scattering
  • Inadequate visualization of the resulting measurements may cause data to be overlooked or not fully appreciated. Such data may be important for debugging a semiconductor manufacturing process, improving yield and reliability for the process, or predicting performance of a semiconductor device.
  • Inadequate visualization also makes comparisons to reference data, such as data from critical-dimension scanning electron microscopy (CD-SEM) and transmission electron microscopy (TEM) difficult.
  • CD-SEM critical-dimension scanning electron microscopy
  • TEM transmission electron microscopy
  • 3D semiconductor structures include, without limitation, memory holes in 3D memories (e.g., 3D flash memories), finFETs, and DRAM ceils.
  • 3D memories e.g., 3D flash memories
  • finFETs finFETs
  • DRAM ceils DRAM ceils
  • a method of semiconductor-structure visualization includes, in a semiconductor metrology tool, inspecting an area of a semiconductor wafer.
  • the semiconductor wafer may include at least one of semiconductor logic circuitry or semiconductor memory circuitry.
  • the inspected area includes a plurality of instances of a 3D semiconductor structure arranged periodically in at least one dimension.
  • the method also includes, m a computer system comprising one or more processors and memory storing instructions for execution by the one or more processors, generating a model of a respective instance of the 3D semiconductor structure based on the inspecting.
  • the method further includes, in the computer
  • a semiconductor-inspection system includes a
  • a semiconductor metrology tool and a computer system with one or more processors and memory storing one or more programs for execution by the one or more processors.
  • the one or more programs include instructions for performing all or a portion of the abo ve method.
  • a non-transitory computer-readable storage medium stores one or more programs configured for execution by a computer system.
  • the one or more programs include instructions for performing all or a portion of the above method.
  • Figures 1A shows a graph that displays variation of the CD profile of a memory hole along its depth.
  • Figure I B shows a graph that displays the tilt of a memory hole along its depth
  • Figure 2 shows a fl owchart of a method of semiconductor-structure visualization in accordance with some embodiments.
  • Figure 3 A shows an image that is an isometric projection of a modeled slice of a
  • 3D semiconductor memory device with a plurality of memory holes in accordance with some embodiments.
  • Figure 3B shows an image that is an isometric projection of modeled portions of two finFETs in accordance with some embodiments.
  • Figures 4A-4D show images of a modeled memory hole, rendered from different perspectives in accordance with some embodiments.
  • Figures 5A and 5B show images that are perspective views of respective modeled memory holes in accordance with some embodiments.
  • Figure 6 shows an image that includes a perspective view of a modeled memory hole along with cross-sections of the model at various depths, in accordance with some embodiments.
  • Figures 7A-7C show' skeleton views of respective modeled memory holes in accordance with some embodiments.
  • Figures 8A and 8B show opaque and translucent images of a modeled volume in a semiconductor with memory holes in accordance with some embodiments.
  • Figure 9 shows an image that includes a bottom surface and a user-selectable cross-section of a modeled memory hole in accordance with some embodiments.
  • Figure 10 is a block diagram of a semiconductor-inspection system in accordance with some embodiments.
  • Figure 1 A shows a graph 100 that displays variation of the critical-dimension
  • CD profile (e.g., the diameter) of a memory hole along its depth.
  • the memory hole extends vertically through a three-dimensional (3D) semiconductor memory structure (e.g., 3D flash memory), with the vertical direction (in other figures, the z-axis) corresponding to depth.
  • the CD profile is measured in nanometers (nm).
  • the graph 100 corresponds to a vertical cross- section of the memory hole.
  • Figure IB shows a graph 110 that displays the tilt of a memory hole along its depth. Ideally the tilt should be zero, such that the graph shows a straight vertical line. In practice, however, the memory hole at any given depth may have an offset with respect to the hole at its surface. Tins offset, measured m nanometers, is the tilt.
  • the tilt at a given depth may be determined by measuring the offset between a specified point on the surface of the memory hole (e.g., its center, a specific point on its circumference, etc.) and a corresponding point at that depth.
  • the low dimensionality of the graphs 100 and 1 10 - each shows variation of a parameter along a single dimension --- limits the information they convey.
  • Each of the graphs 100 and 110 provides only a limited indication of the shape of the memory hole. More robust visualization methods that solve this problem by providing a sense of the 3D shape of the memory hole, or of another semiconductor structure, will now be described.
  • Figure 2 shows a flow-chart of a method 200 of semiconductor-structure visualization in accordance with some embodiments.
  • the method 200 produces images that show 3D shapes and thus avoid the shortcomings of the graphs 100 and 110 ( Figures 1 A and IB).
  • the method 200 is described with reference to Figures 3A-8, which give examples of images that show 3D shapes of semiconductor structures. (Technically, the images show- models of semiconductor structures, wdierein the models are generated based on the results of semiconductor metrology, as described below-.) Steps in the method 200 may be combined or broken out.
  • a semiconductor metrology tool e.g., the metrology tool 1032,
  • Figure 10 is used to inspect (202) an area of a semiconductor wafer.
  • the semiconductor wafer includes at least one of semiconductor logic circuitry or semiconductor memory circuitry.
  • the circuitry may be only partially fabricated at the time of inspection.
  • the area that is inspected includes a plurality of instances of a 3D semiconductor structure arranged periodically in at least one dimension (e.g., in only one dimension or in two dimensions).
  • Optical metrology or small- angle x-ray scattering (SAXS) may be performed (204) to inspect the area.
  • SAXS small- angle x-ray scattering
  • optical- metrology techniques examples include spectroscopic ellipsometry, single- wavelength ellipsometry, beam-profile ellipsometry-, beam-profile reflectometry, single- wavelength reflectometry, angle-resolved reflectometry-, spectroscopic reflectometry, scatterometry, and Raman spectroscopy.
  • SAXS techniques examples include transmissive SAXS, reflective SAXS, and grazing incidence SAXS
  • the 3D semiconductor structure is a memory hole in a 3D memory (e.g., 3D flash memory), a fin field-effect transistor (finFET) or portion thereof, or a dynamic random-access memor (DRAM) ceil or portion thereof
  • a memory hole may be inspected when it is empty (e.g., after etch but before fill), filled, or at some intermediate step between etch and complete fill.
  • other structures may be inspected at various steps in their fabrication processes.
  • the inspected area therefore may include (206) a periodic arrangement of memory holes m a 3D memory, a periodic arrangement of finFETs, or an array of DRAM cells.
  • other 3D semiconductor structures may be inspected.
  • steps 202, 204, and/or 206 are performed in a computer system communicatively coupled with the metrology tool (e.g., the computer system of the semiconductor-inspection system 1000, Figure 10).
  • the metrology tool e.g., the computer system of the semiconductor-inspection system 1000, Figure 10.
  • a model of a respective instance of the 3D semiconductor structure is generated (208).
  • the respective instance is or includes a respective memory hole, a respective finFET or portion thereof, or a respective DRAM cell or portion thereof, in accordance with step 206.
  • a geometric model of the 3D semiconductor structure with parameterized dimensions is obtained (210).
  • the geometric model may also include information about material properties, and thus be a parameterized geometric/material model.
  • the parameterized geometric model e.g., geometric/material model
  • the parameterized geometric model is typically created in advance, before the inspection step 202. Measurements collected during the inspection step 202 are used (212) to determine values of the parameterized dimensions. This determination may be made by performing regression on the parameters of the geometric model (e.g., geometric/material model). For example, this determination may be made using a machine-learning model trained using training sets of measurements, actual and/or simulated, for which corresponding parameter values for the parameterized geometric model (e.g., geometric/material model) have been determined.
  • sets of measurements for varying instances of the 3D semiconductor structure are obtained (214). Each set is labeled with respective values of dimensions. Machine learning is performed, using the set and the measurements collected during the inspection step 202, to determine (216) values of the dimensions for the respective instance. A parameterized geometric model of the 3D semiconductor structure is not used.
  • An image of the model is rendered (218) that show's a 3D shape of the model.
  • the image may show a partial 3D shape of the model, for example because one or more surfaces and/or sides are obscured or absent, and/or because the image includes a limited number of cross-sections.
  • the image may show' the full 3D shape of the model, for example using augmented reality or virtual reality (AR/VR) or holography .
  • the model and image may be voxelated, such that they are built up using voxels (volume elements, w'hich are the 3D equivalent of pixels).
  • the image is provided (224) to a device for display.
  • the image is provided to a display screen (e.g., display 1008, Figure 10) of the computer system that performs steps 208-224.
  • the image is transmitted to a different electronic device (e.g., a client computer or mobile electronic device with a display, an AR/VR viewer, a 3D stereoscopic viewer, a holographic display system, etc.) for display.
  • a different electronic device e.g., a client computer or mobile electronic device with a display, an AR/VR viewer, a 3D stereoscopic viewer, a holographic display system, etc.
  • the image is transmitted to a 3D printer, which may additively manufacture an object having the shape of the model, thereby displaying the 3D shape of the model.
  • the image includes (220) a projection for two-dimensional
  • the projection may be an axonometric projection (e.g., an isometric projection, dimetric projection, or trimetric projection) showing multiple sides of the model.
  • the dimensions of the projection thus may share a common scale or have different scales.
  • the projection is to be displayed in 2D, it shows a 3D shape of the model (although not the entire 3D shape in accordance with some embodiments, because some sides and/or surfaces may be obscured by the visible sides and/or surfaces).
  • Figure 3 A show's an image 300 that is an isometric projection of a modeled slice
  • the slice 304 may comprise multiple layers (e.g., a series of alternating oxide (Sx0 2 ) and nitride (S1 3 N 4 ) layers) through which the memory holes 302 extend vertically.
  • the image 300 only show's the 2D top surfaces of memory holes 302-1, 302-4, and 302-7, but shows cut-away view's of memory holes 302-2, 302-3, 302-5, and 302-6
  • the cut-away views of the memory holes 302-3 and 302-6 show the 3D shapes of their back halves with respect to the plane through which they have been sliced.
  • the image 300 is thus an example of the image of step 220.
  • the 3D shapes of the memory holes 302-3 and 302-6 may be shown using contour lines (as in Figure 3A), shading, coloring, or other appropriate graphical techniques for 2D projections of 3D objects.
  • the image 300 is thus an example of the image of step 220.
  • Figure 3B shows an image 350 that is an isometric projection of modeled portions of two finFETs in accordance with some embodiments.
  • the first fxnFET has a channel 352-1 and the second fmFET has a channel 352-2.
  • the channels 352 are separated by a gap 354 that isolates the two finFETs.
  • the 3D shapes of these structures may be shown using contour lines (as in Figure 3B), shading, coloring, or other appropriate graphical techniques.
  • the image 350 is another example of the image of step 220
  • 3D shape of multiple instances of a semiconductor structure or portions thereof e.g., multiple instances of memory holes 302 or channels 352).
  • the perspective of the image may be varied in response to user input 226.
  • Figure 4A shows an image 400A of a modeled memory' hole, rendered from a first perspective in accordance with some embodiments. From the first perspective, the image 400A show's the top surface 402 and front-side surface 404 of the memory hole. The use of contour lines (or shading, coloring, etc.) shows a 3D shape of the memory hole: the image 400A shows the 3D curvature of the front-side surface 404. The bottom surface 406 and back-side surface of the memory hole are obscured in this perspective.
  • the computer system performing the method 400 renders (218) a new image 400B, 400C, or 400D from the changed perspective and provides (224) the new' image 400B, 400C, or 400D to the user’s device for display.
  • the new image may have been rendered and stored before the user input 226 is received, and is provided in response to the user input 226)
  • This process may be performed iteratively to allow the user to view the memory hole from multiple perspectives (e.g., to view the images 400B, 400C, and/or 400D in turn). For example, the user may rotate the view of the memory hole in specified directions.
  • the image 400B is a side view that shows the 3D curvature of the front-side surface 404 but does not show top surface 402, bottom surface 406, or back-side surface.
  • the image 400C is a bottom view that shows only the bottom surface 406.
  • the image 400D is a top view that shows only the top surface 402.
  • the images 400C and 400D are not examples of the image of step 218, because they do not show' a 3D shape, but they would be if rotated slightly to show a side surface or portion thereof.
  • the model itself may be varied in response to user input 226 (e.g., such that the arrow- labeled with“user input 226” points back to step 208 instead of step 218).
  • the user input 226 may specify changes to one or more dimensions (e.g., distances) or angles of the model of the respective instance.
  • the model is updated in response to the user input 226, such that it no longer corresponds to the measurements collected during the inspection of step 202.
  • An image of the updated model is then rendered and sent to the user’s device for display. This modification allows the user to explore how' much margin the semiconductor structure has before reaching a point of failure (e.g., before adjacent conductive structures short out).
  • the image of the updated model may be annotated to indicate the update(s) to the model (e.g., to indicate the dimensional changes, changes to one or more angles, etc.).
  • Annotations may be user-driven (e.g., indicating specified distances or angles, in accordance with the user input 226).
  • Figure 5A show's an image 500 that is a perspective view of a modeled memory- hole in accordance with some embodiments. Like the image 400A ( Figure 4A), the image 500 shows a top surface 502 and the 3D curvature of a front-side surface 504 of the memory' hole.
  • the image 500 also show-s tilt, w-hereas the memory hole of the image 400 A lacked tilt (i.e. , the tilt was substantially zero, such that the memory hole was substantially straight in the vertical direction).
  • a top portion of the memory hole in the image 500 slants downward at an oblique angle, until a bend 506 in a middle porti on of the memory hole, where the memory hole bends toward the vertical.
  • a bottom portion of the memory hole than extends downward without substantial slant. If tilt is defined as an offset with respect to the top surface, as discussed for Figure I B, then the tilt of the bottom portion below the bend 506 is substantially constant.
  • Figure 5B shows an image 550 that is a perspective view' of a different modeled memory hole in accordance with some embodiments.
  • the image 550 shows a top surface 552 and the 3D curvature of a front-side surface 554 of the memory hole.
  • the image 550 shows that the top surface 552 is elliptical.
  • the shape of the front-side surface 554 suggests that the memory hole retains this elliptical shape as it extends downward.
  • the image shows the elliptical shape of the respective memory hole for multiple cross-sections (e.g., horizontal cross-sections) of the memory hole.
  • the image may also show the helicity of the respective memory hole and/or the tilt of the memory hole for the multiple cross-sections.
  • the helicity indicates change in orientation of the elliptical shape and may be defined as a degree of rotation of the major (or equivalently, the minor) axis of the ellipse with respect to the top surface (e.g., as measured in degrees or radians).
  • Figure 6 shows an image 600 that includes a perspective view (here, a side view 602) of a modeled memory hole along with cross-sections 606-1 through 606-6 of the memory hole at various depths, in accordance with some embodiments.
  • the arrows 604 between the side view 602 and respective cross-sections 606 indicate the depths for the respective cross-sections 606.
  • the cross-sections 606 show the size (e.g., the CD) and elliptical shape of the memory 7 hole at the various depths.
  • the cross-sections 606 also show the helicity of the memory hole at the various depths: the ellipses of the cross-sections 606 rotate as the depth increases. While the memory hole in Figure 6 has substantially zero tilt, the cross-sections 606 could also show' tilt if it were present, for example by having varied positions within their surrounding rectangles to demonstrate the offset with respect to the top surface.
  • the image highlights or otherwise indicates deviation from an elliptical shape for the multiple cross-sections.
  • a particular cross section 606 may not be precisely elliptical.
  • the portion of the cross-section that deviates from an ellipse e.g., falls outside of the ellipse or fails to reach the edge of the ellipse
  • may be highlighted e.g., shown with a particular color, shade, or fill patern.
  • the image may highlight or otherwise indicate deviation of the 3D shape or a portion thereof (e.g., a cross-section) from a nominal shape.
  • a memory hole and ellipse are merely one example of a respective structure and nominal shape for which such deviation may be displayed.
  • cross-sections may be shown such that they appear to be arranged along an axis (e.g., the z-axis, corresponding to depth), with the axis appearing to intersect the page at a slant (i.e., at an oblique angle).
  • the cross-sections may partially overlap fe.g., with respective cross-sections partially obscuring successive cross- sections).
  • the image includes a skeleton view' of the model in which multiple cross-sections are connected by contour lines (e.g., the contour lines intersect corresponding points on the circumference of each cross-section).
  • the skeleton view show's the 3D shape of the model (although not the entire 3D shape, because of the limited number of cross- sections and contour lines) but is to be displayed in 2D.
  • Figures 7A-7C show images 700, 720, and 740 of skeleton views of modeled memory holes in accordance with some embodiments.
  • cross-sections 702-1 through 702-5 are connected by contour lines 704-1 and 704-2.
  • the cross-sections 702 are elliptical, as show'll by the major and minor axes of the ellipses for the cross-sections 702.
  • the elliptical shape of the memory hole as quantified by its ellipticity (e.g., the ratio of the lengths of the major and minor axes) remains constant as a function of depth, as does the memory-hole CD and thus its size.
  • the memory hole is not helical: the ellipses of the cross-sections 702 do not rotate as a function of depth.
  • the memory hole does have tilt, however, which varies as a function of depth, as shown by the curvature of the contour lines 704-1 and 704-2.
  • cross-sections 722-1 through 722-5 are connected by contour lines 724-1 and 724-2.
  • the elliptical shape, and thus the ellipticity changes as a function of depth, with the minor axis increasing in length and becoming the major axis.
  • the ellipses do not rotate, however, indicating a lack of hehcity.
  • cross-sections 742-1 through 742-4 are connected by contour lines 744-1 and 744-2. While the ellipticity and CD of the cross-sections 742 remains constant, the memory' hole shows hehcity: the ellipses of the cross-sections 742 rotate with increasing depth. The axes of the ellipses can be seen to rotate.
  • Figures 8 A and 8B show images 800 and 810 of a modeled volume 802 in a semiconductor in accordance with some embodiments.
  • the volume 802 includes memory holes 804-1, 804-2, and 804-3, which may be part of a periodic 2D arrangement of memory holes.
  • the volume 802 is shown as opaque.
  • the image 800 shows the top surface of the memory hole 804-1, a portion of the top surface of the memory hole 804-2, and a portion of the top surface of the memory hole 804-3 along with a cross-sectional vertical profile of the memory- hole 804-3.
  • the volume 802 is translucent and 3D shapes of ail three memory holes 804-1, 804-2, and 804-3 are visible. Accordingly, both the images 800 and 810 show at least a partial 3D shape of at least one semiconductor structure (as modeled in step 208), but the image 810 shows significantly more 3D information that the image 800.
  • the image includes at least one of a top surface or a bottom surface of the modeled respective instance of the 3D semiconductor structure and also includes a user-selectable cross-section (e.g., a horizontal cross-section perpendicular to the vertical z-axis) of the modeled respective instance of the 3D semiconductor structure between the top and bottom surfaces.
  • a user-selectable cross-section e.g., a horizontal cross-section perpendicular to the vertical z-axis
  • Figure 9 shows an image 900 that includes a bottom surface 902 and a user-selectable cross-section 904 of a modeled memory hole m accordance with some embodiments.
  • the user-selectable cross-section 904 may be translucent.
  • the vertical position of the user-selectable cross-section 904 may vary based on user input 226 (e.g., in response to user input 226 specifying a new vertical position, the computer performing the method 200 repeats steps 218 and 220 to render and provide a new image with the user-selectable cross- section 904 in the newly specified vertical position).
  • the image shows the 3D shape of the model (but not the entire 3D shape, because of the limited number of cross-sections and contour lines), although the image may be for 2D display.
  • the image includes multiple user-selectable cross-sections, one or more (e.g., all) of which may be translucent.
  • the image is or includes (222) an AR/VR image or a 3D stereoscopic image.
  • the device to which the image is provided in step 224 thus may be an AR/VR viewing device (e.g., AR/VR goggles; AR glasses) or a 3D stereographic viewer.
  • the AR/VR image is a first AR/VR image of the model rendered from a first perspective.
  • the method 200 further includes, after sending the first AR/VR image to the AR/VR viewing device for display, receiving user input 226 requesting a change in perspective in response to the user input, step 222 is repeated, such that a second AR/VR image of the model is rendered from a second perspective.
  • the second AR/VR image is sent to the AR/VR viewing device for display, per step 224. In this manner, the user may effectively move around the image in AR/VR.
  • the AR/VR image is a first AR/VR image of the model with an appearance that corresponds to values of a parameter of the model as determined based on measurements collected during the inspection of step 202.
  • the method 200 further includes, after sending the first AR/VR image to the AR R viewing device for display, receiving user input 226 requesting a change to the values of the parameter.
  • the values of the parameter for the model are changed and a second AR/VR image of the model is rendered per step 222 with an appearance that corresponds to the changed values.
  • the second ARVR image is sent to the ARVR viewing device for display, per step 224.
  • the user may explore potential variation in the 3D shape of the semiconductor structure (e.g., explore how r much margin the semiconductor structure has before reaching a point of failure).
  • an image generated m accordance with the method 200 shows (e.g., highlights) the uncertainty associated with its 3D shape according to the model of step 218.
  • a region of uncertainty at the sides of the relevant modeled semiconductor-structure instance e.g., along the walls of a memory hole
  • Blurring e.g., of edges
  • dots may be used to indicate uncertainty.
  • An animation may be shown in which the 3D shape is shown to vary (e.g., positions of edges vary) through a range of possibilities, in accordance with the uncertainty. Other examples are possible.
  • an image generated in accordance with the method 200 includes an animation that successively shows successive portions of the 3D shape.
  • the animation may successively show successive cross-sections, such as cross-sections of increasing or decreasing depth.
  • the animation shows rotation of the 3 D shape, with successive portions rotating into and out of view.
  • data for the model may be overlaid on the image of the model, such that the image provided to a user’s device in step 224 includes the overlaid data.
  • the data may include numbers that specify values of one or more parameters/metrics for the model.
  • the data may include vectors that specify the electric field or strain. Other examples are possible.
  • images shown m Figures 3 A-8 are merely examples of 3 D visualization techniques that may be used in the method 200. Other examples are possible.
  • images produced by the method 200 are used to predict the performance of a semiconductor device.
  • images produced by the method 200 are used to make comparisons to reference images (e.g., CD-SEM or TEM images).
  • images produced by the method 200 are used to identify process or design changes.
  • FIG 10 is a block diagram of a semiconductor-inspection system 1000 in accordance with some embodiments.
  • the semiconductor-inspection system 1000 includes a semiconductor metrology tool 1032 and a computer system with one or more processors 1002 (e.g., CPUs and/or GPUs), optional user interfaces 1006, memory 1010, and one or more communication buses 1004 interconnecting these components.
  • the computer system may be communicatively coupled with the metrology tool 1032 through one or more networks 1030.
  • the computer system may further include one or more network interfaces (wired and/or wireless, not shown) for communicating with the metrology tool 1032 and/or remote computer systems.
  • network interfaces wireless and/or wireless, not shown
  • the metrology tool 1032 performs optical metrology and/or SAXS.
  • the user interfaces 1010 may include a display 1008 and/or one or more input devices (e.g., a keyboard, mouse, touch-sensitive surface of the display 1008, etc.).
  • the display 1008 may display the image of the method 200 in accordance with some embodiments.
  • Memory 1010 includes volatile and/or non-volatile memory.
  • Memory 1010 (e.g., the non-volatile memory within memory 1010) includes a non-transitory computer-readable storage medium.
  • Memory 1010 optionally includes one or more storage devices remotely located from the processors 1002 and/or a non-transitory computer-readable storage medium that is removably inserted into the computer system.
  • memory 1010 (e.g., the non-transitory computer-readable storage medium of memory 1010) stores the following modules and data, or a subset or superset thereof: an operating system 1012 that includes procedures for handling various basic system services and for performing hardware-dependent tasks, a model-generation module 1014, a model-updating module 1016, an image-rendering module 1018, an image-transmission module 1020, and a database 1022 of measurements collected from the metrology tool 1032.
  • an operating system 1012 that includes procedures for handling various basic system services and for performing hardware-dependent tasks
  • a model-generation module 1014 e.g., a model-updating module 1016
  • an image-rendering module 1018 e.g., the image-transmission module 1020
  • database 1022 e.g., the database 1022 of measurements collected from the metrology tool 1032.
  • the memory 1010 (e.g., the non-transitory computer-readable storage medium of the memory 1010) thus includes instructions for performing the method 200 ( Figure 2) m conjunction with the metrology tool 1032.
  • Each of the modules stored in the memory 1010 corresponds to a set of instructions for performing one or more functions described herein.
  • modules need not be implemented as separate software programs.
  • the modules and various subsets of the modules may be combined or otherwise re-arranged. In some
  • the memory 1010 stores a subset or superset of the modules and/or data structures identified above.
  • Figure 10 is intended more as a functional description of the various features that may be present in a semiconductor-inspection system than as a structural schematic.
  • the functionality' of the computer system m the semiconductor-inspection system 1000 may be split between multiple devices.
  • a portion of the modules stored in the memory 1010 may alternatively be stored m one or more other computer systems communicatively coupled with the computer system of the semiconductor-inspection system 1000 through one or more networks.

Abstract

A semiconductor metrology tool inspects an area of a semiconductor wafer. The inspected area includes a plurality of instances of a 3D semiconductor structure arranged periodically in at least one dimension. A computer system generates a model of a respective instance of the 3D semiconductor structure based on measurements collected during the inspection. The computer system renders an image of the model that shows a 3D shape of the model and provides the image to a device for display.

Description

VISUALIZATION OF THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURES
TECHNICAL FIELD
[0001] This disclosure relates to semiconductor metrology, and more specifically to generating visualizations that show the three-dimensional (3D) nature of semiconductor structures.
BACKGROUND
[0002] Three-dimensional semiconductor structures may be characterized using various types of metrology, such as different types of optical metrology and small-angle x-ray scattering (SAXS). Inadequate visualization of the resulting measurements, however, may cause data to be overlooked or not fully appreciated. Such data may be important for debugging a semiconductor manufacturing process, improving yield and reliability for the process, or predicting performance of a semiconductor device. Inadequate visualization also makes comparisons to reference data, such as data from critical-dimension scanning electron microscopy (CD-SEM) and transmission electron microscopy (TEM) difficult.
SUMMARY
[0003] Accordingly, there is a need for improved techniques for visualizing 3D semiconductor structures. Examples of such structures include, without limitation, memory holes in 3D memories (e.g., 3D flash memories), finFETs, and DRAM ceils.
[0004] In some embodiments, a method of semiconductor-structure visualization includes, in a semiconductor metrology tool, inspecting an area of a semiconductor wafer. The semiconductor wafer may include at least one of semiconductor logic circuitry or semiconductor memory circuitry. The inspected area includes a plurality of instances of a 3D semiconductor structure arranged periodically in at least one dimension. The method also includes, m a computer system comprising one or more processors and memory storing instructions for execution by the one or more processors, generating a model of a respective instance of the 3D semiconductor structure based on the inspecting. The method further includes, in the computer
i system, rendering an image of the model that shows a 3D shape of the model and providing the image to a device for display.
[0005] In some embodiments, a semiconductor-inspection system includes a
semiconductor metrology tool and a computer system with one or more processors and memory storing one or more programs for execution by the one or more processors. The one or more programs include instructions for performing all or a portion of the abo ve method. In some embodiments, a non-transitory computer-readable storage medium stores one or more programs configured for execution by a computer system. The one or more programs include instructions for performing all or a portion of the above method.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] For a better understanding of the various described embodiments, reference should be made to the Detailed Description below, in conjunction with the following drawings.
[0007] Figures 1A shows a graph that displays variation of the CD profile of a memory hole along its depth.
[0008] Figure I B shows a graph that displays the tilt of a memory hole along its depth
[0009] Figure 2 shows a fl owchart of a method of semiconductor-structure visualization in accordance with some embodiments.
[0010] Figure 3 A shows an image that is an isometric projection of a modeled slice of a
3D semiconductor memory device with a plurality of memory holes in accordance with some embodiments.
[0011] Figure 3B shows an image that is an isometric projection of modeled portions of two finFETs in accordance with some embodiments.
[0012] Figures 4A-4D show images of a modeled memory hole, rendered from different perspectives in accordance with some embodiments.
[0013] Figures 5A and 5B show images that are perspective views of respective modeled memory holes in accordance with some embodiments. [0014] Figure 6 shows an image that includes a perspective view of a modeled memory hole along with cross-sections of the model at various depths, in accordance with some embodiments.
[0015] Figures 7A-7C show' skeleton views of respective modeled memory holes in accordance with some embodiments.
[0016] Figures 8A and 8B show opaque and translucent images of a modeled volume in a semiconductor with memory holes in accordance with some embodiments.
[0017] Figure 9 shows an image that includes a bottom surface and a user-selectable cross-section of a modeled memory hole in accordance with some embodiments.
[0018] Figure 10 is a block diagram of a semiconductor-inspection system in accordance with some embodiments.
[0019] Like reference numerals refer to corresponding parts throughout the drawings and specification.
DETAILED DESCRIPTION
[0020] Reference will now be made in detail to various embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the various described embodiments. However, it will be apparent to one of ordinary skill in the art that the various described embodiments may be practiced without these specific details. In other instances, well-known methods, procedures, components, circuits, and networks have not been described in detail so as not to unnecessarily obscure aspects of the embodiments.
[0021] Figure 1 A shows a graph 100 that displays variation of the critical-dimension
(CD) profile (e.g., the diameter) of a memory hole along its depth. The memory hole extends vertically through a three-dimensional (3D) semiconductor memory structure (e.g., 3D flash memory), with the vertical direction (in other figures, the z-axis) corresponding to depth. The CD profile is measured in nanometers (nm). The graph 100 corresponds to a vertical cross- section of the memory hole. [0022] Figure IB shows a graph 110 that displays the tilt of a memory hole along its depth. Ideally the tilt should be zero, such that the graph shows a straight vertical line. In practice, however, the memory hole at any given depth may have an offset with respect to the hole at its surface. Tins offset, measured m nanometers, is the tilt. The tilt at a given depth may be determined by measuring the offset between a specified point on the surface of the memory hole (e.g., its center, a specific point on its circumference, etc.) and a corresponding point at that depth.
[0023] The low dimensionality of the graphs 100 and 1 10 - each shows variation of a parameter along a single dimension --- limits the information they convey. Each of the graphs 100 and 110 provides only a limited indication of the shape of the memory hole. More robust visualization methods that solve this problem by providing a sense of the 3D shape of the memory hole, or of another semiconductor structure, will now be described.
[0024] Figure 2 shows a flow-chart of a method 200 of semiconductor-structure visualization in accordance with some embodiments. The method 200 produces images that show 3D shapes and thus avoid the shortcomings of the graphs 100 and 110 (Figures 1 A and IB). The method 200 is described with reference to Figures 3A-8, which give examples of images that show 3D shapes of semiconductor structures. (Technically, the images show- models of semiconductor structures, wdierein the models are generated based on the results of semiconductor metrology, as described below-.) Steps in the method 200 may be combined or broken out.
[0025] In the method 200, a semiconductor metrology tool (e.g., the metrology tool 1032,
Figure 10) is used to inspect (202) an area of a semiconductor wafer. The semiconductor wafer includes at least one of semiconductor logic circuitry or semiconductor memory circuitry. The circuitry may be only partially fabricated at the time of inspection. The area that is inspected includes a plurality of instances of a 3D semiconductor structure arranged periodically in at least one dimension (e.g., in only one dimension or in two dimensions). Optical metrology or small- angle x-ray scattering (SAXS) may be performed (204) to inspect the area. Examples of optical- metrology techniques that may be performed include spectroscopic ellipsometry, single- wavelength ellipsometry, beam-profile ellipsometry-, beam-profile reflectometry, single- wavelength reflectometry, angle-resolved reflectometry-, spectroscopic reflectometry, scatterometry, and Raman spectroscopy. Examples of SAXS techniques that may be performed include transmissive SAXS, reflective SAXS, and grazing incidence SAXS
[0026] In some embodiments, the 3D semiconductor structure is a memory hole in a 3D memory (e.g., 3D flash memory), a fin field-effect transistor (finFET) or portion thereof, or a dynamic random-access memor (DRAM) ceil or portion thereof A memory hole may be inspected when it is empty (e.g., after etch but before fill), filled, or at some intermediate step between etch and complete fill. Likewise, other structures may be inspected at various steps in their fabrication processes. The inspected area therefore may include (206) a periodic arrangement of memory holes m a 3D memory, a periodic arrangement of finFETs, or an array of DRAM cells. Alternatively, other 3D semiconductor structures may be inspected.
[0027] The steps following steps 202, 204, and/or 206 (i.e., steps 208 and on) are performed in a computer system communicatively coupled with the metrology tool (e.g., the computer system of the semiconductor-inspection system 1000, Figure 10).
[0028] Based on measurements collected during the inspection step 202, a model of a respective instance of the 3D semiconductor structure is generated (208). In some embodiments, the respective instance is or includes a respective memory hole, a respective finFET or portion thereof, or a respective DRAM cell or portion thereof, in accordance with step 206.
[0029] In some embodiments, to generate this model, a geometric model of the 3D semiconductor structure with parameterized dimensions (i.e., a parameterized geometric model) is obtained (210). The geometric model may also include information about material properties, and thus be a parameterized geometric/material model. The parameterized geometric model (e.g., geometric/material model) is typically created in advance, before the inspection step 202. Measurements collected during the inspection step 202 are used (212) to determine values of the parameterized dimensions. This determination may be made by performing regression on the parameters of the geometric model (e.g., geometric/material model). For example, this determination may be made using a machine-learning model trained using training sets of measurements, actual and/or simulated, for which corresponding parameter values for the parameterized geometric model (e.g., geometric/material model) have been determined.
[0030] In some other embodiments, to generate this model, sets of measurements (actual and/or simulated) for varying instances of the 3D semiconductor structure are obtained (214). Each set is labeled with respective values of dimensions. Machine learning is performed, using the set and the measurements collected during the inspection step 202, to determine (216) values of the dimensions for the respective instance. A parameterized geometric model of the 3D semiconductor structure is not used.
[0031] An image of the model is rendered (218) that show's a 3D shape of the model.
The image may show a partial 3D shape of the model, for example because one or more surfaces and/or sides are obscured or absent, and/or because the image includes a limited number of cross-sections. Alternatively, the image may show' the full 3D shape of the model, for example using augmented reality or virtual reality (AR/VR) or holography . The model and image may be voxelated, such that they are built up using voxels (volume elements, w'hich are the 3D equivalent of pixels). The image is provided (224) to a device for display. In one example, the image is provided to a display screen (e.g., display 1008, Figure 10) of the computer system that performs steps 208-224. In another example, the image is transmitted to a different electronic device (e.g., a client computer or mobile electronic device with a display, an AR/VR viewer, a 3D stereoscopic viewer, a holographic display system, etc.) for display. In still another example, the image is transmitted to a 3D printer, which may additively manufacture an object having the shape of the model, thereby displaying the 3D shape of the model.
[0032] In some embodiments, the image includes (220) a projection for two-dimensional
(2D) display. For example, the projection may be an axonometric projection (e.g., an isometric projection, dimetric projection, or trimetric projection) showing multiple sides of the model. The dimensions of the projection thus may share a common scale or have different scales. While the projection is to be displayed in 2D, it shows a 3D shape of the model (although not the entire 3D shape in accordance with some embodiments, because some sides and/or surfaces may be obscured by the visible sides and/or surfaces).
[0033] Figure 3 A show's an image 300 that is an isometric projection of a modeled slice
304 of a 3D semiconductor memory device (e.g., a 3D flash memory) with a plurality of memory holes 302-1 through 302-7 in accordance with some embodiments. The slice 304 may comprise multiple layers (e.g., a series of alternating oxide (Sx02) and nitride (S13N4) layers) through which the memory holes 302 extend vertically. The image 300 only show's the 2D top surfaces of memory holes 302-1, 302-4, and 302-7, but shows cut-away view's of memory holes 302-2, 302-3, 302-5, and 302-6 The cut-away views of the memory holes 302-3 and 302-6 show the 3D shapes of their back halves with respect to the plane through which they have been sliced.
The image 300 is thus an example of the image of step 220. The 3D shapes of the memory holes 302-3 and 302-6 may be shown using contour lines (as in Figure 3A), shading, coloring, or other appropriate graphical techniques for 2D projections of 3D objects. The image 300 is thus an example of the image of step 220.
[0034] Figure 3B shows an image 350 that is an isometric projection of modeled portions of two finFETs in accordance with some embodiments. The first fxnFET has a channel 352-1 and the second fmFET has a channel 352-2. The channels 352 are separated by a gap 354 that isolates the two finFETs. As for the memory holes 302-3 and 302-6 of Figure 3 A, the 3D shapes of these structures may be shown using contour lines (as in Figure 3B), shading, coloring, or other appropriate graphical techniques. The image 350 is another example of the image of step 220
[0035] As the images 300 and 350 showy the image of steps 218 and 224 may show- the
3D shape of multiple instances of a semiconductor structure or portions thereof (e.g., multiple instances of memory holes 302 or channels 352).
[0036] In some embodiments, the perspective of the image may be varied in response to user input 226. Figure 4A shows an image 400A of a modeled memory' hole, rendered from a first perspective in accordance with some embodiments. From the first perspective, the image 400A show's the top surface 402 and front-side surface 404 of the memory hole. The use of contour lines (or shading, coloring, etc.) shows a 3D shape of the memory hole: the image 400A shows the 3D curvature of the front-side surface 404. The bottom surface 406 and back-side surface of the memory hole are obscured in this perspective. In response to receiving user input 226 specifying a change in perspective, the computer system performing the method 400 renders (218) a new image 400B, 400C, or 400D from the changed perspective and provides (224) the new' image 400B, 400C, or 400D to the user’s device for display. (Alternatively, the new image may have been rendered and stored before the user input 226 is received, and is provided in response to the user input 226) This process may be performed iteratively to allow the user to view the memory hole from multiple perspectives (e.g., to view the images 400B, 400C, and/or 400D in turn). For example, the user may rotate the view of the memory hole in specified directions. The image 400B is a side view that shows the 3D curvature of the front-side surface 404 but does not show top surface 402, bottom surface 406, or back-side surface. The image 400C is a bottom view that shows only the bottom surface 406. The image 400D is a top view that shows only the top surface 402. The images 400C and 400D are not examples of the image of step 218, because they do not show' a 3D shape, but they would be if rotated slightly to show a side surface or portion thereof.
[0037] In some embodiments, instead of varying the perspective from which the image is rendered, the model itself may be varied in response to user input 226 (e.g., such that the arrow- labeled with“user input 226” points back to step 208 instead of step 218). For example, the user input 226 may specify changes to one or more dimensions (e.g., distances) or angles of the model of the respective instance. The model is updated in response to the user input 226, such that it no longer corresponds to the measurements collected during the inspection of step 202.
An image of the updated model is then rendered and sent to the user’s device for display. This modification allows the user to explore how' much margin the semiconductor structure has before reaching a point of failure (e.g., before adjacent conductive structures short out). The image of the updated model may be annotated to indicate the update(s) to the model (e.g., to indicate the dimensional changes, changes to one or more angles, etc.). Annotations may be user-driven (e.g., indicating specified distances or angles, in accordance with the user input 226).
[0038] Figure 5A show's an image 500 that is a perspective view of a modeled memory- hole in accordance with some embodiments. Like the image 400A (Figure 4A), the image 500 shows a top surface 502 and the 3D curvature of a front-side surface 504 of the memory' hole.
But the image 500 also show-s tilt, w-hereas the memory hole of the image 400 A lacked tilt (i.e. , the tilt was substantially zero, such that the memory hole was substantially straight in the vertical direction). A top portion of the memory hole in the image 500 slants downward at an oblique angle, until a bend 506 in a middle porti on of the memory hole, where the memory hole bends toward the vertical. A bottom portion of the memory hole than extends downward without substantial slant. If tilt is defined as an offset with respect to the top surface, as discussed for Figure I B, then the tilt of the bottom portion below the bend 506 is substantially constant.
[0039] Figure 5B shows an image 550 that is a perspective view' of a different modeled memory hole in accordance with some embodiments. Like the images 400A (Figure 4A) and 500 (Figure 5), the image 550 shows a top surface 552 and the 3D curvature of a front-side surface 554 of the memory hole. The image 550 shows that the top surface 552 is elliptical. The shape of the front-side surface 554 suggests that the memory hole retains this elliptical shape as it extends downward.
[0040] In some embodiments in which the respective instance of the 3D semiconductor structure is a respective memory hole, the image shows the elliptical shape of the respective memory hole for multiple cross-sections (e.g., horizontal cross-sections) of the memory hole.
The image may also show the helicity of the respective memory hole and/or the tilt of the memory hole for the multiple cross-sections. The helicity indicates change in orientation of the elliptical shape and may be defined as a degree of rotation of the major (or equivalently, the minor) axis of the ellipse with respect to the top surface (e.g., as measured in degrees or radians). For example, Figure 6 shows an image 600 that includes a perspective view (here, a side view 602) of a modeled memory hole along with cross-sections 606-1 through 606-6 of the memory hole at various depths, in accordance with some embodiments. The arrows 604 between the side view 602 and respective cross-sections 606 indicate the depths for the respective cross-sections 606. The cross-sections 606 show the size (e.g., the CD) and elliptical shape of the memory7 hole at the various depths. The cross-sections 606 also show the helicity of the memory hole at the various depths: the ellipses of the cross-sections 606 rotate as the depth increases. While the memory hole in Figure 6 has substantially zero tilt, the cross-sections 606 could also show' tilt if it were present, for example by having varied positions within their surrounding rectangles to demonstrate the offset with respect to the top surface.
[0041] In some embodiments, the image highlights or otherwise indicates deviation from an elliptical shape for the multiple cross-sections. For example, a particular cross section 606 may not be precisely elliptical. The portion of the cross-section that deviates from an ellipse (e.g., falls outside of the ellipse or fails to reach the edge of the ellipse) may be highlighted (e.g., shown with a particular color, shade, or fill patern). More generally, the image may highlight or otherwise indicate deviation of the 3D shape or a portion thereof (e.g., a cross-section) from a nominal shape. A memory hole and ellipse are merely one example of a respective structure and nominal shape for which such deviation may be displayed. Other examples are possible. [0042] In some embodiments, cross-sections may be shown such that they appear to be arranged along an axis (e.g., the z-axis, corresponding to depth), with the axis appearing to intersect the page at a slant (i.e., at an oblique angle). In this arrangement, the cross-sections may partially overlap fe.g., with respective cross-sections partially obscuring successive cross- sections).
[0043] In some embodiments, the image includes a skeleton view' of the model in which multiple cross-sections are connected by contour lines (e.g., the contour lines intersect corresponding points on the circumference of each cross-section). The skeleton view show's the 3D shape of the model (although not the entire 3D shape, because of the limited number of cross- sections and contour lines) but is to be displayed in 2D. Figures 7A-7C show images 700, 720, and 740 of skeleton views of modeled memory holes in accordance with some embodiments.
[0044] In the image 700, cross-sections 702-1 through 702-5 are connected by contour lines 704-1 and 704-2. The cross-sections 702 are elliptical, as show'll by the major and minor axes of the ellipses for the cross-sections 702. The elliptical shape of the memory hole, as quantified by its ellipticity (e.g., the ratio of the lengths of the major and minor axes) remains constant as a function of depth, as does the memory-hole CD and thus its size. The memory hole is not helical: the ellipses of the cross-sections 702 do not rotate as a function of depth. The memory hole does have tilt, however, which varies as a function of depth, as shown by the curvature of the contour lines 704-1 and 704-2.
[0045] In the image 720, cross-sections 722-1 through 722-5 are connected by contour lines 724-1 and 724-2. The elliptical shape, and thus the ellipticity, changes as a function of depth, with the minor axis increasing in length and becoming the major axis. The size of the memory hole, and thus its CD, change dramatically as a function of depth. The ellipses do not rotate, however, indicating a lack of hehcity.
[0046] In the image 740, cross-sections 742-1 through 742-4 are connected by contour lines 744-1 and 744-2. While the ellipticity and CD of the cross-sections 742 remains constant, the memory' hole shows hehcity: the ellipses of the cross-sections 742 rotate with increasing depth. The axes of the ellipses can be seen to rotate.
[0047] The use of multiple cross-sections thus can provi de extensive information regarding 3D shape, as shown m Figures 6 and 7A-7C. [0048] Figures 8 A and 8B show images 800 and 810 of a modeled volume 802 in a semiconductor in accordance with some embodiments. The volume 802 includes memory holes 804-1, 804-2, and 804-3, which may be part of a periodic 2D arrangement of memory holes. In the image 800, the volume 802 is shown as opaque. The image 800 shows the top surface of the memory hole 804-1, a portion of the top surface of the memory hole 804-2, and a portion of the top surface of the memory hole 804-3 along with a cross-sectional vertical profile of the memory- hole 804-3. in the image 810, the volume 802 is translucent and 3D shapes of ail three memory holes 804-1, 804-2, and 804-3 are visible. Accordingly, both the images 800 and 810 show at least a partial 3D shape of at least one semiconductor structure (as modeled in step 208), but the image 810 shows significantly more 3D information that the image 800.
[0049] In some embodiments, the image includes at least one of a top surface or a bottom surface of the modeled respective instance of the 3D semiconductor structure and also includes a user-selectable cross-section (e.g., a horizontal cross-section perpendicular to the vertical z-axis) of the modeled respective instance of the 3D semiconductor structure between the top and bottom surfaces. For example, Figure 9 shows an image 900 that includes a bottom surface 902 and a user-selectable cross-section 904 of a modeled memory hole m accordance with some embodiments. The user-selectable cross-section 904 may be translucent. The vertical position of the user-selectable cross-section 904 may vary based on user input 226 (e.g., in response to user input 226 specifying a new vertical position, the computer performing the method 200 repeats steps 218 and 220 to render and provide a new image with the user-selectable cross- section 904 in the newly specified vertical position). By providing multiple cross-sections (i.e , the top and/or bottom surface and the user-selectable cross-section), the image shows the 3D shape of the model (but not the entire 3D shape, because of the limited number of cross-sections and contour lines), although the image may be for 2D display. In some embodiments, the image includes multiple user-selectable cross-sections, one or more (e.g., all) of which may be translucent.
[0050] In some embodiments, the image is or includes (222) an AR/VR image or a 3D stereoscopic image. The device to which the image is provided in step 224 thus may be an AR/VR viewing device (e.g., AR/VR goggles; AR glasses) or a 3D stereographic viewer.
I I [0051] For example, the AR/VR image is a first AR/VR image of the model rendered from a first perspective. The method 200 further includes, after sending the first AR/VR image to the AR/VR viewing device for display, receiving user input 226 requesting a change in perspective in response to the user input, step 222 is repeated, such that a second AR/VR image of the model is rendered from a second perspective. The second AR/VR image is sent to the AR/VR viewing device for display, per step 224. In this manner, the user may effectively move around the image in AR/VR.
[0052] In another example, the AR/VR image is a first AR/VR image of the model with an appearance that corresponds to values of a parameter of the model as determined based on measurements collected during the inspection of step 202. The method 200 further includes, after sending the first AR/VR image to the AR R viewing device for display, receiving user input 226 requesting a change to the values of the parameter. In response to the user input, the values of the parameter for the model are changed and a second AR/VR image of the model is rendered per step 222 with an appearance that corresponds to the changed values. The second ARVR image is sent to the ARVR viewing device for display, per step 224. In this manner, the user may explore potential variation in the 3D shape of the semiconductor structure (e.g., explore howr much margin the semiconductor structure has before reaching a point of failure).
[0053] In some embodiments, an image generated m accordance with the method 200 shows (e.g., highlights) the uncertainty associated with its 3D shape according to the model of step 218. For example, to the extent that there is uncertainty in the CD, a region of uncertainty at the sides of the relevant modeled semiconductor-structure instance (e.g., along the walls of a memory hole) could be shown in a different color, shade, or fill pattern than the rest of the relevant modeled semiconductor-structure instance, thus indicating the uncertainty in the precise location of the sides. Blurring (e.g., of edges) or dots may be used to indicate uncertainty. An animation may be shown in which the 3D shape is shown to vary (e.g., positions of edges vary) through a range of possibilities, in accordance with the uncertainty. Other examples are possible.
[0054] Metrics described above, such as tilt, e!iipticity, deviation from a nominal shape
(e.g., an elliptical shape), and hehcity, are merely examples of metrics that may be shown in an image generating using the method 200. Other metrics (e.g., derivative metrics, metrics generated using a Fourier transform, etc.) may also or alternatively be shown. [0055] In some embodiments, an image generated in accordance with the method 200 includes an animation that successively shows successive portions of the 3D shape. For example, the animation may successively show successive cross-sections, such as cross-sections of increasing or decreasing depth. In another example, the animation shows rotation of the 3 D shape, with successive portions rotating into and out of view.
[0056] In some embodiments, data for the model may be overlaid on the image of the model, such that the image provided to a user’s device in step 224 includes the overlaid data.
The data may include numbers that specify values of one or more parameters/metrics for the model. The data may include vectors that specify the electric field or strain. Other examples are possible.
[0057] The images shown m Figures 3 A-8 are merely examples of 3 D visualization techniques that may be used in the method 200. Other examples are possible. In some embodiments, images produced by the method 200 are used to predict the performance of a semiconductor device. In some embodiments, images produced by the method 200 are used to make comparisons to reference images (e.g., CD-SEM or TEM images). In some embodiments, images produced by the method 200 are used to identify process or design changes.
[0058] Figure 10 is a block diagram of a semiconductor-inspection system 1000 in accordance with some embodiments. The semiconductor-inspection system 1000 includes a semiconductor metrology tool 1032 and a computer system with one or more processors 1002 (e.g., CPUs and/or GPUs), optional user interfaces 1006, memory 1010, and one or more communication buses 1004 interconnecting these components. The computer system may be communicatively coupled with the metrology tool 1032 through one or more networks 1030.
The computer system may further include one or more network interfaces (wired and/or wireless, not shown) for communicating with the metrology tool 1032 and/or remote computer systems.
In some embodiments, the metrology tool 1032 performs optical metrology and/or SAXS.
[0059] The user interfaces 1010 may include a display 1008 and/or one or more input devices (e.g., a keyboard, mouse, touch-sensitive surface of the display 1008, etc.). The display 1008 may display the image of the method 200 in accordance with some embodiments.
[0060] Memory 1010 includes volatile and/or non-volatile memory. Memory 1010 (e.g., the non-volatile memory within memory 1010) includes a non-transitory computer-readable storage medium. Memory 1010 optionally includes one or more storage devices remotely located from the processors 1002 and/or a non-transitory computer-readable storage medium that is removably inserted into the computer system. In some embodiments, memory 1010 (e.g., the non-transitory computer-readable storage medium of memory 1010) stores the following modules and data, or a subset or superset thereof: an operating system 1012 that includes procedures for handling various basic system services and for performing hardware-dependent tasks, a model-generation module 1014, a model-updating module 1016, an image-rendering module 1018, an image-transmission module 1020, and a database 1022 of measurements collected from the metrology tool 1032.
[0061] The memory 1010 (e.g., the non-transitory computer-readable storage medium of the memory 1010) thus includes instructions for performing the method 200 (Figure 2) m conjunction with the metrology tool 1032. Each of the modules stored in the memory 1010 corresponds to a set of instructions for performing one or more functions described herein.
Separate modules need not be implemented as separate software programs. The modules and various subsets of the modules may be combined or otherwise re-arranged. In some
embodiments, the memory 1010 stores a subset or superset of the modules and/or data structures identified above.
[0062] Figure 10 is intended more as a functional description of the various features that may be present in a semiconductor-inspection system than as a structural schematic. For example, the functionality' of the computer system m the semiconductor-inspection system 1000 may be split between multiple devices. A portion of the modules stored in the memory 1010 may alternatively be stored m one or more other computer systems communicatively coupled with the computer system of the semiconductor-inspection system 1000 through one or more networks.
[0063] The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the scope of the claims to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The embodiments were chosen in order to best explain the principles underlying the claims and their practical applications, to thereby enable others skilled in the art to best use the embodiments with various modifications as are suited to the particular uses contemplated.

Claims

WHAT IS CLAIMED IS:
1. A method of semiconductor-structure visualization, comprising,
in a semiconductor metrology tool:
on a semiconductor wafer comprising at least one of semiconductor logic circuitry or semiconductor memory circuitry, inspecting an area of the semiconductor wafer that includes a plurality of instances of a three-dimensional (3D) semiconductor structure arranged periodically in at least one dimension; and
in a computer system comprising one or more processors and memory storing instructions for execution by the one or more processors:
based on the inspecting, generating a model of a respective instance of the 3D semiconductor structure;
rendering an image of the model that shows a 3D shape of the model; and providing the image to a device for display.
2. The method of claim 1, wherein the image comprises a projection of the model to be displayed in two dimensions.
3. The method of claim 1, wherein the image comprises a skeleton view of the model in which multiple cross-sections are connected by contour lines, wherein the skeleton view is to be displayed in two dimensions.
4. The method of claim 1, wherein the image comprises:
at least one of a top surface or a bottom surface of the respective instance of the 3D semiconductor structure; and
a user-selectable translucent cross-section of the respective instance of the 3D
semiconductor structure between the top and bottom surfaces.
5. The method of claim 1, wherein the image shows uncertainty for the 3D shape in the model.
6. The method of claim 1, wherein the image indicates deviation of the 3D shape or a cross- section of the 3D shape from a nominal shape.
7. The method of claim 1, wherein the image comprises an animation that successively shows successive portions of the 3D shape.
8. The method of claim 1, wherein:
rendering the image comprises rendering an augmented-reality or virtual-reality (AR/VR) image; and
providing the image comprises sending the AR/VR image to an AR/VR viewing device for display.
9. The method of claim 8, wherein the AR/VR image is a first AR/VR image of the model rendered from a first perspective, the method further comprising, after sending the first AR/VR image to the AR/VR viewing device for display:
receiving user input requesting a change in perspective;
in response to the user input, rendering a second AR/VR image of the model from a second perspective; and
sending the second AR/VR image to the AR/VR viewing device for display.
10. The method of claim 8, wherein the AR/VR image is a first ARVR image of the model with an appearance that corresponds to values of a parameter of the model as determined based on measurements collected during the inspecting, the method further comprising, after sending the first AR/VR image to the AR/VR viewing device for display:
receiving user input requesting a change to the values of the parameter;
in response to the user input, changing the values of the parameter for the model;
rendering a second AR/VR image of the model with an appearance that corresponds to the changed values; and
sending the second AR/VR image to the AR/VR viewing device for display.
11. The method of claim 1, wherein:
the image is a 3D stereographic image; and
providing the image comprises sending the image to a 3D stereographic viewrer.
12. The method of claim l, wherein:
the plurality of instances of the 3D semiconductor structure comprises a periodic arrangement of memory holes in a 3D memory; and
the respective instance of the 3D semiconductor structure comprises a respective memory hole.
13. The method of claim 12, wherein the image shows an elliptical shape of the respective memory hole for multiple cross-sections of the memory hole.
14. The method of claim 13, wherein the image shows the heiicity of the respective memory hole for the multiple cross-sections, wherein the heiicity indicates change in orientation of the elliptical shape.
15. The method of claim 12, wherein the image indicates deviation from an elliptical shape for the multiple cross-sections.
16. The method of claim 12, wherein the image shows tilt of the respective memory hole.
17. The method of claim 1 , wherein:
the plurality of instances of the 3D semiconductor structure comprises a periodic arrangement of finFETs; and
the respective instance of the 3D semiconductor structure comprises a respective finFET or a portion of a respective finFET
18. The method of claim 1, wherein:
the plurality of instances of the 3D semiconductor structure comprises an array of DRAM cells; and
the respective instance of the 3D semiconductor structure comprises a respective DRAM cell or a portion of a respective DRAM cell.
19. The method of claim 1 , wherein generating the model of the respective instance of the 3D semiconductor structure comprises:
obtaining a geometric model of the 3D semiconductor structure with parameterized dimensions; and using measurements collected during the inspecting to determine values of the parameterized dimensions.
20. The method of claim 1, wherein generating the model of the respective instance of the 3D semiconductor structure comprises:
obtaining sets of measurements for varying instances of the 3D semiconductor structure, the sets being labeled with respective values of dimensions; and
performing machine learning, using the sets and measurements collected during the inspecting, to determine values of the dimensions for the respective instance,
wherein the generating is performed without using a parameterized geometric model of the 3D semiconductor structure.
21. The method of claim 1, wherein inspecting the area of the semiconductor wafer comprises performing an optical metrology technique selected from the group consisting of spectroscopic ellipsometry, single- wavelength ellipsometry, beam-profile ellipsometry, beam- profile refiectometry, single-wavelength refiectometry, angle-resolved reflectometry, spectroscopic refiectometry, scatterometry, and Raman spectroscopy.
22. The method of claim 1, wherein inspecting the area of the semiconductor wafer comprises performing small-angle x-ray scattering.
23. A semiconductor-inspection system, comprising:
a semiconductor metrology tool;
one or more processors; and
memory storing one or more programs for execution by the one or more processors, the one or more programs comprising instructions for:
based on inspection by the semiconductor metrology tool of an area of a semiconductor wafer that includes a plurality of instances of a three-dimensional (3D) semiconductor structure arranged periodically, generating a model of a respective instance of the 3D semiconductor structure;
rendering an image of the model that show¾ a 3D shape of the model; and providing the image to a device for display.
24. A non-transitory computer-readable storage medium storing one or more programs for execution by one or more processors of a computer system, the one or more programs including instructions for:
based on inspection by a semiconductor metrology tool of an area of a semiconductor wafer that includes a plurality of instances of a three-dimensional (3D) semiconductor structure arranged periodically, generating a model of a respective instance of the 3D semiconductor structure;
rendering an image of the model that shows a 3D shape of the model; and
providing the image to a device for display.
PCT/US2019/020470 2018-03-05 2019-03-04 Visualization of three-dimensional semiconductor structures WO2019173170A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201980016475.0A CN111837226B (en) 2018-03-05 2019-03-04 Visualization of three-dimensional semiconductor structures
KR1020207028527A KR102468979B1 (en) 2018-03-05 2019-03-04 Visualization of 3D semiconductor structures
JP2020546171A JP7189959B2 (en) 2018-03-05 2019-03-04 Visualization of 3D semiconductor structures
JP2022193365A JP2023025174A (en) 2018-03-05 2022-12-02 Computer-readable storage medium for visualizing three-dimensional semiconductor structure

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201862638721P 2018-03-05 2018-03-05
US62/638,721 2018-03-05
US16/283,690 2019-02-22
US16/283,690 US10794839B2 (en) 2019-02-22 2019-02-22 Visualization of three-dimensional semiconductor structures

Publications (1)

Publication Number Publication Date
WO2019173170A1 true WO2019173170A1 (en) 2019-09-12

Family

ID=67846809

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2019/020470 WO2019173170A1 (en) 2018-03-05 2019-03-04 Visualization of three-dimensional semiconductor structures

Country Status (5)

Country Link
JP (2) JP7189959B2 (en)
KR (1) KR102468979B1 (en)
CN (1) CN111837226B (en)
TW (1) TWI778239B (en)
WO (1) WO2019173170A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021113191A1 (en) * 2019-12-02 2021-06-10 Kla Corporation Tomography based semiconductor measurements using simplified models
CN113539877A (en) * 2021-07-22 2021-10-22 长鑫存储技术有限公司 Measuring device and measuring method for semiconductor structure
WO2022051171A1 (en) * 2020-09-04 2022-03-10 Kla Corporation Binning-enhanced defect detection method for three-dimensional wafer structures

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112384749B (en) * 2020-03-13 2022-08-19 长江存储科技有限责任公司 System and method for semiconductor chip hole geometry metrology
KR102554169B1 (en) * 2021-10-06 2023-07-12 (주)구일엔지니어링 Inspection method for via-hole of the wafer

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090296073A1 (en) * 2008-05-28 2009-12-03 Lam Research Corporation Method to create three-dimensional images of semiconductor structures using a focused ion beam device and a scanning electron microscope
JP2014130077A (en) * 2012-12-28 2014-07-10 Hitachi High-Technologies Corp Pattern shape evaluation method, semiconductor device manufacturing method, and pattern shape evaluation device
US20160290934A1 (en) * 2015-04-03 2016-10-06 Kla-Tencor Corporation Optical Die to Database Inspection
US20160307116A1 (en) * 2013-12-05 2016-10-20 Tokyo Electron Limited System and method for learning and/or optimizing manufacturing processes
US20160350445A1 (en) * 2006-04-17 2016-12-01 Omnivision Technologies Inc. Arrayed imaging systems having improved alignment and associated methods

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08298092A (en) * 1995-04-26 1996-11-12 Hitachi Ltd Analyzing method for scanning electron microscope
JP3749107B2 (en) 1999-11-05 2006-02-22 ファブソリューション株式会社 Semiconductor device inspection equipment
JP3959355B2 (en) 2003-01-17 2007-08-15 株式会社日立ハイテクノロジーズ Measuring method of three-dimensional shape of fine pattern
JP4516957B2 (en) * 2003-01-25 2010-08-04 パーデュー リサーチ ファンデーション Method, system and data structure for searching for 3D objects
JP4500653B2 (en) 2003-11-25 2010-07-14 株式会社日立ハイテクノロジーズ Sample observation method and apparatus
JP4695857B2 (en) 2004-08-25 2011-06-08 株式会社日立ハイテクノロジーズ Semiconductor inspection method and semiconductor inspection apparatus
US8485038B2 (en) 2007-12-18 2013-07-16 General Electric Company System and method for augmented reality inspection and data visualization
KR101670458B1 (en) 2010-06-25 2016-10-28 삼성전자주식회사 Method of measuring an overlay of an object
US8832620B1 (en) 2013-03-14 2014-09-09 Coventor, Inc. Rule checks in 3-D virtual fabrication environment
NL2013312A (en) * 2013-09-09 2015-03-10 Asml Netherlands Bv Methods and apparatus for calculating electromagnetic scattering properties of a structure and for reconstruction of approximate structures.
US9553033B2 (en) * 2014-01-15 2017-01-24 Kla-Tencor Corporation Semiconductor device models including re-usable sub-structures
US9494535B2 (en) * 2014-04-21 2016-11-15 Kla-Tencor Corporation Scatterometry-based imaging and critical dimension metrology
US10352876B2 (en) * 2014-05-09 2019-07-16 KLA—Tencor Corporation Signal response metrology for scatterometry based overlay measurements
US10096144B2 (en) * 2014-07-17 2018-10-09 Crayola, Llc Customized augmented reality animation generator
KR102076527B1 (en) * 2014-08-27 2020-04-02 삼성전자주식회사 A radiographic imaging apparatus and a method for controlling the same
US10380728B2 (en) * 2015-08-31 2019-08-13 Kla-Tencor Corporation Model-based metrology using images
US10352695B2 (en) * 2015-12-11 2019-07-16 Kla-Tencor Corporation X-ray scatterometry metrology for high aspect ratio structures
EP3398123A4 (en) * 2015-12-31 2019-08-28 KLA - Tencor Corporation Accelerated training of a machine learning based model for semiconductor applications

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160350445A1 (en) * 2006-04-17 2016-12-01 Omnivision Technologies Inc. Arrayed imaging systems having improved alignment and associated methods
US20090296073A1 (en) * 2008-05-28 2009-12-03 Lam Research Corporation Method to create three-dimensional images of semiconductor structures using a focused ion beam device and a scanning electron microscope
JP2014130077A (en) * 2012-12-28 2014-07-10 Hitachi High-Technologies Corp Pattern shape evaluation method, semiconductor device manufacturing method, and pattern shape evaluation device
US20160307116A1 (en) * 2013-12-05 2016-10-20 Tokyo Electron Limited System and method for learning and/or optimizing manufacturing processes
US20160290934A1 (en) * 2015-04-03 2016-10-06 Kla-Tencor Corporation Optical Die to Database Inspection

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021113191A1 (en) * 2019-12-02 2021-06-10 Kla Corporation Tomography based semiconductor measurements using simplified models
US11610297B2 (en) 2019-12-02 2023-03-21 Kla Corporation Tomography based semiconductor measurements using simplified models
WO2022051171A1 (en) * 2020-09-04 2022-03-10 Kla Corporation Binning-enhanced defect detection method for three-dimensional wafer structures
US11798828B2 (en) 2020-09-04 2023-10-24 Kla Corporation Binning-enhanced defect detection method for three-dimensional wafer structures
CN113539877A (en) * 2021-07-22 2021-10-22 长鑫存储技术有限公司 Measuring device and measuring method for semiconductor structure
CN113539877B (en) * 2021-07-22 2023-10-17 长鑫存储技术有限公司 Measuring device and measuring method for semiconductor structure

Also Published As

Publication number Publication date
JP2021516448A (en) 2021-07-01
KR102468979B1 (en) 2022-11-18
CN111837226A (en) 2020-10-27
KR20200118905A (en) 2020-10-16
JP7189959B2 (en) 2022-12-14
JP2023025174A (en) 2023-02-21
CN111837226B (en) 2024-03-08
TWI778239B (en) 2022-09-21
TW201945691A (en) 2019-12-01

Similar Documents

Publication Publication Date Title
WO2019173170A1 (en) Visualization of three-dimensional semiconductor structures
US11099137B2 (en) Visualization of three-dimensional semiconductor structures
Zhang et al. Plenopatch: Patch-based plenoptic image manipulation
US9972120B2 (en) Systems and methods for geometrically mapping two-dimensional images to three-dimensional surfaces
US9916684B2 (en) Generating portable three-dimensional print-preview renderings of three-dimensional models
US20130112407A1 (en) Obtaining Data From An Earth Model Using Functional Descriptors
US10410380B2 (en) Image rendering utilizing procedural yarn model generated in multi-stage processing pipeline
Seers et al. Extraction of three-dimensional fracture trace maps from calibrated image sequences
US20160092605A1 (en) System and method for generating planar section 3d shape representations
US20070201737A1 (en) System And Method For Vascular Visualization Using Planar Reformation Of Vascular Central Axis Surface With Biconvex Slab
Yu et al. Multiperspective modeling, rendering, and imaging
Campos et al. Splat-based surface reconstruction from defect-laden point sets
US20220222842A1 (en) Image reconstruction for virtual 3d
Ravanelli et al. A high-resolution photogrammetric workflow based on focus stacking for the 3D modeling of small Aegean inscriptions
Wagemans et al. Measuring 3D point configurations in pictorial space
Bueno et al. Quantitative evaluation of CHT and GHT for column detection under different conditions of data quality
Zhao et al. Paracatadioptric camera calibration using sphere images and common self-polar triangles
Olsen et al. Hinged, pseudo-grid triangulation method for long, near-linear cliff analyses
US20110074777A1 (en) Method For Displaying Intersections And Expansions of Three Dimensional Volumes
Kumar et al. Estimation of planar angles from non-orthogonal imaging
JPWO2019173170A5 (en)
CN117456550B (en) MR-based CAD file viewing method, device, medium and equipment
US20020171643A1 (en) Surface generator unit for and method of approximating an implicit surface and image display apparatus comprising the surface generator unit
Kamali Ardakani et al. Camera Arrangement using Geometric Optimization to Minimize Localization Error in Stereo-vision Systems
Obermaier et al. Visualizing strain anisotropy in mantle flow fields

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19764593

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2020546171

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 20207028527

Country of ref document: KR

Kind code of ref document: A

122 Ep: pct application non-entry in european phase

Ref document number: 19764593

Country of ref document: EP

Kind code of ref document: A1