CN111837226B - Visualization of three-dimensional semiconductor structures - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 135
- 238000012800 visualization Methods 0.000 title description 5
- 238000007689 inspection Methods 0.000 claims abstract description 31
- 238000005259 measurement Methods 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims description 55
- 238000003860 storage Methods 0.000 claims description 26
- 230000008859 change Effects 0.000 claims description 16
- 238000002310 reflectometry Methods 0.000 claims description 12
- 230000004044 response Effects 0.000 claims description 11
- 238000000235 small-angle X-ray scattering Methods 0.000 claims description 11
- 238000010801 machine learning Methods 0.000 claims description 8
- 230000000737 periodic effect Effects 0.000 claims description 8
- 230000003287 optical effect Effects 0.000 claims description 6
- 238000001069 Raman spectroscopy Methods 0.000 claims description 4
- 238000000096 single-wavelength ellipsometry Methods 0.000 claims description 3
- 238000000391 spectroscopic ellipsometry Methods 0.000 claims description 3
- 238000009877 rendering Methods 0.000 claims 1
- 239000000463 material Substances 0.000 description 5
- 238000004040 coloring Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- 238000007794 visualization technique Methods 0.000 description 2
- 238000003917 TEM image Methods 0.000 description 1
- 230000003190 augmentative effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000001093 holography Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000009304 pastoral farming Methods 0.000 description 1
- 238000001878 scanning electron micrograph Methods 0.000 description 1
- 238000004626 scanning electron microscopy Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004611 spectroscopical analysis Methods 0.000 description 1
- 238000012549 training Methods 0.000 description 1
- 238000004627 transmission electron microscopy Methods 0.000 description 1
- 239000013598 vector Substances 0.000 description 1
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
- G01B11/00—Measuring arrangements characterised by the use of optical techniques
- G01B11/24—Measuring arrangements characterised by the use of optical techniques for measuring contours or curvatures
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
- G01B15/00—Measuring arrangements characterised by the use of electromagnetic waves or particle radiation, e.g. by the use of microwaves, X-rays, gamma rays or electrons
- G01B15/04—Measuring arrangements characterised by the use of electromagnetic waves or particle radiation, e.g. by the use of microwaves, X-rays, gamma rays or electrons for measuring contours or curvatures
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
- G01B21/00—Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant
- G01B21/20—Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant for measuring contours or curvatures, e.g. determining profile
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N23/00—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00
- G01N23/20—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by using diffraction of the radiation by the materials, e.g. for investigating crystal structure; by using scattering of the radiation by the materials, e.g. for investigating non-crystalline materials; by using reflection of the radiation by the materials
- G01N23/201—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by using diffraction of the radiation by the materials, e.g. for investigating crystal structure; by using scattering of the radiation by the materials, e.g. for investigating non-crystalline materials; by using reflection of the radiation by the materials by measuring small-angle scattering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
- G01B2210/00—Aspects not specifically covered by any group under G01B, e.g. of wheel alignment, caliper-like sensors
- G01B2210/56—Measuring geometric parameters of semiconductor structures, e.g. profile, critical dimensions or trench depth
Abstract
A semiconductor metrology tool inspects a region of a semiconductor wafer. The inspected region includes a plurality of examples of 3D semiconductor structures that are periodically arranged in at least one dimension. A computer system generates a model of a respective instance of the 3D semiconductor structure based on measurements collected during the inspection. The computer system presents an image of the model showing a 3D shape of the model and provides the image to a device for display.
Description
Technical Field
The present invention relates to semiconductor metrology, and more particularly, to generating visualizations showing three-dimensional (3D) properties of semiconductor structures.
Background
Various types of metrology, such as different types of optical metrology and small angle x-ray scattering (SAXS), may be used to characterize three-dimensional semiconductor structures. However, inadequate visualization of the resulting measurements may cause the data to be ignored or inadequately understood. This data may be important to debug the semiconductor manufacturing process, to improve yield and reliability of the process, or to predict performance of the semiconductor device. Inadequate visualization also makes comparison with reference data, such as data from critical dimension scanning electron microscopy (CD-SEM) and Transmission Electron Microscopy (TEM), difficult.
Disclosure of Invention
Accordingly, improved techniques for visualizing 3D semiconductor structures are needed. Examples of such structures include, but are not limited to, memory holes, finfets, and DRAM cells in 3D memory, such as 3D flash memory.
In some embodiments, a method of visualizing a semiconductor structure includes: in a semiconductor metrology tool, a region of a semiconductor wafer is inspected. The semiconductor die may include at least one of semiconductor logic circuitry or semiconductor memory circuitry. The inspected region includes a plurality of examples of 3D semiconductor structures that are periodically arranged in at least one dimension. The method further comprises: in a computer system comprising one or more processors and a memory storing instructions for execution by the one or more processors, a model of a respective instance of the 3D semiconductor structure is generated based on the verification. The method further comprises: an image of the model showing a 3D shape of the model is presented in the computer system and provided to a device for display.
In some embodiments, a semiconductor inspection system includes a semiconductor metrology tool and a computer system having one or more processors and memory storing one or more programs executed by the one or more processors. The one or more programs include instructions for performing all or a portion of the above methods. In some embodiments, a non-transitory computer readable storage medium stores one or more programs configured to be executed by a computer system. The one or more programs include instructions for performing all or a portion of the above methods.
Drawings
For a better understanding of the various described embodiments, reference should be made to the following description taken in conjunction with the following drawings.
FIG. 1A shows a graph showing the variation of CD profile of a memory hole along its depth.
Fig. 1B shows a graph showing the inclination of a memory hole along its depth.
Fig. 2 shows a flow chart of a method of visualizing a semiconductor structure in accordance with some embodiments.
Fig. 3A shows an image that is an isometric projection of a modeled slice of a 3D semiconductor memory device having a plurality of memory holes, according to some embodiments.
Figure 3B shows an image that is an isometric projection of modeled segments of two finfets, according to some embodiments.
Fig. 4A-4D show images of modeled memory apertures presented from different perspectives, according to some embodiments.
Fig. 5A and 5B show images that are perspective views of respective modeled memory apertures, according to some embodiments.
FIG. 6 shows an image including a perspective view of a modeled memory hole along with a cross-section of a model at various depths, according to some embodiments.
Fig. 7A-7C show architectural views of respective modeled memory holes, according to some embodiments.
Fig. 8A and 8B show opaque and semi-transparent images of modeled volumes in a semiconductor with memory holes, according to some embodiments.
FIG. 9 shows an image including a bottom surface of a modeled memory hole and a user-selectable cross-section, according to some embodiments.
FIG. 10 is a block diagram of a semiconductor inspection system according to some embodiments.
Like reference numerals designate corresponding parts throughout the drawings and specification.
Detailed Description
Reference will now be made in detail to various embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the various described embodiments. However, it will be apparent to one of ordinary skill in the art that the various described embodiments may be practiced without these specific details. In other instances, well-known methods, procedures, components, circuits, and networks have not been described in detail so as not to unnecessarily obscure aspects of the embodiments.
Fig. 1A shows a graph 100 showing a variation in Critical Dimension (CD) profile (e.g., diameter) of a memory hole along its depth. The memory holes extend vertically through a three-dimensional (3D) semiconductor memory structure (e.g., a 3D flash memory), with the vertical direction (in other figures, the z-axis) corresponding to depth. The CD profile is measured in nanometers (nm). Graph 100 corresponds to a vertical cross section of a memory aperture.
FIG. 1B shows a graph 110 of the inclination of a memory hole along its depth. Ideally the slope should be zero so that the graph shows a straight vertical line. In practice, however, the memory holes at any given depth may have an offset relative to the holes at their surface. This shift measured in nanometers is the tilt. The inclination at a given depth may be determined by measuring the offset between a specified point on the surface of the memory hole (e.g., the center of the memory hole, a specified point on the circumference of the memory hole, etc.) and a corresponding point at that depth.
The low-dimension limit graphs of graphs 100 and 110, each showing a variation in parameters along a single dimension, convey information. Each of the graphs 100 and 110 provides only a limited indication of the shape of the memory aperture. A more robust visualization method to solve this problem by providing sensing (sense) of the 3D shape of the memory hole or another semiconductor structure will now be described.
Fig. 2 shows a flow chart of a method 200 of visualizing a semiconductor structure in accordance with some embodiments. Method 200 produces an image that shows a 3D shape and thus avoids the drawbacks of charts 100 and 110 (fig. 1A and 1B). The method 200 is described with reference to fig. 3A-8, which give examples of images showing 3D shapes of semiconductor structures. (technically, the image shows a model of the semiconductor structure, wherein the model is generated based on the results of semiconductor metrology, as described below). The steps in method 200 may be combined or broken down.
In method 200, a semiconductor metrology tool (e.g., metrology tool 1032, fig. 10) is used to inspect (202) a region of a semiconductor wafer. The semiconductor die includes at least one of a semiconductor logic circuit or a semiconductor memory circuit. The circuit may be only partially fabricated at the time of the inspection. The region examined includes multiple examples of 3D semiconductor structures that are periodically arranged in at least one dimension (e.g., in only one dimension or in two dimensions). Optical metrology or small angle x-ray scattering (SAXS) may be performed (204) to inspect a region. Examples of optical metrology techniques that may be performed include spectroscopic ellipsometry, single wavelength ellipsometry, beam profile reflectometry, single wavelength reflectometry, angle resolved reflectometry, spectroscopic reflectometry, scatterometry, and Raman (Raman) spectroscopy. Examples of executable SAXS techniques include transmissive SAXS, reflective SAXS, and grazing incidence SAXS.
In some embodiments, the 3D semiconductor structure is a memory hole, a fin field effect transistor (finFET), or a portion thereof, or a Dynamic Random Access Memory (DRAM) cell, or a portion thereof, in a 3D memory (e.g., a 3D flash memory). The memory holes may be empty (e.g., after etching but before filling), filled, or inspected at some intermediate step between etching and completing filling. Likewise, other structures may be inspected at various steps in their manufacturing process. The verified region may thus include (206) a periodic arrangement of memory holes in the 3D memory, a periodic arrangement of finfets, or an array of DRAM cells. Alternatively, other 3D semiconductor structures may be inspected.
The steps following steps 202, 204, and/or 206 (i.e., step 208, etc.) are performed in a computer system communicatively coupled with the metrology tool (e.g., the computer system of semiconductor inspection system 1000, fig. 10).
Based on the measurements collected during the inspection step 202, a model of the respective instance of the 3D semiconductor structure is generated (208). In some embodiments, the respective examples are or include respective memory holes, respective finfets or portions thereof, or respective DRAM cells or portions thereof, in accordance with step 206.
In some embodiments, to generate this model, a geometric model (i.e., a parameterized geometric model) of the 3D semiconductor structure having parameterized dimensions is obtained (210). The geometric model may also include information about material properties, and thus be a parameterized geometric/material model. The parameterized geometric model (e.g., geometric/material model) is typically formed in advance of the inspection step 202. Measurements collected during the inspection step 202 are used (212) to determine values of the parameterized dimensions. This determination may be made by performing regression on parameters of a geometric model (e.g., geometric/material model). For example, this determination may be made using a machine learning model that is trained using a training measurement set (actual and/or simulated) for which corresponding parameter values for a parameterized geometric model (e.g., geometric/material model) have been determined.
In some other embodiments, to generate this model, a set of measurements (actual and/or simulated) for different examples of 3D semiconductor structures is obtained (214). Each set is marked with a corresponding value of the size. Machine learning is performed using the set and measurements collected during the checking step 202 to determine (216) values for the dimensions of the respective examples. A parameterized geometric model of the 3D semiconductor structure is not used.
An image of the model showing the 3D shape of the model is presented (218). The image may show a portion of the 3D shape of the model, for example, because one or more surfaces and/or sides are obscured or absent, and/or because the image includes a limited number of cross-sections. Alternatively, the image may show the complete 3D shape of the model, for example using augmented reality or virtual reality (AR/VR) or holography. The model and image may be voxelized such that they are built using voxels (volume elements, which are 3D equivalents of pixels). The image is provided (224) to the device for display. In one example, the image is provided to a display screen (e.g., display 1008, fig. 10) of the computer system performing steps 208-224. In another example, the image is transmitted to a different electronic device (e.g., a client computer or mobile electronic device with a display, an AR/VR viewer, a 3D stereoscopic viewer, a holographic display system, etc.) for display. In yet another example, the image is transmitted to a 3D printer, which can additively manufacture an object having the shape of the model, thereby displaying the 3D shape of the model.
In some embodiments, the image includes (220) a projection for a two-dimensional (2D) display. For example, the projections may be axonometric projections (e.g., equiangular projections, or non-equiangular projections) of multiple sides of the presentation model. The dimensions of the projections may thus share a common scale or have different scales. When the projection is to be displayed in 2D, it shows the 3D shape of the model (but not the entire 3D shape according to some embodiments, as some sides and/or surfaces may be obscured by visible sides and/or surfaces).
FIG. 3A shows an image 300 according to some embodiments, the image 300 beingAn isometric projection of a modeled slice 304 of a 3D semiconductor memory device (e.g., 3D flash memory) having a plurality of memory holes 302-1 through 302-7. The slice 304 may include multiple layers through which the memory holes 302 extend vertically (e.g., a series of alternating oxides (SiO) 2 ) Nitride (Si) 3 N 4 ) A layer). Image 300 shows only the 2D top surfaces of memory holes 302-1, 302-4, and 302-7, but shows cross-sectional views of memory holes 302-2, 302-3, 302-5, and 302-6. The cross-sectional view of the memory holes 302-3 and 302-6 shows the 3D shape of the rear half relative to the plane through which they have been sliced. Image 300 is thus an example of the image of step 220. The 3D shape of the memory holes 302-3 and 302-6 may be shown using contour lines (as in fig. 3A), shading, coloring, or other suitable graphics techniques for 2D projection of 3D objects. Image 300 is thus an example of the image of step 220.
Figure 3B shows an image 350, the image 350 being an isometric projection of modeled portions of two finfets, according to some embodiments. The first finFET has a channel 352-1 and the second finFET has a channel 352-2. The channels 352 are separated by a gap 352-4 that separates the two finfets. With respect to memory holes 302-3 and 302-6 of FIG. 3A, the 3D shape of these structures may be shown using contours (as in FIG. 3B), shading, coloring, or other suitable graphics techniques. Image 350 is another example of the image of step 220.
As shown in images 300 and 350, the images of steps 218 and 224 may show 3D shapes of multiple instances of a semiconductor structure or portion thereof (e.g., multiple instances of memory hole 302 or channel 352).
In some embodiments, the perspective of the image may be changed in response to user input 226. FIG. 4A shows an image 400A of a modeled memory hole presented from a first perspective, according to some embodiments. From the first perspective, image 400A shows top surface 402 and front side surface 404 of the memory hole. The 3D shape of the memory aperture is shown using contour lines (or shading, coloring, etc.): image 400A shows the 3D curvature of anterior surface 404. The bottom surface 406 and the backside surface of the memory aperture are obscured in this view. In response to receiving user input 226 specifying a change in perspective, the computer system executing method 200 presents (218) a new image 400B, 400C, or 400D from the changed perspective and provides (224) the new image 400B, 400C, or 400D to the user's device for display. (alternatively, the new image may have been presented and stored prior to the user input 226 being received and provided in response to the user input 226). This process may be performed iteratively to allow a user to view the memory aperture from multiple perspectives (e.g., view images 400B, 400C, and/or 400D in sequence). For example, a user may rotate the view of the memory aperture in a specified direction. Image 400B is a side view showing the 3D curvature of front side surface 404 but not showing top surface 402, bottom surface 406, or back side surface. Image 400C is a bottom view showing only bottom surface 406. Image 400D is a top view showing only top surface 402. Images 400C and 400D are examples of the images of step 218 because they do not show a 3D shape, but if they are rotated slightly to show a side surface or portion of a side surface they will show a 3D shape.
In some embodiments, instead of changing the perspective of the presented image, the model itself may be changed in response to user input 226 (e.g., such that the arrow labeled "user input 226" points back to step 208 instead of step 218), e.g., user input 226 may specify a change in one or more dimensions (e.g., distances) or angles of the model of the respective instance. The model is updated in response to the user input 226 such that the model no longer corresponds to the measurements collected during the verification of step 202. An image of the updated model is then presented and sent to the user's device for display. This modification allows the user to explore how much margin the semiconductor structure has before reaching the failure point (e.g., before shorting of adjacent conductive structures). The image of the updated model may be annotated to indicate update(s) of the model (e.g., to indicate a change in size, a change in one or more angles, etc.). The annotation may be user-driven (e.g., indicative of a specified distance or angle according to user input 226).
FIG. 5A shows an image 500, the image 500 being a perspective view of a modeled memory hole, according to some embodiments. Like image 400A (fig. 4A), image 500 shows the 3D curvature of the top surface 502 and front side surface 504 of the memory hole. Image 500 also shows a tilt, whereas the memory aperture of image 400A is not tilted (i.e., the tilt is substantially zero such that the memory aperture is substantially straight in the vertical direction). The top portion of the memory hole in image 500 is tilted downward at an oblique angle to a bend 506 in the middle portion of the memory hole (where the memory hole is bent toward the vertical). The bottom of the memory hole extends downward without significant tilting. If the slope is defined as an offset relative to the top surface (as discussed with respect to fig. 1B), then the slope of the bottom portion below the curve 506 is substantially constant.
FIG. 5B shows an image 550, the image 550 being a perspective view of a different modeled memory aperture, according to some embodiments. Like images 400A (fig. 4A) and 500 (fig. 5A), image 550 shows the 3D curvature of the top surface 552 and front side surface 554 of the memory hole. Image 550 shows that top surface 552 is elliptical. The shape of the front side surface 554 implies that the memory aperture retains this oval shape as it extends downward.
In some embodiments in which the respective examples of 3D semiconductor structures are respective memory holes, the images show elliptical shapes of the memory holes for multiple cross-sections (e.g., horizontal cross-sections) of the respective memory holes. The image may also show the helicity of the respective reservoir hole and/or the inclination of the reservoir hole for multiple cross sections. Helicity indicates the change in orientation of the elliptical shape and may be defined as the degree of rotation of the long (or equivalently, short) axis of the ellipse relative to the top surface (e.g., as measured in degrees or radians). For example, FIG. 6 shows an image 600 according to some embodiments, the image 600 including a perspective view (here, side view 602) of a modeled memory hole along with cross-sections 606-1 to 606-6 of the memory hole at various depths. Arrow 604 between side view 602 and respective cross section 606 indicates a depth for respective cross section 606. Cross section 606 shows the dimensions (e.g., CD) and oval shape of the memory hole at various depths. Cross section 606 also shows the helicity of the memory hole at various depths: the ellipse of cross section 606 rotates with increasing depth. Although the memory aperture in fig. 6 has a substantially zero slope, cross section 606 may also exhibit a slope (if it exists), for example, by having varying positions within its surrounding rectangle to demonstrate an offset relative to the top surface.
In some embodiments, the image highlights or otherwise indicates deviations from the elliptical shape for the plurality of cross-sections. For example, the particular cross-section 606 may not be exactly elliptical. Portions of the cross-section that deviate from an ellipse (e.g., fall outside the ellipse or cannot reach the edges of the ellipse) may be highlighted (e.g., shown with a particular color, shading, or fill pattern). More generally, the image may highlight or otherwise indicate a deviation of the 3D shape or a portion thereof (e.g., cross-section) from a nominal shape. Memory holes and ellipses are merely examples of corresponding structures and nominal shapes for which such deviations may be displayed. Other examples are possible.
In some embodiments, the cross section may be shown such that it appears to be arranged along an axis (e.g., the z-axis corresponding to depth), where the axis appears to intersect the page at an inclination (e.g., at an oblique angle). In this arrangement, the cross-sections may partially overlap (e.g., where the respective cross-section partially obscures the continuous cross-section).
In some embodiments, the image includes an architectural view of the model, where multiple cross-sections are connected by contour lines (e.g., the contour lines intersect corresponding points on the circumference of each cross-section). The architectural view shows the 3D shape of the model (but not the entire 3D shape, due to the limited number of cross-sections and contour lines), but will be displayed in 2D. Fig. 7A-7C show images 700, 720, and 740 of architectural views of modeled memory holes, according to some embodiments.
In image 700, cross sections 702-1 through 702-5 are connected by contours 704-1 and 704-2. The cross section 702 is elliptical, as shown by the major and minor axes of the ellipse for the cross section 702. The elliptical shape of the memory hole, as quantified by its ellipticity (e.g., length ratio of major axis to minor axis), remains constant as a function of depth, as does the memory hole CD and thus its size. The reservoir holes are not helical: the ellipse of the cross section 702 does not rotate with depth. However, the memory holes do have a slope that varies with depth (as shown by the curvature of the contours 704-1 and 704-2).
In image 720, cross-sections 722-1 through 722-5 are connected by contours 724-1 and 724-2. The elliptical shape, and thus ellipticity, changes with depth, with the minor axis increasing in length and becoming the major axis. The size of the memory hole and thus its CD changes significantly with depth. However, the ellipse does not rotate, indicating no helicity.
In image 740, cross sections 742-1 through 742-4 are connected by contours 744-1 and 744-2. Although the ellipticity and CD of cross section 742 remain constant, the memory hole shows a helicity: the ellipse of cross section 742 rotates with increasing depth. The elliptical axis rotation is visible.
The use of multiple cross-sections may thus provide broad information about the 3D shape, as shown in fig. 6 and 7A-7C.
Fig. 8A and 8B show images 800 and 810 of modeled volume 802 in a semiconductor according to some embodiments. The volume 802 includes memory holes 804-1, 804-2, and 804-3, which may be part of a periodic 2D arrangement of memory holes. In image 800, volume 802 is shown as opaque. Image 800 shows the top surface of memory hole 804-1, a portion of the top surface of memory hole 804-2, and a portion of the top surface of memory hole 804-3 along with the cross-sectional vertical profile of memory hole 804-3. In image 810, volume 802 is semi-transparent and the 3D shape of all three memory holes 804-1, 804-2, and 804-3 is visible. Thus, both images 800 and 810 show at least a portion of the 3D shape of at least one semiconductor structure (as modeled in step 208), but image 810 shows significantly more 3D information than image 800.
In some embodiments, the image includes at least one of a top surface or a bottom surface of the modeled respective instance of the 3D semiconductor structure and also includes a user selectable cross section (e.g., a horizontal cross section perpendicular to a vertical z-axis) of the modeled respective instance of the 3D semiconductor structure between the top surface and the bottom surface. For example, fig. 9 shows an image 900 including a bottom surface 902 of a modeled memory hole and a user-selectable cross-section 904, according to some embodiments. The user selectable cross section 904 may be translucent. The vertical position of the user-selectable cross-section 904 may be changed based on the user input 226 (e.g., in response to the user input 226 specifying a new vertical position, the computer executing the method 200 repeats steps 218 and 220 to present and provide a new image in which the user-selectable cross-section 904 is in the newly specified vertical position). By providing multiple cross-sections (i.e., top and/or bottom surfaces and user-selectable cross-sections), the image shows the 3D shape of the model (but not the entire 3D shape, due to the limited number of cross-sections and contours), but the image can be used for 2D display. In some embodiments, the image includes a plurality of user selectable cross-sections, one or more (e.g., all) of which may be translucent.
In some embodiments, the image is or includes (222) an AR/VR image or a 3D stereoscopic image. The device to which the image is provided in step 224 may thus be an AR/VR viewing device (e.g., AR/VR goggles; AR glasses) or a 3D stereoscopic viewer.
For example, the AR/VR image is a first AR/VR image of the model that is presented from a first perspective. The method 200 further includes, after sending the first AR/VR image to an AR/VR viewing device for display, receiving a user input requesting a change in viewing angle 226. Responsive to the user input, step 222 is repeated such that a second AR/VR image of the model is presented from a second perspective. Each step 224 sends the second AR/VR image to an AR/VR viewing device for display. In this way, the user can effectively move around the image in the AR/VR.
In another example, the AR/VR image is a first AR/VR image of the model having an appearance corresponding to values of parameters of the model as determined based on measurements collected during the inspection of step 202. The method 200 further includes, after sending the first AR/VR image to an AR/VR viewing device for display, receiving a user input requesting a change in the value of the parameter 226. In response to the user input, the values of the parameters for the model are changed and each step 222 presents a second AR/VR image of the model having an appearance corresponding to the changed values. Each step 224 sends the second AR/VR image to an AR/VR viewing device for display. In this way, a user may explore potential changes in the 3D shape of the semiconductor structure (e.g., explore how much margin the semiconductor structure has before reaching the failure point).
In some embodiments, the image generated according to method 200 shows (e.g., highlights) the uncertainty associated with its 3D shape according to the model of step 218. For example, to the extent there is uncertainty in the CD, the uncertainty region (e.g., along the walls of the memory hole) at the side of the relevant modeled semiconductor structural example may be different from the color, shading, or fill pattern presentation of the rest of the relevant modeled semiconductor structural example, indicating uncertainty in the precise location of the side. Blur (e.g., blurring of edges) or points may be used to indicate uncertainty. Animation may be shown in which the 3D shape is shown to change within a range of possibilities (e.g., the position of the edge changes) according to the uncertainty. Other examples are possible.
The indices described above, such as slope, ellipticity, deviation from a nominal shape (e.g., elliptical shape), and helicity, are merely examples of indices that may be shown in the image produced using the method 200. Other metrics (e.g., derived metrics, metrics generated using fourier transforms, etc.) may also or alternatively be presented.
In some embodiments, the image generated according to method 200 includes an animation that continuously shows successive portions of the 3D shape. For example, the animation may continuously show a continuous cross section (e.g., a cross section of increasing or decreasing depth). In another example, the animation shows a rotation of the 3D shape, with successive portions rotated into and out of the field of view.
In some embodiments, the data for the model may be superimposed on the image of the model such that the image provided to the user's device in step 224 includes the superimposed data. The data may include numbers specifying values for one or more parameters/metrics of the model. The data may include vectors specifying electric fields or strains. Other examples are possible.
The images shown in fig. 3A-8 are merely examples of 3D visualization techniques that may be used in the method 200. Other examples are possible. In some embodiments, the image produced by the method 200 is used to predict the performance of a semiconductor device. In some embodiments, the image produced by the method 200 is for comparison with a reference image (e.g., a CD-SEM or TEM image). In some embodiments, the image produced by the method 200 is used to identify process or design variations.
Fig. 10 is a block diagram of a semiconductor inspection system 1000 in accordance with some embodiments. The semiconductor inspection system 1000 includes a semiconductor metrology tool 1032 and a computer system having one or more processors 1002 (e.g., CPUs and/or GPUs), an optional user interface 1006, a memory 1010, and one or more communication buses 1004 interconnecting these components. The computer system may be communicatively coupled with a metrology tool 1032 through one or more networks 1030. The computer system may further include one or more network interfaces (wired and/or wireless, not shown) for communicating with the metrology tool 1032 and/or a remote computer system. In some embodiments, metrology tool 1032 performs optical metrology and/or SAXS.
The user interface 1010 may include the display 1008 and/or one or more input devices (e.g., a keyboard, a mouse, a touch-sensitive surface of the display 1008, etc.). The display 1008 may display an image of the method 200 according to some embodiments.
Memory 1010 includes volatile and/or nonvolatile memory. Memory 1010 (e.g., non-volatile memory within memory 1010) includes non-transitory computer-readable storage media. Memory 1010 optionally includes one or more storage devices remotely located from processor 1002 and/or non-transitory computer-readable storage media removably inserted into a computer system. In some embodiments, the memory 1010 (e.g., a non-transitory computer-readable storage medium of the memory 1010) stores the following modules and data, or a subset or superset thereof: an operating system 1012 including programs for handling various basic system services and for performing hardware dependent tasks, a model generation module 1014, a model update module 1016, an image presentation module 1018, an image transmission module 1020, and a database 1022 of measurements collected from metrology tools 1032.
The memory 1010 (e.g., a non-transitory computer-readable storage medium of the memory 1010) thus includes instructions for performing the method 200 (fig. 2) in conjunction with the metrology tool 1032. Each of the modules stored in the memory 1010 corresponds to a set of instructions for performing one or more functions described herein. The separation module need not be implemented as a separate software program. The modules and various subsets of the modules may be combined or otherwise rearranged. In some embodiments, memory 1010 stores a subset or superset of the modules and/or data structures identified above.
Fig. 10 is intended more as a functional description of various features that may be present in a semiconductor inspection system than as a schematic. For example, the functionality of a computer system in semiconductor inspection system 1000 may be divided among multiple devices. A portion of the modules stored in memory 1010 may alternatively be stored in one or more other computer systems that are communicatively coupled to the computer system of semiconductor inspection system 1000 through one or more networks.
The foregoing description, for purposes of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the scope of the claims to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching. The embodiments were chosen in order to best explain the principles of the invention as a basis for the claims and their practical application to thereby enable others skilled in the art to best utilize the embodiments with various modifications as are suited to the particular use contemplated.
Claims (38)
1. A non-transitory computer-readable storage medium storing one or more programs for execution by one or more processors of a computer system, the one or more programs comprising instructions for:
Generating a model of a respective instance of a periodically arranged three-dimensional 3D semiconductor structure based on inspection of a region of a semiconductor wafer containing the respective instance of the 3D semiconductor structure by a semiconductor metrology tool;
presenting an image of the model showing a 3D shape of the model, the image comprising:
at least one of a top surface or a bottom surface of the respective example of the 3D semiconductor structure; and
A user selectable translucent cross-section of the respective example of the 3D semiconductor structure between the top surface and the bottom surface; and
Providing the image to a device for display;
wherein generating the model of the respective instance of the 3D semiconductor structure comprises:
obtaining a set of measurements for different examples of the 3D semiconductor structure, the set being labeled with respective values of dimensions; and
Machine learning is performed using the set and measurements collected during the inspection to determine values of the dimensions for the respective examples,
wherein the generating is performed without using a parameterized geometric model of the 3D semiconductor structure.
2. The computer-readable storage medium of claim 1, wherein the image comprises a projection of the model to be displayed in two dimensions.
3. The computer-readable storage medium of claim 1, wherein the image shows uncertainty for the 3D shape in the model.
4. The computer-readable storage medium of claim 1, wherein the image indicates a deviation of the 3D shape or a cross-section of the 3D shape from a nominal shape.
5. The computer-readable storage medium of claim 1, wherein the image comprises an animation that continuously shows successive portions of the 3D shape.
6. The computer-readable storage medium of claim 1, wherein:
the image is a 3D stereoscopic image; and is also provided with
Providing the image includes sending the image to a 3D stereoscopic viewer.
7. The computer-readable storage medium of claim 1, wherein:
the plurality of examples of the 3D semiconductor structure include a periodic arrangement of memory holes in a 3D memory; and is also provided with
The respective examples of the 3D semiconductor structure include respective memory holes.
8. The computer-readable storage medium of claim 7, wherein the image shows an elliptical shape of the respective memory hole for a plurality of cross-sections of the respective memory hole.
9. The computer-readable storage medium of claim 8, wherein the image shows a helicity of the respective memory hole for the plurality of cross sections, wherein the helicity indicates a change in an orientation of the elliptical shape.
10. The computer-readable storage medium of claim 7, wherein the image indicates a deviation from an elliptical shape for the plurality of cross-sections.
11. The computer-readable storage medium of claim 7, wherein the image shows a tilt of the respective memory aperture.
12. The computer-readable storage medium of claim 1, wherein:
the plurality of examples of the 3D semiconductor structure include a periodic arrangement of finfets; and is also provided with
The respective examples of the 3D semiconductor structure include a respective finFET or a portion of a respective finFET.
13. The computer-readable storage medium of claim 1, wherein:
the plurality of examples of the 3D semiconductor structure include an array of DRAM cells; and is also provided with
The respective examples of the 3D semiconductor structure include respective DRAM cells or portions of respective DRAM cells.
14. The computer-readable storage medium of claim 1, wherein inspecting the region of the semiconductor wafer comprises performing an optical metrology technique selected from the group consisting of: spectroscopic ellipsometry, single wavelength ellipsometry, beam profile reflectometry, single wavelength reflectometry, angle resolved reflectometry, spectroscopic reflectometry, scatterometry, and raman spectroscopy.
15. The computer-readable storage medium of claim 1, wherein inspecting the region of the semiconductor wafer comprises performing small angle x-ray scattering.
16. A non-transitory computer-readable storage medium storing one or more programs for execution by one or more processors of a computer system, the one or more programs comprising instructions for:
generating a model of a respective instance of a periodically arranged three-dimensional 3D semiconductor structure based on inspection of a region of a semiconductor wafer containing the respective instance of the 3D semiconductor structure by a semiconductor metrology tool;
presenting a first AR/VR image of the model showing a 3D shape of the model from a first perspective;
providing the first AR/VR image to an AR/VR viewing device for display;
after providing the first AR/VR image to the AR/VR viewing device for display, receiving a user input requesting a change in viewing angle;
presenting a second AR/VR image of the model from a second perspective in response to the user input; and
The second AR/VR image is provided to the AR/VR viewing device for display.
17. A non-transitory computer-readable storage medium storing one or more programs for execution by one or more processors of a computer system, the one or more programs comprising instructions for:
Generating a model of a respective instance of a periodically arranged three-dimensional 3D semiconductor structure based on inspection of a region of a semiconductor wafer containing the respective instance of the 3D semiconductor structure by a semiconductor metrology tool;
presenting a first AR/VR image of the model showing a 3D shape of the model, the model having an appearance corresponding to values of parameters of the model as determined based on measurements collected during the inspection;
providing the first AR/VR image to an AR/VR viewing device for display;
after providing the first AR/VR image to the AR/VR viewing device for display, receiving a user input requesting a change in the value of the parameter;
changing the value of the parameter for the model in response to the user input;
presenting a second AR/VR image of the model that will have an appearance corresponding to the changed value; and
The second AR/VR image is provided to the AR/VR viewing device for display.
18. A non-transitory computer-readable storage medium storing one or more programs for execution by one or more processors of a computer system, the one or more programs comprising instructions for:
Generating a model of a respective memory hole based on inspection of an area of a semiconductor wafer containing a periodic arrangement of memory holes in a three-dimensional 3D semiconductor memory by a semiconductor metrology tool;
presenting an image of the model showing a 3D shape of the model, wherein the image shows an elliptical shape of the respective memory hole for a plurality of cross-sections of the respective memory hole and shows a helicity of the respective memory hole for the plurality of cross-sections, wherein the helicity indicates a change in orientation of the elliptical shape; and
Providing the image to a device for display;
wherein generating the model of the respective memory hole comprises:
obtaining a set of measurements for different memory holes of the 3D semiconductor memory, the set being marked with respective values of dimensions; and
Machine learning is performed using the set and measurements collected during the inspection to determine values for the sizes of the respective memory apertures,
wherein the generating is performed without using a parameterized geometric model of the 3D semiconductor memory.
19. A non-transitory computer-readable storage medium storing one or more programs for execution by one or more processors of a computer system, the one or more programs comprising instructions for:
Based on inspection of an area of a semiconductor wafer containing multiple instances of a periodically arranged three-dimensional 3D semiconductor structure by a semiconductor metrology tool, a model of the respective instance of the 3D semiconductor structure is generated, comprising:
obtaining a set of measurements for different examples of the 3D semiconductor structure, the set being labeled with respective values of dimensions; and
Machine learning is performed using the set and measurements collected during the inspection to determine values of the dimensions for the respective examples,
wherein the generating is performed without using a parameterized geometric model of the 3D semiconductor structure, rendering an image of the model showing a 3D shape of the model; and
The image is provided to a device for display.
20. A method of visualizing a semiconductor structure, comprising:
in a semiconductor metrology tool:
inspecting, on a semiconductor wafer comprising at least one of semiconductor logic circuitry or semiconductor memory circuitry, an area of the semiconductor wafer comprising a plurality of instances of one three-dimensional 3D semiconductor structure periodically arranged in at least one dimension; and
In a computer system comprising one or more processors and a memory storing instructions for execution by the one or more processors:
Generating a model of a respective instance of the 3D semiconductor structure based on the inspection;
presenting an AR/VR image of the model showing a 3D shape of the model; and
Providing the AR/VR image to an AR/VR viewing device for display;
wherein generating the model of the respective instance of the 3D semiconductor structure comprises:
obtaining a set of measurements for different examples of the 3D semiconductor structure, the set being labeled with respective values of dimensions; and
Machine learning is performed using the set and measurements collected during the inspection to determine values of the dimensions for the respective examples,
wherein the generating is performed without using a parameterized geometric model of the 3D semiconductor structure.
21. The method of claim 20, wherein the AR/VR image is a first AR/VR image of the model presented from a first perspective, the method further comprising, after sending the first AR/VR image to the AR/VR viewing device for display:
receiving a user input requesting a change in viewing angle;
presenting a second AR/VR image of the model from a second perspective in response to the user input; and
The second AR/VR image is sent to the AR/VR viewing device for display.
22. The method of claim 20, wherein the AR/VR image is a first AR/VR image of the model having an appearance corresponding to values of parameters of the model as determined based on measurements collected during the inspection, the method further comprising, after sending the first AR/VR image to the AR/VR viewing device for display:
receiving a user input requesting a change in the value of the parameter;
applying the change to the value of the parameter for the model in response to the user input;
presenting a second AR/VR image having the model corresponding to the altered appearance; and
The second AR/VR image is sent to the AR/VR viewing device for display.
23. The method of claim 20, wherein the AR/VR image shows uncertainty for the 3D shape in the model.
24. The method of claim 20, wherein the AR/VR image indicates a deviation of the 3D shape or a cross section of the 3D shape from a nominal shape.
25. The method of claim 20, wherein the AR/VR image comprises an animation of the 3D shape that continuously shows a continuous portion of the 3D shape.
26. The method of claim 25, wherein the animation shows a rotation of the 3D shape.
27. The method of claim 20, wherein the presenting comprises superimposed data for the model on the AR/VR image.
28. The method according to claim 20, wherein:
the plurality of examples of the 3D semiconductor structure include a periodic arrangement of memory holes in a 3D memory; and is also provided with
The respective examples of the 3D semiconductor structure include respective memory holes.
29. The method of claim 28, wherein the AR/VR image shows an elliptical shape of the respective memory hole.
30. The method of claim 29, wherein the AR/VR image shows a helicity for the elliptical shape, wherein the helicity indicates a change in an orientation of the elliptical shape.
31. The method of claim 28, wherein the AR/VR image indicates a deviation from an elliptical shape for the respective memory hole.
32. The method of claim 28, wherein the AR/VR image shows a tilt of the respective memory hole.
33. The method according to claim 20, wherein:
The plurality of examples of the 3D semiconductor structure include a periodic arrangement of finfets; and is also provided with
The respective examples of the 3D semiconductor structure include a respective finFET or a portion of a respective finFET.
34. The method according to claim 20, wherein:
the plurality of examples of the 3D semiconductor structure include an array of DRAM cells; and is also provided with
The respective examples of the 3D semiconductor structure include respective DRAM cells or portions of respective DRAM cells.
35. The method of claim 20, wherein inspecting the region of the semiconductor wafer comprises performing an optical metrology technique selected from the group consisting of: spectroscopic ellipsometry, single wavelength ellipsometry, beam profile reflectometry, single wavelength reflectometry, angle resolved reflectometry, spectroscopic reflectometry, scatterometry, and raman spectroscopy.
36. The method of claim 20, wherein inspecting the region of the semiconductor wafer comprises performing small angle x-ray scattering.
37. A semiconductor inspection system, comprising:
a semiconductor metrology tool;
one or more processors; and
A memory storing one or more programs for execution by the one or more processors, the one or more programs comprising instructions for:
Generating a model of a respective instance of a periodically arranged three-dimensional 3D semiconductor structure based on inspection of a region of a semiconductor wafer containing the respective instance of the 3D semiconductor structure by the semiconductor metrology tool;
presenting an AR/VR image of the model showing a 3D shape of the model; and
Providing the AR/VR image to an AR/VR viewing device for display;
wherein generating the model of the respective instance of the 3D semiconductor structure comprises:
obtaining a set of measurements for different examples of the 3D semiconductor structure, the set being labeled with respective values of dimensions; and
Machine learning is performed using the set and measurements collected during the inspection to determine values of the dimensions for the respective examples,
wherein the generating is performed without using a parameterized geometric model of the 3D semiconductor structure.
38. A non-transitory computer-readable storage medium storing one or more programs for execution by one or more processors of a computer system, the one or more programs comprising instructions for:
generating a model of a respective instance of a periodically arranged three-dimensional 3D semiconductor structure based on inspection of a region of a semiconductor wafer containing the respective instance of the 3D semiconductor structure by a semiconductor metrology tool;
Presenting an AR/VR image of the model showing a 3D shape of the model; and
Providing the AR/VR image to an AR/VR viewing device for display;
wherein generating the model of the respective instance of the 3D semiconductor structure comprises:
obtaining a set of measurements for different examples of the 3D semiconductor structure, the set being labeled with respective values of dimensions; and
Machine learning is performed using the set and measurements collected during the inspection to determine values of the dimensions for the respective examples,
wherein the generating is performed without using a parameterized geometric model of the 3D semiconductor structure.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201862638721P | 2018-03-05 | 2018-03-05 | |
| US62/638,721 | 2018-03-05 | ||
| US16/283,690 | 2019-02-22 | ||
| US16/283,690 US10794839B2 (en) | 2019-02-22 | 2019-02-22 | Visualization of three-dimensional semiconductor structures |
| PCT/US2019/020470 WO2019173170A1 (en) | 2018-03-05 | 2019-03-04 | Visualization of three-dimensional semiconductor structures |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111837226A CN111837226A (en) | 2020-10-27 |
| CN111837226B true CN111837226B (en) | 2024-03-08 |
Family
ID=67846809
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201980016475.0A Active CN111837226B (en) | 2018-03-05 | 2019-03-04 | Visualization of three-dimensional semiconductor structures |
Country Status (5)
| Country | Link |
|---|---|
| JP (2) | JP7189959B2 (en) |
| KR (1) | KR102468979B1 (en) |
| CN (1) | CN111837226B (en) |
| TW (1) | TWI778239B (en) |
| WO (1) | WO2019173170A1 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11610297B2 (en) | 2019-12-02 | 2023-03-21 | Kla Corporation | Tomography based semiconductor measurements using simplified models |
| CN112384749B (en) | 2020-03-13 | 2022-08-19 | 长江存储科技有限责任公司 | System and method for semiconductor chip hole geometry metrology |
| US11798828B2 (en) * | 2020-09-04 | 2023-10-24 | Kla Corporation | Binning-enhanced defect detection method for three-dimensional wafer structures |
| CN113539877B (en) * | 2021-07-22 | 2023-10-17 | 长鑫存储技术有限公司 | Measuring device and measuring method for semiconductor structure |
| KR102554169B1 (en) * | 2021-10-06 | 2023-07-12 | (주)구일엔지니어링 | Inspection method for via-hole of the wafer |
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Also Published As
| Publication number | Publication date |
|---|---|
| JP2021516448A (en) | 2021-07-01 |
| JP2023025174A (en) | 2023-02-21 |
| KR102468979B1 (en) | 2022-11-18 |
| WO2019173170A1 (en) | 2019-09-12 |
| TW201945691A (en) | 2019-12-01 |
| JP7189959B2 (en) | 2022-12-14 |
| TWI778239B (en) | 2022-09-21 |
| CN111837226A (en) | 2020-10-27 |
| KR20200118905A (en) | 2020-10-16 |
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