JP7189959B2 - Visualization of 3D semiconductor structures - Google Patents

Description

TECHNICAL FIELD The present disclosure relates to semiconductor metrology and, more particularly, to generating visualizations showing three-dimensional (3D) properties of semiconductor structures.

Various types of metrics, such as various optical metrics and small-angle X-ray scattering (SAXS), can be used to characterize three-dimensional semiconductor structures. However, improper visualization of the resulting measurements can result in data being missed or underperceived. Such data can be important for debugging a semiconductor manufacturing process, improving the yield and reliability of that process, or predicting the performance of semiconductor devices. Inadequate visualization also makes comparison with reference data difficult, such as data obtained with critical dimension scanning electron microscopy (CD-SEM) and transmission electron microscopy (TEM).

U.S. Patent Application Publication No. 2009/0296073 U.S. Patent Application Publication No. 2016/0350445 U.S. Patent Application Publication No. 2016/0307116

Accordingly, there is a need for improved techniques for visualizing 3D semiconductor structures. Examples of such structures include, but are not limited to, memory holes, finFETs and DRAM cells in 3D memory (eg, 3D flash memory).

A semiconductor structure visualization method according to some embodiments inspects an area of a semiconductor wafer in a semiconductor metrology tool. The semiconductor wafer may include at least one of a semiconductor logic circuit and a semiconductor memory circuit. The area to be inspected has a plurality of instances (structures) of the 3D semiconductor structure where they are periodically arranged in at least one dimension. In this method, in a computer system comprising one or more processors and a memory storing instructions to be executed by the one or more processors, based on the inspection, the 3D semiconductor Generate models for individual instances of structures. The method further includes rendering in the computer system an image of the model showing the 3D shape of the model and providing the image to a device for display.

A semiconductor inspection system according to some embodiments includes a semiconductor metrology tool and a computer system, wherein the computer system is executed by one or more processors and the one or more processors. and a memory in which one or more programs are stored. The one or more programs contain instructions for performing all or part of the methods described above. A non-transitory computer-readable storage medium according to some embodiments stores one or more programs configured to be executed by a computer system. The one or more programs contain instructions for performing all or part of the methods described above.

For a better understanding of the various embodiments described, reference should be made to the detailed description below in conjunction with the following drawings.

FIG. 4 is a graph showing the variation of the CD profile of a memory hole along its depth; FIG. 4 is a graph showing the slope of a memory hole along its depth; 4 is a flowchart of a semiconductor structure visualization method according to some embodiments; FIG. 3 is an isometric image of a modeled slice of a 3D semiconductor memory device having a plurality of memory holes, according to some embodiments. FIG. 10 is an isometric image of a modeled portion of two finFETs, according to some embodiments; FIG. 10 illustrates an image of a modeled memory hole rendered from a viewing angle, according to some embodiments; FIG. 10 illustrates images of a modeled memory hole rendered from another viewing angle, according to some embodiments; FIG. 10 illustrates images of a modeled memory hole rendered from another viewing angle, according to some embodiments; FIG. 10 illustrates images of a modeled memory hole rendered from another viewing angle, according to some embodiments; [0014] FIG. 4 illustrates a perspective exterior image of a modeled memory hole, according to some embodiments; [0014] FIG. 5 illustrates a perspective exterior image of another modeled memory hole, according to some embodiments. [0014] FIG. 5 illustrates images including a perspective view of a modeled memory hole and cross-sections of the model at various depths, according to some embodiments. [0014] FIG. 4 illustrates a skeletal view of a modeled memory hole, according to some embodiments; [0014] FIG. 4B illustrates a skeleton view of another modeled memory hole, in accordance with some embodiments; [0014] FIG. 4B illustrates a skeleton view of another modeled memory hole, in accordance with some embodiments; FIG. 4B shows an opaque image of a modeled volume in a semiconductor with memory holes, according to some embodiments. [0014] FIG. 5 is a semi-transparent image of a modeled volume in a semiconductor with memory holes, according to some embodiments; [0014] FIG. 4 illustrates an image including a bottom surface and a user-selectable cross-section of a modeled memory hole, according to some embodiments; 1 is a block diagram of a semiconductor inspection system according to some embodiments; FIG.

Like reference numerals refer to corresponding parts throughout the drawings and specification.

Reference will now be made in detail to various embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the various described embodiments. However, as will be apparent to those skilled in the art (so-called skilled artisans), the various described embodiments may be practiced without these specific details. In other instances, well-known methods, procedures, components, circuits and networks have not been described in detail so as not to unnecessarily obscure aspects of the embodiments.

FIG. 1A shows a graph 100 of the variation of the critical dimension (CD) profile (eg, diameter) of a memory hole along its depth. A memory hole extends vertically through a three-dimensional (3D) semiconductor memory structure (eg, 3D flash memory), and the vertical direction (z-axis in other figures) corresponds to depth. CD profiles are measured in nanometers (nm). Graph 100 corresponds to a vertical cross section of the memory hole.

FIG. 1B shows a graph 110 of the slope of a memory hole along its depth. Ideally, the slope should be zero so that a straight vertical line appears on this graph. However, in reality, any given depth of a memory hole will exhibit an offset relative to the hole at its surface. The tilt is the measurement of this offset in nanometers. The slope at a given depth is obtained by measuring the offset between a specific point on the surface of the memory hole (e.g. its center, a specific point on its periphery, etc.) and the corresponding point at its depth. can decide.

The low dimensionality of graphs 100 and 110, each showing parameter variation along some single dimension, limits the information they carry. Both graphs 100 and 110 provide only a limited indication of the shape of the memory hole. A more robust visualization method that solves this problem by providing a 3D shape sensation of memory holes and other semiconductor structures will be described below.

FIG. 2 shows a flowchart of a semiconductor structure visualization method 200 according to some embodiments. The method 200 creates an image showing the 3D shape, thereby eliminating the shortcomings of the graphs 100 and 110 (FIGS. 1A and 1B). The method 200 will be described with reference to FIGS. 3A-8B, and in those figures will be given examples of images showing the 3D shape of a semiconductor structure (strictly speaking, the images shown by those images are the same). are models of the semiconductor structure, and as described below, those models are generated based on the results of semiconductor metrology). The steps in method 200 may be combined or decomposed.

In the method 200, an area of a semiconductor wafer is inspected (202) using a semiconductor metrology tool (eg, metrology tool 1032, FIG. 10). The semiconductor wafer has at least one of a semiconductor logic circuit and a semiconductor memory circuit. The circuit may be only partially fabricated at the time of inspection. The inspected area is an area containing multiple instances of the 3D semiconductor structure, which are periodically arranged in at least one dimension (eg, unidimensionally or two-dimensionally). Optical metrology or small angle X-ray scattering (SAXS) may be performed 204 to inspect this area. Among the examples of optical metrology techniques that may be performed are spectroscopic ellipsometry (elliptical deflection), single wavelength ellipsometry, beam profile ellipsometry, beam profile reflectometry (reflection metrology), single wavelength reflectometry, angle resolved reflectometry. spectrometry, spectroscopic reflectometry, scatterometry and Raman spectroscopy. Transmission SAXS, reflection SAXS and grazing incidence SAXS are among the examples of SAXS techniques that may be implemented.

In some embodiments, the 3D semiconductor structure is a memory hole in a 3D memory (e.g., 3D flash memory), a fin field effect transistor (finFET) or portion thereof, or a dynamic random access memory (DRAM) cell or portion thereof. be done. A memory hole may be inspected when it is empty (eg, after etching but before filling), when it is filled, or at some intermediate step between etching and full filling. Similarly, inspection of other structures may be performed at various steps during their manufacturing process. Thus, the area under test can include a periodic array of memory holes in a 3D memory, a periodic array of finFETs, or an array of DRAM cells (206). Alternatively, other 3D semiconductor structures may be inspected.

Steps subsequent to steps 202, 204 and/or 206 (i.e., step 208 onwards) are performed in a computer system (e.g., computer system of semiconductor inspection system 1000, FIG. 10) communicatively coupled to the metrology tool. be.

Based on the metrology results collected during inspection step 202, models of individual instances of the 3D semiconductor structure are generated (208). In some embodiments, the individual instances are or include individual memory holes, individual finFETs or portions thereof, or individual DRAM cells or portions thereof, according to step 206 .

In some embodiments, a geometric model of the 3D semiconductor structure with parameterized dimensions (ie, a parameterized geometric model) is obtained 210 to generate the model. The geometric model may also include information about material properties, resulting in a parameterized geometric/material model. The parameterized geometric model (eg, geometry/material model) is typically pre-generated prior to the checking step 202 . Using the metrology results collected during the inspection step 202, the values of these parameterized dimensions are determined (212). The determination can be made by performing a regression on the parameters of the geometric model (eg, geometric/material model). For example, using a machine learning model trained using a training set of real and/or simulated measurement results for which the corresponding parameter values for the parameterized geometric model (e.g., geometric/material model) have been determined It can be performed.

In some other embodiments, a set of measurements (real and/or simulated) are obtained 214 for the varying instance of the 3D semiconductor structure to generate the model. Each set is labeled with its respective dimension value. When performing machine learning, the measurement results collected during the inspection step 202 and the set thereof can be used to determine 216 the value of the dimension associated with that individual instance. A parameterized geometric model of the 3D semiconductor structure is not used.

An image of the model showing the 3D shape of the model is rendered (218). The image shows the partial 3D shape of the model, for example as a result of one or more surfaces and/or sides being hidden or omitted and/or the number of cross-sections included in the image being constrained. It may be Alternatively, the image may show the full 3D shape of the model, for example using augmented or virtual reality (AR/VR) or holography. The models and images may be voxelized so that they are constructed using voxels (solid elements that are the 3D equivalent of pixels). The image is provided 224 to a device for display. In one example, the image is provided to a display screen (eg, display 1008, FIG. 10) of the computer system performing steps 208-224. In another example, the image is transmitted to another electronic device (e.g., a client computer or mobile electronic device having a display, an AR/VR viewer, a 3D stereoscopic viewer, a holographic display system, etc.) for display. be done. According to yet another example, the 3D shape of the model can be presented by transmitting the image to a 3D printer, where an object having the shape of the model is additionally manufactured.

In some embodiments, the image includes a projection image for two-dimensional (2D) display (220). For example, the projections can be axonometric projections (eg, conformal, biconformal, or axonometric) showing multiple sides of the model. That is, the dimensions of the projection may share a common scale or have different scales. The projection will show the 3D shape of the model while being displayed in 2D (although some sides and/or surfaces may be occluded by visible sides and/or surfaces, so embodiments may not be the entire 3D shape).

FIG. 3A shows an isometric image 300 of a modeled slice 304 of a 3D semiconductor memory device (eg, 3D flash memory) having a plurality of memory holes 302-1 through 302-7, according to some embodiments. indicates Slice 304 comprises a plurality of layers (eg, a series of alternating oxide ( _SiO2 ) and nitride _{( Si3N4} ) layers) through which memory holes 302 extend vertically. be able to. In image 300, only the 2D top view of memory holes 302-1, 302-4 and 302-7 are shown, while cutaway views of memory holes 302-2, 302-3, 302-5 and 302-6 are shown. It is A cutaway view of memory holes 302-3 and 302-6 shows the 3D shape of the back half relative to the plane fragmenting them. Image 300 is thus an example image of step 220 . The 3D shape of memory holes 302-3 and 302-6 can be represented using contour lines (as in FIG. 3A), shading, coloring, or any other graphical technique suitable for 2D projection of 3D objects. good.

FIG. 3B shows an isometric image 350 of modeled portions of two finFETs, according to some embodiments. The first finFET has channel 352-1 and the second finFET has channel 352-2. A gap 354 separating the channels 352 separates the two finFETs. Show the 3D shape of those structures using outlines (as in FIG. 3B), shading, coloring, or other suitable graphical technique, as was the case with memory holes 302-3 and 302-6 in FIG. 3A. be able to. Image 350 is another example of the image of step 220 .

As shown in images 300 and 350, the images of steps 218 and 224 may show the 3D shape of multiple instances of a semiconductor structure or portions thereof (eg, multiple instances of memory holes 302 or channels 352). .

According to some embodiments, the viewing angle of the image can be changed in response to user input 226 . FIG. 4A shows an image 400A of a modeled memory hole rendered from a first viewing angle, according to some embodiments. Image 400A from a first viewing angle shows the top surface 402 and front surface 404 of the memory hole. Image 400A shows the 3D curvature of front surface 404, where the use of contour lines (or shading, coloring, etc.) shows the 3D shape of that memory hole. The bottom surface 406 and back surface of this memory hole are occluded at this viewing angle. In response to receiving user input 226 specifying a viewing angle change, the computer system executing method 200 renders 218 a new image 400B, 400C or 400D from the changed viewing angle, and renders 218 the new image 400B, 400C or 400D is provided 224 to the user's device for display (alternatively, the new image may be rendered and stored prior to user input 226 and provided in response to the user input 226). Performing this process iteratively allows the user to view the memory hole from multiple viewing angles (eg, and thus view images 400B, 400C and/or 400D). For example, the user can rotate the drawing of the memory hole along a specified direction. Image 400B is a side view showing the 3D curvature of front surface 404 but not top surface 402, bottom surface 406 and rear surface. Image 400C is a bottom view, only bottom 406 is shown. Image 400D is a top view, only top 402 is shown. Images 400C and 400D are not examples of images in step 218 because they do not show 3D geometry, but they would if turned slightly to reveal side surfaces or portions thereof.

According to some embodiments, instead of changing the viewing angle at which the image is rendered, the model itself changes in response to user input 226 (e.g., arrow line labeled "user input 226"). (the tip returns to step 208 instead of step 218). For example, user input 226 may specify changes to one or more dimensions (eg, distances) or angles of the model for that individual instance. The model is updated according to its user input 226 and no longer corresponds to the measurements collected during the inspection of step 202 . An image of the updated model is then rendered and sent to the user's device for display. This modification allows the user to see how much margin the semiconductor structure has before reaching the point of failure (eg, shorting neighboring conductive structures). The update(s) to the model may be indicated by annotating the image of the updated model (eg, indicating changes to its dimensions, changes to one or more angles, etc.). Annotations may be user-driven (eg, may display specified distances or angles according to user input 226).

FIG. 5A shows a perspective appearance image 500 of a modeled memory hole, according to some embodiments. Similar to image 400A (FIG. 4A), image 500 shows the top surface 502 of the memory hole and the 3D curvature of the front surface 504. FIG. However, unlike image 400A, where the memory hole was not tilted (i.e., its tilt was substantially zero and the memory hole was substantially straight along the vertical direction), image 500 has a tilted memory hole. are also appearing. The top of the memory hole in image 500 is slanted downward at an oblique angle, up to a bend 506 in the middle of the memory hole, where the memory hole bends toward the vertical direction. The bottom of this memory hole extends downward without substantial inclination. As discussed with respect to FIG. 1B, if the slope is defined as an offset to the top surface, the slope of the bottom portion below the bend 506 will be substantially constant.

FIG. 5B shows a perspective exterior image 550 of another modeled memory hole, according to some embodiments. Similar to images 400A (FIG. 4A) and 500 (FIG. 5), image 550 shows the top surface 552 of the memory hole and the 3D curvature of the front surface 554. FIG. Image 550 shows that its top surface 552 is elliptical. As the shape of the front surface 554 suggests, this memory hole extends downward while maintaining its elliptical shape.

In some embodiments in which the individual instances of the 3D semiconductor structure are individual memory holes, the image indicates that the individual memory holes are elliptical in relation to multiple cross-sections (e.g., horizontal cross-sections) of the memory holes. shown. The image may also show the helicity of the individual memory holes and/or the slope of the memory holes for the multiple cross-sections. Helicity is a measure of the change in orientation of the ellipse, the degree of rotation (e.g. degrees or radians) of the major axis (or equivalently the minor axis) of the ellipse with respect to its top surface. that measured in units). For example, FIG. 6 shows a perspective view (here, side view 602) of a modeled memory hole and cross-sections 606-1 through 606-6 of that memory hole at various depths, according to some embodiments. A containing image 600 is shown. Arrow line 604 between side view 602 and individual cross-section 606 indicates the depth associated with that individual cross-section 606 . The cross-sections 606 show the size (eg CD) and elliptical shape of the memory hole at various depths. The cross-sections 606 also show the helicity of the memory hole at various depths, with the ellipse of cross-section 606 also turning as the depth increases. The memory holes in FIG. 6 are substantially non-tilted, but if there is a tilt, the cross section 606 also shows the tilt, e.g. You could do that by specifying the offset.

In some embodiments, the image displays, eg, highlights, deviations from the ellipse for the multiple cross-sections. For example, a particular cross-section 606 may not be precisely elliptical. Highlight (e.g., with a particular color, shape, or fill pattern) those portions of the cross-section that deviate from the ellipse (e.g., run outside the ellipse or miss the edge of the ellipse) be able to. More generally, the image can display, eg highlight, the extent to which the 3D shape, or a portion (eg, cross-section), deviates from the nominal shape. Memory holes and ellipses are but one example of individual structures and nominal shapes whose deviations can be displayed. Other examples are possible.

According to some embodiments, the cross-sections are shown to appear side-by-side along an axis (e.g., the z-axis corresponding to depth) and that axis intersects the plane of the paper obliquely (i.e., at an oblique angle). can be made visible by This arrangement allows the cross-sections to partially overlap (eg, individual cross-sections partially occlude subsequent cross-sections).

In some embodiments, the image represents a skeletal view of the model, i.e., cross-sections joined by contour lines (e.g., where the contour lines meet corresponding points on the perimeter of each cross-section). shall be included. The skeleton view shows the 3D shape of the model (although not the entire 3D shape due to the limited number of cross-sections and contours) and can still be displayed in 2D. 7A-7C show skeleton view images 700, 720 and 740 of modeled memory holes, according to some embodiments.

In image 700, cross-sections 702-1 through 702-5 are connected by contour lines 704-1 and 704-2. The cross-sections 702 are elliptical, as indicated by the major and minor axes of the ellipses associated with the cross-sections 702 . The elliptical shape of the memory hole, which is quantified by its ellipticity (e.g. ratio of the lengths of the major and minor axes), is the depth and depth, as is the CD of the memory hole and hence its size. is kept constant in relation to This memory hole is not spiral and the ellipse of the cross-sections 702 is not rotated with depth. However, the memory holes do slope, and the slope varies with depth, as shown by the curvature of contour lines 704-1 and 704-2.

In image 720, cross-sections 722-1 through 722-5 are connected by contour lines 724-1 and 724-2. Its elliptical shape, and thus its ellipticity, changes with depth, increasing the length of the minor axis to become the major axis. The size of a memory hole, and thus its CD, changes drastically in relation to depth. However, the ellipses do not rotate, indicating a lack of helicity.

In image 740, cross-sections 742-1 through 742-4 are connected by contour lines 744-1 and 744-2. Although the ellipticity and CD of the cross-sections 742 are kept constant, the memory holes exhibit helicity and the ellipses of the cross-sections 742 turn as the depth increases. You can see that the axes of those ellipses are rotating.

Thus, the use of multiple cross-sections can provide extensive information about the 3D geometry, as shown in FIGS. 6 and 7A-7C.

8A and 8B show images 800 and 810 of a modeled volume 802 in a semiconductor, according to some embodiments. Within this volume 802 are memory holes 804-1, 804-2 and 804-3, which can be part of a periodic 2D array of memory holes. Volume 802 is shown as opaque in image 800 . Image 800 shows the top surface of memory hole 804-1, a portion of the top surface of memory hole 804-2, and a portion of the top surface of memory hole 804-3 along with the vertical cross-sectional profile of memory hole 804-3. It is shown. In image 810, volume 802 is translucent, revealing the 3D shape of all three memory holes 804-1, 804-2 and 804-3. Thus, while both images 800 and 810 show at least a partial 3D shape of at least one semiconductor structure (as modeled in step 208), image 810 shows more than image 800. also shows quite a lot of 3D information.

In some embodiments, the image includes at least one of a top surface and a bottom surface of a modeled discrete instance of the 3D semiconductor structure, and between the top and bottom surfaces of the modeled 3D semiconductor structure. It is intended to contain user-selectable cross-sections of individual instances (eg, horizontal cross-sections perpendicular to the vertical z-axis). For example, FIG. 9 shows an image 900 including a bottom surface 902 and a user-selectable cross-section 904 of a modeled memory hole, according to some embodiments. User selectable cross section 904 may be translucent. The vertical position of the user-selectable cross-section 904 can be changed based on user input 226 (e.g., steps in computer performing method 200 in response to user input 226 specifying a new vertical position). Repeating 218 and 220 may render and present a new image with the user-selectable cross-section 904 at its new explicit vertical position). By presenting multiple cross-sections (i.e., top and/or bottom and user-selectable cross-sections), the image can represent the 3D shape of the model (although not the entire 3D shape due to the limited number of cross-sections and contours). The image may be intended for 2D display while being shown. According to some embodiments, the image may include a plurality of user-selectable cross-sections, one or more (eg, all) of which may be translucent.

In some embodiments, the image is or includes an AR/VR image or a 3D stereoscopic image (222). The device to which the image is provided in step 224 can thus be an AR/VR viewing device (eg, AR/VR goggles, AR glasses) or a 3D stereoscopic viewer.

For example, let the AR/VR image be the first AR/VR image of the model rendered from a first viewing angle. The method 200 further accepts user input 226 requesting a change in viewing angle after sending the first AR/VR image to the AR/VR viewing device for display. A second AR/VR image of the model can be rendered from a second viewing angle by repeating step 222 in response to the user input. The second AR/VR image is sent to the AR/VR viewing device for display at step 224 . By doing so, the user can effectively move around the image in AR/VR.

Also for example, the AR/VR image is the first AR/VR image of the model and has an appearance corresponding to parameter values of the model, where the parameter values correspond to measurements collected during the inspection of step 202. It is assumed that the image is determined based on The method 200 also accepts user input 226 requesting changes to the parameter values after the first AR/VR image is sent to the AR/VR viewing device for display. In response to the user input, the parameter values associated with the model are changed, and at step 222 a second AR/VR image of the model is rendered with an appearance corresponding to the changed values. The second AR/VR image is sent to the AR/VR viewing device for display at step 224 . In this way, the user can examine potential variations in the 3D shape of the semiconductor structure (eg, how much margin the semiconductor structure has before reaching the point of failure).

In some embodiments, the image generated according to the method 200 shows (eg, highlights) the 3D shape uncertainty according to the model of step 218 . For example, to the extent that there is uncertainty in its CD, the uncertainty region on the edge (e.g., along the wall of the memory hole) of the associated modeled semiconductor structure instance is different from the rest of the associated modeled semiconductor structure instance. The uncertainty can be indicated in the precise location of the edge by showing it with color, shading, or a fill pattern. A blur (eg, that of the edge) or a dot may be used to indicate uncertainty. Animating according to the uncertainty may indicate that the 3D shape may change within some probability range (eg, edge positions may change). Other examples are possible.

The above indicators, such as slope, ellipticity, deviation from a nominal shape (eg, ellipse), and helicity, are only examples of indicators that may be shown in images generated using the method 200. FIG. Other indices (eg, derivative indices, indices generated using Fourier transforms, etc.) may be presented in addition or instead.

In some embodiments, the image generated according to the method 200 includes an animation showing successive parts of the 3D shape in sequence. For example, the animation can show successive cross-sections, eg, cross-sections of increasing or decreasing depth. Also for example, the animation shows the rotation of the 3D shape with successive parts entering and leaving the field of view.

According to some embodiments, data for the model can be superimposed on the image of the model so that the superimposed data can be included in the image provided to the user's device in step 224. . The data can include numerical values that specify the value of one or more parameters/indicators for the model. The data can include vectors that characterize the electric field or strain. Other examples are possible.

The images shown in FIGS. 3A-8B are only examples of 3D visualization techniques that may be used in the method 200. FIG. Other examples are possible. According to some embodiments, the images produced by the method 200 can be used to predict the performance of semiconductor devices. According to some embodiments, the images produced by the method 200 can be used for comparison with reference images (eg, CD-SEM or TEM images). According to some embodiments, the images produced by the method 200 can be used to identify process or design changes.

FIG. 10 is a block diagram of a semiconductor inspection system 1000 according to some embodiments. The semiconductor inspection system 1000 includes a semiconductor metrology tool 1032 and a computer system that includes one or more processors 1002 (eg, CPU and/or GPU), optional user interface 1006, memory 1010, and one or more communication buses 1004 connecting between these members. The computer system can be communicatively coupled to weighing tools 1032 via one or more networks 1030 . The computer system may also have one or more network interfaces (wired and/or wireless, not shown) for communication with weighing tool 1032 and/or remote computer systems. In some embodiments, the metrology tool 1032 performs optical metrology and/or SAXS.

User interface 1006 may include display 1008 and/or one or more input devices (eg, keyboard, mouse, touch-sensitive surface of display 1008, etc.). The display 1008 may display images of the method 200 according to some embodiments.

Memory 1010 includes volatile and/or nonvolatile memory. Memory 1010 (eg, non-volatile memory within memory 1010) includes non-transitory computer-readable storage media. Memory 1010 includes, but is not required to include, one or more storage devices remotely located relative to processor 1002 and/or non-transitory computer-readable storage media removably inserted into the computer system. is doing. In some embodiments, operating system 1012, model generation module 1014, model update module 1016, image rendering module 1018, and image transmission module 1020 contain procedures to handle various basic system services and to perform hardware dependent tasks. , and database 1022 of measurement results collected from metrology tool 1032, or a subset or superset thereof, are stored in memory 1010 (eg, a non-transitory computer-readable storage medium in memory 1010).

Accordingly, within memory 1010 (eg, a non-transitory computer-readable storage medium in memory 1010) are instructions for cooperating with metrology tool 1032 to perform method 200 (FIG. 2). Each module stored in memory 1010 represents a set of instructions for performing one or more functions described herein. Separate modules need not be implemented as separate software programs. The modules, as well as various subsets of the modules, may be rearranged, eg combined. In some embodiments, a subset or superset of the modules and/or data structures noted above are stored in memory 1010 .

Figure 10 is intended as a functional description of various features that may be inherent in a semiconductor inspection system rather than as a structural diagram. For example, the functionality of the computer system in the semiconductor inspection system 1000 may be shared among multiple devices. A portion of the modules stored in memory 1010 may, alternatively, be one or more communicatively coupled to the computer system of semiconductor inspection system 1000 via one or more networks. may be stored in the computer system of

In the foregoing description, for purposes of explanation, reference is made to specific embodiments. However, the illustrative discussion above is not meant to be exclusive, nor is it intended to limit the scope of the claims to the precise forms disclosed. Various modifications and variations may be made within the scope of the above disclosure. The embodiments best describe the principles underlying the claims and their practical applications, and thus may be implemented by those skilled in the art with various modifications as appropriate for the particular applications envisioned. It is chosen for the purpose of making the form suitable for use.

Claims (23)

A semiconductor structure visualization method,
In semiconductor weighing tools,
On a semiconductor wafer having at least one of a semiconductor logic circuit and a semiconductor memory circuit, an area of the semiconductor wafer in which a plurality of instances of a three-dimensional (3D) semiconductor structure are periodically arranged in at least one dimension. inspect and
In a computer system comprising one or more processors and a memory storing instructions executed by the one or more processors,
generating models of individual instances of the 3D semiconductor structure in light of the inspection;
an augmented reality or virtual reality (AR/VR) image of the model, rendering an AR/VR image showing the 3D shape of the model, and providing said AR/VR image to an AR/VR display device for display. do,
Method. 2. The method of claim 1, wherein the AR/VR image is a first AR/VR image rendering the model from a first viewing angle, further comprising: After sending to the AR/VR display ,
receiving user input requesting a change in viewing angle;
Rendering a second AR/VR image of the model from a second viewing angle in response to the user input, and sending the second AR/VR image to the AR/VR display device for display.
Method. 2. The method of claim 1, wherein the AR/VR image is the first AR/VR image of the model, the appearance of which is determined based on measurements collected during the inspection. after the method further sends the first AR/VR image to the AR/VR display device for display, corresponding to a value of
receiving user input requesting a change to the value of said parameter;
changing the values of the parameters associated with the model according to the user input;
Rendering a second AR/VR image of the model with an appearance corresponding to the modification, and sending the second AR/VR image to the AR/VR display device for display.
Method. 2. The method of claim 1, wherein the AR/VR image shows uncertainty of the 3D shape in the model. 2. The method of claim 1, wherein the AR/VR image shows deviations of the 3D shape or cross-sections of the 3D shape from a nominal shape. 2. The method of claim 1, wherein the AR/VR image includes an animation showing successive portions of the 3D shape. 7. The method of claim 6, wherein the animation shows rotation of the 3D shape. 2. The method of claim 1, wherein said rendering includes overlaying data about said model onto said AR/VR image. 2. The method of claim 1, wherein
said plurality of instances of said 3D semiconductor structure comprising a periodic array of memory holes in a 3D memory, and said individual instances of said 3D semiconductor structure comprising individual memory holes;
Method. 10. The method of Claim 9, wherein the AR/VR image shows an elliptical shape of the individual memory holes. 11. The method of claim 10, wherein the AR/VR image indicates helicity of the individual memory holes, the helicity indicating changes in orientation of the elliptical shape. 10. The method of claim 9, wherein the AR/VR image exhibits deviations from an elliptical shape for the individual memory holes. 10. The method of Claim 9, wherein the AR/VR image shows the slope of the individual memory holes. 2. The method of claim 1, wherein
said plurality of instances of said 3D semiconductor structure comprising a periodic array of finFETs, and said individual instances of said 3D semiconductor structure comprising individual finFETs or portions of individual finFETs;
Method. 2. The method of claim 1, wherein
said plurality of instances of said 3D semiconductor structure comprising an array of DRAM cells, and said individual instances of said 3D semiconductor structure comprising individual DRAM cells or portions of individual DRAM cells;
Method. 2. The method of claim 1, wherein generating models of the individual instances of the 3D semiconductor structure comprises:
obtaining a geometric model of the 3D semiconductor structure with parameterized dimensions; and using metrology results collected during said inspection to determine values of those parameterized dimensions. 2. The method of claim 1, wherein generating models of the individual instances of the 3D semiconductor structure comprises:
Obtaining a set of measurements for varying instances of the 3D semiconductor structure, labeling the sets with individual dimension values, and performing machine learning using the sets and the measurements collected during the inspection. determining a dimension value associated with the individual instance by
A method of performing said model generation without using a parameterized geometric model of said 3D semiconductor structure. 2. The method of claim 1, wherein inspecting an area of the semiconductor wafer comprises spectroscopic ellipsometry, single wavelength ellipsometry, beam profile ellipsometry, beam profile reflectometry, single wavelength reflectometry, angular resolution. performing an optical metrology technique selected from the set consisting of reflectometry, spectroscopic reflectometry, scatterometry and Raman spectroscopy. 2. The method of claim 1, wherein inspecting the area of the semiconductor wafer comprises performing small-angle X-ray scattering. A semiconductor inspection system,
a semiconductor weighing tool;
one or more processors;
a memory storing one or more programs executed by the one or more processors;
wherein the one or more programs comprise:
instructions to generate a model of an individual instance of a three-dimensional (3D) semiconductor structure based on inspection by the semiconductor metrology tool of an area of a semiconductor wafer in which multiple instances of the three-dimensional (3D) semiconductor structure are periodically arranged;
an augmented reality or virtual reality (AR/VR) image of the model, instructions to render an AR/VR image showing the 3D shape of the model, and instructions to render the AR/VR image to an AR/VR display device for display. order to supply,
semiconductor inspection system including; A non-transitory computer-readable storage medium storing one or more programs executed by one or more processors in a computer system, wherein the one or more programs are
instructions to generate a model of an individual instance of a three-dimensional (3D) semiconductor structure based on inspection by a semiconductor metrology tool of an area of a semiconductor wafer in which multiple instances of the three-dimensional (3D) semiconductor structure are periodically arranged;
an augmented reality or virtual reality (AR/VR) image of the model, instructions to render an AR/VR image showing the 3D shape of the model, and instructions to render the AR/VR image to an AR/VR display device for display. order to supply,
A non-transitory computer-readable storage medium comprising: A non-transitory computer-readable storage medium storing one or more programs executed by one or more processors of a computer system, the one or more programs comprising:
generating models of individual instances of a three-dimensional (3D) semiconductor structure based on inspection by a semiconductor metrology tool of an area of a semiconductor wafer in which multiple instances of the three-dimensional (3D) semiconductor structure are periodically arranged;
rendering a first augmented reality or virtual reality (AR/VR) image of the model, the first AR/VR image showing a 3D shape of the model from a first viewing angle;
providing the first A R/VR image to an AR/VR display for display;
contains instructions for
After sending the first AR/VR image to the AR/VR display device for display,
receiving user input requesting a change in viewing angle;
Rendering a second AR/VR image of the model from a second viewing angle in response to the user input;
providing the second AR/VR image to the AR/VR display device for display;
A non-transitory computer-readable storage medium. A non-transitory computer-readable storage medium storing one or more programs executed by one or more processors of a computer system, the one or more programs comprising:
generating models of individual instances of a three-dimensional (3D) semiconductor structure based on inspection by a semiconductor metrology tool of an area of a semiconductor wafer in which multiple instances of the three-dimensional (3D) semiconductor structure are periodically arranged;
a first augmented reality or virtual reality (AR/VR) image of the model, the appearance of which corresponds to values of parameters of the model determined based on measurements collected during the inspection; Render the VR image,
providing the first AR/VR image to an AR/VR display device for display;
receiving user input requesting a change to the value of the parameter after sending the first AR/VR image to the AR/VR display device for display;
changing values of the parameters associated with the model in response to the user input;
Rendering a second AR/VR image of the model having an appearance corresponding to the modified values;
providing the second AR/VR image to the AR/VR display device for display;
A computer-readable storage medium containing instructions for

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