CN111835355B - Time interval digital converter with high repetition rate based on TDC - Google Patents

Time interval digital converter with high repetition rate based on TDC Download PDF

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CN111835355B
CN111835355B CN202010710991.8A CN202010710991A CN111835355B CN 111835355 B CN111835355 B CN 111835355B CN 202010710991 A CN202010710991 A CN 202010710991A CN 111835355 B CN111835355 B CN 111835355B
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trigger
tda
tdo
gate
output
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CN111835355A (en
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安永泉
禹健
王萌洁
李晋华
王志斌
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North University of China
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North University of China
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention belongs to the technical field of time interval measurement, and particularly relates to a time interval digital converter with high repetition rate based on a TDC (time-to-digital converter), which comprises a TDC circuit and a TAC circuit, wherein the TDC circuit comprises a first comparator, a second comparator, a first trigger, a second trigger, a third trigger, a fourth trigger, a fifth trigger, a sixth trigger, a seventh trigger, an eighth trigger, a ninth trigger and a tenth trigger, the positive end of the first comparator is connected with a starting voltage, the negative end of the first comparator is connected with a threshold voltage, and the output end of the first comparator is connected with a CP control end of the first trigger. The TDC circuit does not need to carry out special reset operation, and solves the problems that in the prior art, an analog interpolation method based on a time-amplitude conversion principle is adopted to measure time intervals, a measurement result is sensitive to temperature, and the measurement reaction speed of the circuit is slower during continuous measurement. The invention is used for measuring the time interval.

Description

Time interval digital converter with high repetition rate based on TDC
Technical Field
The invention belongs to the technical field of time interval measurement, and particularly relates to a time interval digitizer with high repetition rate based on TDC.
Background
The traditional time interval digital converter mostly adopts an analog interpolation method based on a time-amplitude conversion principle to realize time interval measurement, the principle is to convert the time length into amplitude height, a direct counting method and a time-amplitude conversion principle are combined to realize time interval measurement with wide range and high resolution, and then the time interval to be measured is output in a digital mode through a TDC circuit.
However, the conventional high resolution time interval measurement technique has the following problems in measuring the time interval: 1) When continuous measurement is carried out, the traditional TDC circuit carries out analog-digital conversion on the voltage through the ADC circuit each time, and then special reset is carried out, so that the next time interval digital conversion can be carried out, and the conversion rate is lower in unit time; 2) When measuring in long distance, drift phenomenon exists; 3) The measurement is temperature sensitive.
Disclosure of Invention
Aiming at the technical problems that the traditional high-resolution time interval measurement technology has lower conversion rate in unit time, has drift phenomenon in long-distance measurement and the measurement result is sensitive to temperature, the invention provides the time interval digital converter based on the TDC with wide measurement range, high precision and high speed.
In order to solve the technical problems, the invention adopts the following technical scheme:
the time interval digital converter based on the TDC comprises a TDC circuit and a TAC circuit, wherein the TDC circuit comprises a first comparator, a second comparator, a first trigger, a second trigger, a third trigger, a fourth trigger, a fifth trigger, a sixth trigger, a seventh trigger, an eighth trigger, a ninth trigger and a tenth trigger, the positive end of the first comparator is connected with a starting voltage, the negative end of the first comparator is connected with a threshold voltage, the output end of the first comparator is connected with the CP control end of the first trigger, the Q end of the first trigger is connected with the D end of the second trigger, and the Q end of the second trigger is connected with the D end of the third trigger; the positive end of the second comparator is connected with an end voltage, the negative end of the second comparator is connected with a threshold voltage, the output end of the second comparator is connected with a CP control end of a fourth trigger, the Q end of the fourth trigger is connected with the D end of a fifth trigger, and the Q end of the fifth trigger is connected with the D end of a sixth trigger; the Q end of the first trigger is connected with one input end of the first exclusive-OR gate, and the other input end of the first exclusive-OR gate is respectively connected with the Q end of the second trigger and the Q end of the third trigger through a first multi-way switchThe D end of the first trigger is connected with the Q end of the second trigger and the Q end of the third trigger respectively through a second multi-way switch, the D end of the fourth trigger is connected with the Q end of the fourth trigger and a fourth multi-way switch respectively through a third multi-way switch, and the fourth multi-way switch is connected with the Q end of the fifth trigger respectivelySide, sixth trigger +.>The end connection, the D end of fourth trigger is connected with one input of second exclusive-OR gate, another input of second exclusive-OR gate is connected with the Q end of fifth trigger, the Q end of sixth trigger is connected with the Q end of fifth trigger respectively through fifth multiway switch, the TAC circuit includes first TAC circuit, second TAC circuit, the output of first exclusive-OR gate is connected with the D end of first TAC circuit, seventh trigger respectively, the output of second exclusive-OR gate is connected with the D end of second TAC circuit, eighth trigger respectively, the Q end of seventh trigger is connected with the D end of ninth trigger, the Q end of seventh trigger is connected with two input of first or gate respectively, the Q end of eighth trigger is connected with the D end of tenth trigger, the Q end of eighth trigger is connected with two input of second TAC circuit respectively, the output of first, second exclusive-OR gate is connected with the D end of seventh trigger respectively, the Q end of seventh trigger constitutes the first TAC circuit, the second trigger is connected with the first exclusive-OR gate, the first comparator circuit, the second trigger is interpolated to the fifth trigger, the first trigger is compared to the first trigger, the second trigger is the first comparator, the second trigger is the comparator.
The R ends of the first trigger, the second trigger, the third trigger, the fourth trigger, the fifth trigger, the sixth trigger, the seventh trigger, the eighth trigger, the ninth trigger and the tenth trigger are all connected with a Reset signal Reset, and the CP ends of the second trigger, the third trigger, the fifth trigger, the sixth trigger, the seventh trigger, the eighth trigger, the ninth trigger and the tenth trigger are all connected with a clock signal CLK.
The first multi-way switch, the second multi-way switch, the fourth multi-way switch and the fifth multi-way switch are all connected with interpolation precision mode control bits, the third multi-way switch is connected with the output end of a third exclusive-OR gate, the Start voltage sends a Start signal, the Start signal is sent to the CP end of the first trigger through the first comparator, the end voltage sends a Stop signal, and the Stop signal is sent to the CP end of the fourth trigger through the second comparator.
The first TAC circuit and the second TAC circuit both comprise an integrating capacitor, an output current source driving end logic control circuit and a temperature drift suppression circuit, the input end of the integrating capacitor is provided with a first constant current source, a second constant current source and a third constant current source, the output end of the integrating capacitor is connected with an A/D converter, the first constant current source flows into the integrating capacitor, the second constant current source and the third constant current source flow out of the integrating capacitor, the input end of the first constant current source is connected with the temperature drift suppression circuit, the second constant current source and the third constant current source are both connected with the output current source driving end logic control circuit, the output current source driving end logic control circuit comprises a third comparator, a D trigger, a logic gate, a third OR gate, a first NOT gate and a second NOT gate, the output end of the integrating capacitor is connected with the positive end of the third comparator, the negative end of the third comparator is grounded, the output end of the third comparator is connected with the D end of the D trigger, the CP end of the D trigger is connected with a CLK signal, the Q end of the D trigger is connected with one end of an AND logic gate, the other end of the AND logic gate is connected with an integral pulse signal, the output end of the AND logic gate is connected with one input end of a third OR gate, the Q end of the D trigger is connected with the other input end of the third OR gate through a first NOT gate, the output end of the third OR gate is connected with a first BJT switch, the output end of the AND logic gate is connected with a second BJT switch through a second NOT gate, the first BJT switch and the second BJT switch respectively control the switches of a second constant current source and a third constant current source, the temperature drift suppression circuit comprises an ADC sampling part, a D/A converter and an analog PID control part, the output end of the integral capacitor is connected with the A/D converter, the analog-to-digital converter is connected with the analog-to-digital converter, the analog-to-digital converter is connected with the analog-to-digital converter through a sixth multiplexing switch, the analog-to-digital converter is connected with the analog PID control part, and the analog PID control part is connected with the positive end of the first constant current source.
The D trigger is a rising edge trigger.
A method of controlling a TDC-based high repetition rate time interval digitizer, comprising the steps of:
s1, selecting a working mode, wherein the TDC circuit has two working modes, the switching of the working modes is controlled by an interpolation precision mode control bit, when the interpolation precision mode control bit is output to be 0, the working mode is a dead zone-free mode, and when the interpolation precision mode control bit is output to be 1, the working mode is a high-linearity mode;
s2, generating an integral pulse signal;
s3, performing time-amplitude conversion to obtain a first integrated pulse signal T 1 Second integral pulse signal T 2 ；
S4, calculating a time interval T 12 ；
S5, calculating a total time interval T, and utilizing a formula T=T 12 +T 1 -T 2 And calculating T, and digitally outputting the size of the total time interval T.
The method for generating the integral pulse signal in the step S2 is as follows: connecting the D end and the Q end of the fourth trigger through a third multi-way switch, sending a Start signal, and enabling the upper interpolation branch to work, wherein the lower interpolation branch is not allowed to work before a Stop signal comes; after the Stop signal comes, the lower interpolation branch works; if the upper interpolation leg is not active, the lower interpolation leg is not active under any conditions, and the upper interpolation leg generates a first integrated pulse signal T 1 The lower interpolation branch generates a second integral pulse signal T 2 。
The S3 obtains a first integral pulse signal T 1 Second integral pulse signal T 2 The method of (1) is as follows: first integral pulse signal T 1 Second integral pulse signal T 2 Respectively viaThe first TAC circuit and the second TAC circuit are used for performing time-amplitude conversion, and the capacitor is charged and discharged through current to generate T 1 /T 2 The voltage with proportional length is subjected to analog-digital conversion by ADC sampling to obtain a first integral pulse signal T 1 Second integral pulse signal T 2 Is a value of (2).
Calculating the time interval T in the S4 12 The method of (1) is as follows: two output ends of the TAC circuit are connected to an FPGA module, and T is calculated by a 16-bit counter in the FPGA module 12 For each rising edge of the clock, the Q value of the counter is increased by 1 until the rising edge of the Stop signal comes, according to T 12 ＝Q*T CLK Measuring time interval T 12 The value of T CLK Is the period of the clock signal.
Compared with the prior art, the invention has the beneficial effects that:
the TDC circuit does not need to carry out special reset operation, and solves the problems that in the prior art, an analog interpolation method based on a time-amplitude conversion principle is adopted to measure time intervals, a measurement result is sensitive to temperature, and the measurement reaction speed of the circuit is slower during continuous measurement.
Drawings
FIG. 1 is a circuit diagram of the present invention;
FIG. 2 is a schematic diagram of the TAC circuit of the present invention;
FIG. 3 is a diagram showing the composition of a TDC circuit in a high-linearity mode of operation of the present invention;
FIG. 4 is a diagram showing the composition of a TDC circuit in a dead-zone-free operating mode according to the present invention;
FIG. 5 is a graph of integrated pulse signal generated in a high linearity mode of the present invention;
FIG. 6 is a signal waveform diagram of a TDC main circuit of the present invention operating in a high linearity mode;
FIG. 7 is a sampling process in a high linearity mode of the present invention;
FIG. 8 is a graph showing the generation of an integrated pulse signal in a dead zone free mode of the present invention;
FIG. 9 is a signal waveform diagram of a TDC main circuit of the present invention operating in a dead-band-free mode;
FIG. 10 is a sampling process in the dead zone-free mode of the present invention;
wherein: 1 is a TDC circuit, 2 is a first comparator, 3 is a second comparator, TDA1 is a first trigger, TDA2 is a second trigger, TDA3 is a third trigger, TDO1 is a fourth trigger, TDO2 is a fifth trigger, TDO3 is a sixth trigger, TDA4 is a seventh trigger, TDO4 is an eighth trigger, TDA5 is a ninth trigger, TDO5 is a tenth trigger, V START To start voltage, V TH Is a threshold voltage, V STOP To end the voltage, Q 1 For the first multi-way switch, Q 2 For the second multi-way switch, Q 3 For the third multi-way switch, Q 4 For the fourth multi-way switch, Q 5 For the fifth multi-way switch, Q 6 The digital signal processor comprises a sixth multiplexing switch, wherein the first multiplexing switch is composed of a first TAC circuit, a second TAC circuit, an FPGA module, an integrating capacitor, an output current source driving end logic control circuit, a temperature drift suppression circuit, a first constant current source, a second constant current source, a third comparator, a D trigger, a first OR gate, a second OR gate, a AND logic gate, a third OR gate, a first NOT gate, a second NOT gate, a first BJT switch, a second BJT switch, an ADC sampling, a D/A converter, an analog PID control part, an interpolation precision mode control bit, an A/D converter, an XOR1, a first XOR2, a second XOR gate and a third XOR 3.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
A TDC-based high repetition rate time interval digitizer, as shown in FIG. 1, includes a TDC circuit 1 and a TAC circuit, the TDC circuit 1 including a first comparator2. A second comparator 3, a first trigger TDA1, a second trigger TDA2, a third trigger TDA3, a fourth trigger TDO1, a fifth trigger TDO2, a sixth trigger TDO3, a seventh trigger TDA4, an eighth trigger TDO4, a ninth trigger TDA5 and a tenth trigger TDO5, wherein the positive end of the first comparator 2 is connected with a starting voltage V START The negative terminal of the first comparator 2 is connected with a threshold voltage V TH The output end of the first comparator 2 is connected with the CP control end of the first trigger TDA1, the Q end of the first trigger TDA1 is connected with the D end of the second trigger TDA2, and the Q end of the second trigger TDA2 is connected with the D end of the third trigger TDA 3; the positive end of the second comparator 3 is connected with an end voltage V STOP The negative terminal of the second comparator 3 is connected with a threshold voltage V TH The output end of the second comparator 3 is connected with the CP control end of a fourth trigger TDO1, the Q end of the fourth trigger TDO1 is connected with the D end of a fifth trigger TDO2, and the Q end of the fifth trigger TDO2 is connected with the D end of a sixth trigger TDO 3; the Q end of the first trigger TDA1 is connected with one input end of a first exclusive OR gate XOR1, and the other input end of the first exclusive OR gate XOR1 is connected with a first multi-way switch Q 1 The D end of the first trigger TDA1 is connected with the Q end of the second trigger TDA2 and the Q end of the third trigger TDA3 respectively, and the D end of the first trigger TDA1 is connected with the Q end of the second trigger TDA3 through a second multi-way switch 2 The D end of the fourth trigger TDO1 is connected with the Q end of the second trigger TDA2 and the Q end of the third trigger TDA3 respectively, and the D end of the fourth trigger TDO1 is connected with the Q end of the third multi-way switch 3 Respectively with the Q end of the fourth trigger TDO1 and the fourth multi-way switch Q 4 Connected with a fourth multi-way switch Q 4 Respectively with the fifth trigger TDO2End, sixth flip-flop TDO3 +.>The end connection, D end of the fourth trigger TDO1 is connected with one input end of the second exclusive OR gate XOR2, and the other input end of the second exclusive OR gate XOR2 is connected with the second input end of the second trigger TDO1 through a fifth multiplexing switch Q 5 Is respectively connected with the Q end of the fifth trigger TDO2 and the Q end of the sixth trigger TDO3, the TAC circuits comprise a first TAC circuit 4 and a second TAC circuit 5,the output end of the first exclusive or gate XOR1 is respectively connected with the D ends of the first TAC circuit 4 and the seventh trigger TDA4, the output end of the second exclusive or gate XOR2 is respectively connected with the D ends of the second TAC circuit 5 and the eighth trigger TDO4, the Q end of the seventh trigger TDA4 is connected with the D end of the ninth trigger TDA5, the Q end of the seventh trigger TDA4 and the Q end of the ninth trigger TDA5 are respectively connected with the two input ends of the first or gate 16, the Q end of the eighth trigger TDO4 is connected with the D end of the tenth trigger TDO5, the Q end of the eighth trigger TDO4 and the Q end of the tenth trigger TDO5 are respectively connected with the two input ends of the second or gate 17, the output ends of the first TAC circuit 4 and the second TAC circuit 5 are respectively connected with the input ends of the FPGA module 6, the first comparator 2, the first trigger TDA1, the second trigger TDA2, the third trigger TDA3, the first trigger TDO1 and the second trigger TDO3 are respectively connected with the two input ends of the first exclusive or gate TDO4, the second trigger TDO3 and the second exclusive or gate XOR2 are interpolated by the fifth trigger TDO 3.
Further, R ends of the first, second, third, fourth, fifth, sixth, seventh, eighth, and tenth flip-flops TDA1, TDA2, TDA3, TDO1, TDO2, TDO3, TDA4, TDO4, TDA5, TDO5 are all connected to a Reset signal Reset, and CP ends of the second, third, fifth, sixth, seventh, eighth, ninth, and tenth flip-flops TDA2, TDA3, TDO2, TDO3, TDO4, TDA5, TDO5 are all connected to a clock signal CLK.
Further, a first multi-way switch Q 1 Second multi-way switch Q 2 Fourth multiway switch Q 4 Fifth multi-way switch Q 5 Are all connected with interpolation precision mode control bits 27, a third multi-way switch Q 3 A third exclusive or gate XOR3 is connected to start voltage V START A Start signal is sent to the CP end of the first trigger TDA1 through the first comparator 2, and the voltage V is ended STOP A Stop signal is sent out and sent to the CP end of the fourth flip-flop TDO1 through the second comparator 3.
Further, as shown in fig. 2, the first TAC circuit 4 and the second TAC circuit 5 each includeThe integrating capacitor 8, the output current source driving end logic control circuit 9 and the temperature drift suppression circuit 10, the input end of the integrating capacitor 8 is provided with a first constant current source 11, a second constant current source 12 and a third constant current source 13, the first constant current source 11 flows into the integrating capacitor 8, the second constant current source 12 and the third constant current source 13 flow out of the integrating capacitor 8, the input end of the first constant current source 11 is connected with the temperature drift suppression circuit 10, the second constant current source 12 and the third constant current source 13 are both connected with the output current source driving end logic control circuit 9, the output current source driving end logic control circuit 9 comprises a third comparator 14, a D trigger 15, a logic gate 18, a third OR gate 19, a first NOT gate 20 and a second NOT gate 21, the output end of the integrating capacitor 8 is connected with the positive end of the third comparator 14, the negative end of the third comparator 14 is grounded, the output end of the third comparator 14 is connected with the D end of the D trigger 15, the CP end of the D trigger 15 is connected with a CLK signal, the Q end of the D trigger 15 is connected with one end of an AND logic gate 18, the other end of the AND logic gate 18 is connected with an integral pulse signal, the output end of the AND logic gate 18 is connected with one input end of a third OR gate 19, the Q end of the D trigger 15 is connected with the other input end of the third OR gate 19 through a first NOT gate 20, the output end of the third OR gate 19 is connected with a first BJT switch 22, the output end of the AND logic gate 18 is connected with a second BJT switch 23 through a second NOT gate 21, the first BJT switch 22 and the second BJT switch 23 respectively control the switches of a second constant current source 12 and a third constant current source 13, the temperature drift suppression circuit 10 comprises an ADC sampling 24, a D/A converter 25 and an analog PID control part 26, the output end of the integral capacitor 8 is connected with an A/D converter, the A/D converter is connected with the ADC sampling 24, ADC sampling 24 is through a sixth multiplexing switch Q 6 The D/a converter 25 is connected to the analog PID control section 26, and the analog PID control section 26 is connected to the positive terminal of the first constant current source 11.
Further, preferably, the D flip-flop 15 is a rising edge trigger.
A method of controlling a TDC-based high repetition rate time interval digitizer, comprising the steps of:
s1, selecting a working mode, wherein the TDC circuit has two working modes, the switching of the working modes is controlled by an interpolation precision mode control bit, when the interpolation precision mode control bit is output to be 0, the working mode is a dead zone-free mode, and when the interpolation precision mode control bit is output to be 1, the working mode is a high-linearity mode;
the high linearity mode is shown in FIG. 3, and generates an integral pulse signal
The interpolation branch generates an integral pulse signal T 1 For example, as shown in fig. 5.
In the high linearity mode, at initial time, the Reset signal Reset sets the Q-terminal of the first, second and third flip-flops TDA1, TDA2 and TDA3 to zero, and the first, second and third flip-flops TDA1, TDA2 and TDA3End 1; at this time, the output T of the first exclusive OR gate XOR1 1 Is 0. Third flip-flop TDA3 +.>The terminal passes through a second multi-way switch Q 2 Is connected to the D terminal of the first flip-flop TDA1, so that the D terminal of the first flip-flop TDA1 is 1 at the reset time.
Clock signal t 1 When the event signal Start/Stop arrives at a certain time of the period, the Start/Stop signal is sent to the CP terminal of the first trigger TDA1 through the comparator, and the Q terminal of the first trigger TDA1 is 1. One path of the Q end of the first trigger TDA1 is directly sent to the first exclusive OR gate XOR1, and at the moment, the Q ends of the two paths of input first trigger TDA1 and third trigger TDA3 of the first exclusive OR gate XOR1 are respectively 1 and 0. Therefore, the output terminal T of the first exclusive OR gate XOR1 1 Becomes 1. To clock signal t 2 At the time of the falling edge of the period, the Q end of the third trigger TDA3 is arranged at 1 and passes through the first multi-way switch Q 1 Is fed into the first exclusive or gate XOR1, and the Q ends of the two paths of the first exclusive or gate XOR1 input the first trigger TDA1 and the third trigger TDA3 are respectively 1 and 1, and output T 1 Becomes 0. The Q-terminal of the third flip-flop TDA3 and the D-terminal of the first flip-flop TDA1 are set to zero.
Over several clock cycles, clock signal t n At a certain moment in the period, the next event signal Start/Stop arrives, at this time, the D end of the first trigger TDA1 is 0, the firstThe Q end of one trigger TDA1 is 0, one path of the Q end of the first trigger TDA1 is directly sent to the first exclusive OR gate XOR1, and at the moment, the Q ends of the two paths of input first trigger TDA1 and third trigger TDA3 of the first exclusive OR gate XOR1 are respectively 0 and 1. Therefore, the output terminal T of the first exclusive OR gate XOR1 1 Becomes 1. The other path of the first trigger TDA1 is fed to the next second trigger TDA2 and via the second trigger TDA2 to the third trigger TDA3. To the next clock cycle (t n+1 Period), the Q end of the third trigger TDA3 is set to 0 and passes through the first multiplexing switch Q 1 Is fed into the first exclusive or gate XOR1, and the Q end of the first trigger TDA1 and the Q end of the third trigger TDA3 are respectively 0 and 0 at the moment, and output T 1 Becomes 0. The Q-terminal of the third flip-flop TDA3 and the D-terminal 1 of the first flip-flop TDA 1. The signal states in the circuit are restored to Reset time as shown in fig. 6.
Generating an integral pulse signal T in a high linearity mode of the TDC circuit by the above process 1 . Similarly, T can be obtained 2 。
In order to obtain the output voltage values of the integrating capacitors before and after pulse integration, the following sampling process is adopted in the high linearity mode:
taking 6 clock cycles as an example, the sampling instant is the rising edge of the clock cycle.
The first sample is an effective sample of the output voltage in the hold state. Integration starts when the event signal Start/Stop arrives, and the second period (t 3 Period) the integration ends at the time the clock falling edge arrives.
The second sampling occurs after the integration begins, but at this point the capacitor charging has not yet been completed (i.e., the integration has not yet ended), so the second sampling is an invalid sampling, and the data from the invalid sampling is discarded.
The third sampling occurs after the capacitor discharge is completed, and is effective sampling, and the collected data is effective data.
The fourth sampling is the effective sampling as the third sampling, and the collected data is effective data.
The fifth sample, similar to the second sample, occurs during capacitor charging, as an invalid sample, and the data of the invalid sample is discarded.
The sixth sampling is similar to the third sampling, and takes place after the integration is finished, and is effective sampling, and the output voltage of the integration capacitor is stable at this time, and the data acquired at this time is effective data.
As shown in fig. 7, the sampling mode in the high linearity mode is to sample at the moment when the output voltage of the integrating capacitor stabilizes. This mode has the advantage of high integration process linearity, and the disadvantage that the event signal Start/Stop can only be triggered at intervals.
No dead zone mode as shown in FIG. 4, an integral pulse signal is generated
The interpolation branch generates an integral pulse signal T 1 For example, no dead zone mode generates an integrated pulse signal T 1 /T 2 The working process of (2) is as follows:
in the dead zone-free mode, at initial time, the Reset signal Reset sets the Q-terminal of the first and second flip-flops TDA1 and TDA2 to zero, while the first and second flip-flops TDA1 and TDA2End 1; at this time, the Q ends of the two input first flip-flop TDA1 and the second flip-flop TDA2 of the first exclusive OR gate XOR1 are respectively 0 and 0, and the output T of the first exclusive OR gate XOR1 1 Is 0. Second flip-flop TDA2 +.>The terminal passes through a second multi-way switch Q 2 Is connected to the D terminal of the first flip-flop TDA1, so that the D terminal of the first flip-flop TDA1 is 1 at the reset time.
Clock signal t 1 When the event signal Start/Stop arrives at a certain time of the period, the Start/Stop signal is sent to the CP terminal of the first trigger TDA1 through the comparator, and the Q terminal of the first trigger TDA1 is 1. One path of the Q end of the first trigger TDA1 is directly sent to the first exclusive OR gate XOR1, at this time, the Q ends of the two paths of the first trigger TDA1 and the second trigger TDA2 input into the first exclusive OR gate XOR1 are respectively 1 and 0, and the output end T of the first exclusive OR gate XOR1 1 1 is shown in the specification; the other path of the Q terminal of the first flip-flop TDA1 is sent to the next second flip-flop TDA2. To clock signal t 2 At the rising edge of the period, the Q end 1 of the second trigger TDA2 passes through the first multiplexing switch Q 1 Into the first exclusive or gate XOR1, the Q ends of the two input first and second flip-flops TDA1 and TDA2 of the first exclusive or gate XOR1 are respectively 1 and 1, so that the output T 1 Becomes 0. Second trigger TDA2The D-end of the end and first flip-flop TDA1 is set to zero.
Over several clock cycles, clock signal t n At a certain moment in the period, the next event signal Start/Stop arrives, at this time, the D end of the first trigger TDA1 is 0, the Q end of the first trigger TDA1 is 0, one path of the Q end of the first trigger TDA1 is directly sent to the first exclusive or gate XOR1, at this time, two paths of input of the first exclusive or gate XOR1 are respectively 0 and 1, and the Q ends of the first trigger TDA1 and the second trigger TDA2 are respectively 0 and 1, so the output end T of the first exclusive or gate XOR1 1 1. The other path of the Q terminal of the first flip-flop TDA1 feeds into the next second flip-flop TDA2. To the next clock cycle (t n+1 Period), the Q end of the second trigger TDA2 is set to 0 and passes through the first multiplexing switch Q 1 Is fed into the first exclusive or gate XOR1, and the Q ends of the two paths of the first exclusive or gate XOR1 input the first trigger TDA1 and the second trigger TDA2 are respectively 0 and 0, and output T 1 Becomes 0. The third trigger TDA3Terminal and D-terminal 1 of the first flip-flop TDA 1. The state of each signal in the circuit is restored to Reset timing as shown in fig. 9.
Generating an integral pulse signal T of the TDC circuit in the dead zone-free mode by the above process 1 . Similarly, T can be obtained 2 。
In order to obtain the output voltage values of the integrating capacitors before and after the pulse integration, the sampling process shown in fig. 10 is adopted in the no dead zone mode.
Taking 5 clock cycles as an example, 5 samples are all valid samples.
Sampling at a time deltat from the rising clock edge is employed in the dead-zone-free mode. When the sampling occurs at the time when the integration capacitor is not integrated, the sampling value is equal to the value before the integration time; when sampling occurs at the integration time of the integrating capacitor, the sampling value is added with DeltaU C Is the value of the integration end time. Because the capacitor charge rate is constant DeltaU C Is a fixed value.
Therefore, the dead zone-free mode well solves the problem that sampling cannot be performed at the moment that the output of the integration capacitor is unstable in the high-linearity mode.
S2, generating an integral pulse signal;
s3, performing time-amplitude conversion to obtain a first integrated pulse signal T 1 Second integral pulse signal T 2 ；
S4, calculating a time interval T 12 ；
S5, calculating a total time interval T, and utilizing a formula T=T 12 +T 1 -T 2 And calculating T, and digitally outputting the size of the total time interval T.
Further, the method for generating the integrated pulse signal in S2 is as follows: connecting the D end and the Q end of the fourth trigger through a third multi-way switch, sending a Start signal, and enabling the upper interpolation branch to work, wherein the lower interpolation branch is not allowed to work before a Stop signal comes; after the Stop signal comes, the lower interpolation leg operates. If the upper interpolation leg is not active, the lower interpolation leg is inactive under any conditions. The upper interpolation branch generates a first integral pulse signal T 1 The lower interpolation branch generates a second integral pulse signal T 2 . S3, obtaining a first integral pulse signal T 1 Second integral pulse signal T 2 The method of (1) is as follows: first integral pulse signal T 1 Second integral pulse signal T 2 The time-amplitude conversion is carried out by the first TAC circuit and the second TAC circuit respectively, and the capacitor is charged and discharged through current to generate T 1 /T 2 The voltage with proportional length is subjected to analog-digital conversion by ADC sampling to obtain a first integral pulse signal T 1 Second integral pulse signal T 2 Is a value of (2).
Further, the time interval T is calculated in S4 12 The method of (1) is as follows: two output ends of the TAC circuit are connected to an FPGA module, and T is calculated by a 16-bit counter in the FPGA module 12 For each rising edge of the clock, the Q value of the counter is increased by 1 until the rising edge of the Stop signal comes, according to T 12 ＝Q*T CLK Measuring time interval T 12 Is a value of (2).
The preferred embodiments of the present invention have been described in detail, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the spirit of the present invention, and the various changes are included in the scope of the present invention.

Claims (9)

1. A TDC-based high repetition rate time interval digitizer, characterized by: the TDC circuit (1) comprises a first comparator (2), a second comparator (3), a first trigger (TDA 1), a second trigger (TDA 2), a third trigger (TDA 3), a fourth trigger (TDO 1), a fifth trigger (TDO 2), a sixth trigger (TDO 3), a seventh trigger (TDA 4), an eighth trigger (TDO 4), a ninth trigger (TDA 5) and a tenth trigger (TDO 5), wherein the positive end of the first comparator (2) is connected with a starting voltage (V START ) The negative terminal of the first comparator (2) is connected with a threshold voltage (V TH ) The output end of the first comparator (2) is connected with the CP control end of the first trigger (TDA 1), the Q end of the first trigger (TDA 1) is connected with the D end of the second trigger (TDA 2), and the Q end of the second trigger (TDA 2) is connected with the D end of the third trigger (TDA 3); the positive end of the second comparator (3) is connected with an end voltage (V) STOP ) The negative end of the second comparator (3) is connected with a threshold voltage (V TH ) The output end of the second comparator (3) is connected with the CP control end of a fourth trigger (TDO 1), the Q end of the fourth trigger (TDO 1) is connected with the D end of a fifth trigger (TDO 2), and the Q end of the fifth trigger (TDO 2) is connected with the D end of a sixth trigger (TDO 3); the first touchThe Q terminal of the generator (TDA 1) is connected to one input terminal of a first exclusive OR gate (XOR 1), the other input terminal of the first exclusive OR gate (XOR 1) is connected to the output terminal of the first multiplexer (Q) 1 ) Is respectively connected with the Q end of the second trigger (TDA 2) and the Q end of the third trigger (TDA 3), the D end of the first trigger (TDA 1) is connected with the Q end of the second trigger (TDA 2) through a second multiplexing switch (Q) 2 ) Is respectively connected with the Q end of the second trigger (TDA 2) and the Q end of the third trigger (TDA 3), and the D end of the fourth trigger (TDO 1) is connected with the Q end of the third multi-way switch (Q) 3 ) Respectively with the Q end of the fourth trigger (TDO 1) and a fourth multiplexing switch (Q 4 ) Is connected to the fourth multi-way switch (Q 4 ) Respectively with a fifth trigger (TDO 2)End, sixth flip-flop (TDO 3)>A terminal connection, the D terminal of the fourth flip-flop (TDO 1) being connected to one input terminal of a second exclusive-OR gate (XOR 2), the other input terminal of the second exclusive-OR gate (XOR 2) being connected to the input terminal of the second exclusive-OR gate (TDO 1) via a fifth multiplexing switch (Q) 5 ) The output end of the first exclusive-OR gate (XOR 1) is respectively connected with the D end of the first TAC circuit (4) and the D end of the seventh trigger (TDA 4), the output end of the second exclusive-OR gate (XOR 2) is respectively connected with the D end of the second TAC circuit (5) and the D end of the eighth trigger (TDO 4), the Q end of the seventh trigger (TDA 4) is connected with the D end of the ninth trigger (TDA 5), the Q end of the seventh trigger (TDA 4) is respectively connected with the two input ends of the first OR gate (16), the Q end of the eighth trigger (TDO 4) is connected with the D end of the tenth trigger (TDO 5), and the Q end of the eighth trigger (TDO 4) is respectively connected with the Q end of the ninth trigger (TDA 5), the Q end of the seventh trigger (TDA 4), the Q end of the ninth trigger (TDA 5) is respectively connected with the two input ends of the first OR gate (16), the Q end of the eighth trigger (TDO 4) is respectively connected with the Q end of the first or the second trigger (TDA 4), the Q end of the eighth trigger (TDA 4) is respectively connected with the Q end of the first or the third trigger (TDA 5), the Q end of the eighth trigger (TDA 4) is connected with the Q end of the first trigger (TDA 2, the second trigger (TDA 2), the output end of the eighth trigger (TDO 2, the output end of the eighth trigger (TDO 2) is respectively, the output end is connected with the output end of the output and the output signal is respectively, and the output signal is output, and the output signal is output and is outputAn exclusive-OR gate (XOR 1) and the first TAC circuit (4) form an upper interpolation branch, and the second comparator (3), the fourth flip-flop (TDO 1), the fifth flip-flop (TDO 2), the sixth flip-flop (TDO 3), the second exclusive-OR gate (XOR 2) and the second TAC circuit (5) form a lower interpolation branch.
2. A TDC-based high repetition rate time interval digitizer according to claim 1, characterized in that: the first flip-flop (TDA 1), the second flip-flop (TDA 2), the third flip-flop (TDA 3), the fourth flip-flop (TDO 1), the fifth flip-flop (TDO 2), the sixth flip-flop (TDO 3), the seventh flip-flop (TDA 4), the eighth flip-flop (TDO 4), the ninth flip-flop (TDA 5), and the tenth flip-flop (TDO 5) are each connected with a Reset signal Reset, and the CP ends of the second flip-flop (TDA 2), the third flip-flop (TDA 3), the fifth flip-flop (TDO 2), the sixth flip-flop (TDO 3), the seventh flip-flop (TDA 4), the eighth flip-flop (TDO 4), the ninth flip-flop (TDA 5), and the tenth flip-flop (TDO 5) are each connected with a clock signal CLK.
3. A TDC-based high repetition rate time interval digitizer according to claim 1, characterized in that: the first multi-way switch (Q 1 ) Second multiway switch (Q) 2 ) Fourth multiway switch (Q) 4 ) Fifth multi-way switch (Q) 5 ) Are all connected with interpolation precision mode control bits (27), the third multiplexing switch (Q 3 ) The output of the third exclusive or gate (XOR 3) is connected, the start voltage (V START ) A Start signal is sent to the CP end of the first trigger (TDA 1) through a first comparator (2), and the end voltage (V STOP ) And a Stop signal is sent out and is sent to the CP end of the fourth trigger (TDO 1) through the second comparator (3).
4. A TDC-based high repetition rate time interval digitizer according to claim 1, characterized in that: the first TAC circuit (4) and the second TAC circuit (5) comprise an integrating capacitor (8), an output current source driving end logic control circuit (9) and a temperature drift suppression circuit (10), and the integrating capacitor is connected with the output current source driving end logic control circuitThe output end of the capacitor (8) is connected with an A/D converter (28), the input end of the integrating capacitor (8) is provided with a first constant current source (11), a second constant current source (12) and a third constant current source (13), the first constant current source (11) flows into the integrating capacitor (8), the second constant current source (12) and the third constant current source (13) flow out of the integrating capacitor (8), the input end of the first constant current source (11) is connected with a temperature drift suppressing circuit (10), the second constant current source (12) and the third constant current source (13) are connected with an output current source driving end logic control circuit (9), the output current source driving end logic control circuit (9) comprises a third comparator (14), a D trigger (15), an AND logic gate (18), a third OR gate (19), a first NOT gate (20) and a second NOT gate (21), the output end of the integrating capacitor (8) is connected with the positive end of the third comparator (14), the negative end of the third comparator (14) is grounded, the output end of the third comparator (14) is connected with the D trigger end of the D trigger (15), the other end of the D trigger (15) is connected with the output end of the D trigger logic gate (18) and the other end of the output logic gate (18), the output end of the AND logic gate (18) is connected with one input end of a third OR gate (19), the Q end of the D trigger (15) is connected with the other input end of the third OR gate (19) through a first NOT gate (20), the output end of the third OR gate (19) is connected with a first BJT switch (22), the output end of the AND logic gate (18) is connected with a second BJT switch (23) through a second NOT gate (21), the first BJT switch (22) and the second BJT switch (23) respectively control the switches of a second constant current source (12) and a third constant current source (13), the temperature drift suppression circuit (10) comprises an ADC sample (24), a D/A converter (25) and an analog PID control part (26), the output end of the integrating capacitor (8) is connected with an A/D converter, the A/D converter is connected with the ADC sample (24), and the ADC sample (24) is respectively controlled by a sixth multiplexing switch (Q) 6 ) The D/A converter (25) is connected with an analog PID control part (26), and the analog PID control part (26) is connected with the positive end of the first constant current source (11).
5. A TDC-based high repetition rate time interval digitizer according to claim 1, characterized in that: the D trigger (15) is triggered by a rising edge.
6. A method of controlling a TDC-based high repetition rate time interval digitizer according to any one of claims 1-5, characterized by: comprises the following steps:
s1, selecting a working mode, wherein the TDC circuit has two working modes, the switching of the working modes is controlled by an interpolation precision mode control bit, when the interpolation precision mode control bit is output to be 0, the working mode is a dead zone-free mode, and when the interpolation precision mode control bit is output to be 1, the working mode is a high-linearity mode;
s2, generating an integral pulse signal;
s3, performing time-amplitude conversion to obtain a first integrated pulse signal T 1 Second integral pulse signal T 2 ；
S4, calculating a time interval T 12 ；
S5, calculating a total time interval T, and utilizing a formula T=T 12 +T 1 -T 2 And calculating T, and digitally outputting the size of the total time interval T.
7. The method for controlling a TDC-based high repetition rate time interval digitizer according to claim 6, wherein: the method for generating the integral pulse signal in the step S2 is as follows: connecting the D end and the Q end of the fourth trigger through a third multi-way switch, sending a Start signal, and enabling the upper interpolation branch to work, wherein the lower interpolation branch is not allowed to work before a Stop signal comes; after the Stop signal comes, the lower interpolation branch works; if the upper interpolation leg is not active, the lower interpolation leg is not active under any conditions, and the upper interpolation leg generates a first integrated pulse signal T 1 The lower interpolation branch generates a second integral pulse signal T 2 。
8. The method for controlling a TDC-based high repetition rate time interval digitizer according to claim 6, wherein: the S3 obtains a first integral pulse signal T 1 Second oneIntegral pulse signal T 2 The method of (1) is as follows: first integral pulse signal T 1 Second integral pulse signal T 2 The time-amplitude conversion is carried out by the first TAC circuit and the second TAC circuit respectively, and the capacitor is charged and discharged through current to generate T 1 /T 2 The voltage with proportional length is subjected to analog-digital conversion by ADC sampling to obtain a first integral pulse signal T 1 Second integral pulse signal T 2 Is a value of (2).
9. The method for controlling a TDC-based high repetition rate time interval digitizer according to claim 6, wherein: calculating the time interval T in the S4 12 The method of (1) is as follows: two output ends of the TAC circuit are connected to an FPGA module, and T is calculated by a 16-bit counter in the FPGA module 12 For each rising edge of the clock, the Q value of the counter is increased by 1 until the rising edge of the Stop signal comes, according to T 12 ＝Q*T CLK Measuring time interval T 12 The value of T CLK Is the period of the clock signal.
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