CN205453666U - High performance -price ratio simple integral type adc - Google Patents
High performance -price ratio simple integral type adc Download PDFInfo
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- CN205453666U CN205453666U CN201620181698.6U CN201620181698U CN205453666U CN 205453666 U CN205453666 U CN 205453666U CN 201620181698 U CN201620181698 U CN 201620181698U CN 205453666 U CN205453666 U CN 205453666U
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Abstract
The utility model discloses a high performance -price ratio simple integral type adc, adc includes sawtooth wave generator, negative feedback circuit and analog to digital conversion circuit, analog to digital conversion circuit comprises first multiple selector, first comparator, a digital logic control circuit and first counter, to the await measuring size of voltage of this adc converts the sawtooth wave into and drops to the time length of the voltage that awaits measuring by reference voltage, and then converts corresponding counting value to, the await measuring magnitude of voltage of voltage of final computation play. The utility model discloses a control of digital logic circuit makes the conversion process, and the error that the time delay of centre devices such as comparator caused is offset, and then reaches the improvement performance, and reduce cost's purpose simultaneously through digital circuit's design, makes analog circuit's components and parts parameter to system performance's influence reduction, compares with traditional total mark type adc, changes the debugging, has saved development cost, has shortened development period.
Description
Technical field
This utility model relates to a kind of analog-digital converter, especially a kind of high performance-price ratio simple integral pattern number converter, belongs to modulus conversion technique field.
Background technology
Along with digital integrated electronic circuit and the development of embedded system, use the product design scheme with digital circuit as core such as embedded system, SOC(system on a chip), PLD, have become as electronic product and manufacture and design first-selection and the main flow of industry.Many products inevitably need to apply modulus conversion technique among these.And due to digital circuit capacity of resisting disturbance, the able to programme and outstanding advantage of low-power consumption, increasing analog systems uses digital circuit to be controlled, wherein it is also required to apply modulus conversion technique.
At present the Design of A/D Converter scheme in electron trade mainly has: successive approximation, ∑-Δ modulation type, compare type, integral form, voltage to frequency conversion type etc. parallel.And for quick consumer electronics and the low cost of portable type electronic product, the demand that the smallest and the most exquisite and the construction cycle is short, double integrator pattern number converter more conforms to the market demand.
But the shortcoming of double integrator pattern number converter is that conversion speed is slow.If using the simple integral pattern number converter of equal clock speed, conversion rate can promote one times, but performance is easily subject to the impact of electronic component parameter in integrating circuit, comparator is also required to the employing high-speed comparator time delay with the reduction comparator output level reversion impact on performance.
" a kind of improved single-slope serial analog-digital converter " shown in CN101964662B improves performance and is easily subject to the shortcoming of the impact of electronic component parameter in integrating circuit, but still can be affected performance by the reversion time delay of comparator output level.
Utility model content
The purpose of this utility model is the defect in order to solve above-mentioned prior art, provide a kind of high performance-price ratio simple integral pattern number converter, the feature that this analog-digital converter has low cost, the smallest and the most exquisite, the construction cycle is short, solves comparator speed and the restriction to performance of the integrating circuit parameter simultaneously.
The purpose of this utility model can reach by adopting the following technical scheme that:
High performance-price ratio simple integral pattern number converter, including sawtooth generator, negative-feedback circuit and analog to digital conversion circuit, analog-digital conversion circuit as described is made up of the first MUX, the first comparator, the first Digital Logic control circuit and the first enumerator；
The sawtooth waveforms outfan of described sawtooth generator connects an input and an input of the first comparator of negative-feedback circuit；The outfan of described negative-feedback circuit connects the slope adjustment input of sawtooth generator；The reference voltage of outside input connects another input of negative-feedback circuit and an input of the first MUX respectively；The voltage to be measured of outside input connects another input of the first MUX；The outfan of described first MUX connects another input of the first comparator；The outfan of described first comparator connects the input of the first Digital Logic control circuit；The sawtooth period pulse digital signal of outside input connects sawtooth generator, negative-feedback circuit, the first Digital Logic control circuit and the clear terminal of the first enumerator；Two outfans of described first Digital Logic control circuit connect selection signal input part and the enable signal input part of the first enumerator of the first MUX respectively；The outfan of described first enumerator is connected to system output.
Further, the sawtooth waveforms outfan of described sawtooth generator connects the inverting input of the first comparator, and the outfan of described first MUX connects the normal phase input end of the first comparator.
Further, the negative feedback control mode of described negative-feedback circuit is pwm pulse width modulated.
nullFurther，Described negative-feedback circuit is by the second MUX、Second comparator、Second Digital Logic control circuit、Second enumerator and PWM module composition，Two inputs of described second MUX connect reference voltage and the 0V of outside input respectively，The outfan of described second MUX connects the normal phase input end of the second comparator，The outfan of described sawtooth generator connects the inverting input of the second comparator，The outfan of described second comparator connects the input of the second Digital Logic control circuit，Two outfans of described second Digital Logic control circuit connect selection input and the enable input of the second enumerator of the second MUX respectively，The outfan of described second enumerator connects the input of PWM module，The outfan of described PWM module connects the slope adjustment input of sawtooth generator，The sawtooth period pulse digital signal of outside input connects the second Digital Logic control circuit and the clear terminal of the second enumerator.
Further, the slope adjustment of described sawtooth generator, realize by the way of constant-current source controls charge storage module electric discharge.
Further, described sawtooth generator is made up of constant-current source, charge storage module and the 3rd comparator, and the constant current output end of described constant-current source connects the discharge and recharge input of charge storage module；The level output end of described charge storage module connects an input of negative-feedback circuit, and the first comparator and the inverting input of the 3rd comparator；The normal phase input end of described 3rd comparator connects fixed level；The outfan of described 3rd comparator connects an input of constant-current source；The outfan of described negative-feedback circuit connects another input of constant-current source；The sawtooth period pulse digital signal of outside input connects the clear terminal of constant-current source.
This utility model has a following beneficial effect relative to prior art:
1, the integrating circuit in analog-digital converter of the present utility model is carried out negative-feedback circuit control by digital circuit output PWM, solve the shortcoming that integrating circuit parameter affects conversion performance, reduce the cost of integrating circuit, reduce the design difficulty of integrating circuit, shorten the debugging cycle of integrating circuit.
2, the analog-digital converter of the present utility model control by Digital Logical Circuits, make in transformation process, the error that the time delay of the intermediary device such as comparator causes is cancelled, solve the restriction to conversion performance of the comparator speed, reduce the cost of comparator simultaneously, reduce global design difficulty, shorten overall debugging cycle.
3, the analog-digital converter of the present utility model design by digital circuit, makes the component parameter of analog circuit reduce the impact of systematic function, compared with traditional integral analogue-to-digital converter, is more easy to debugging, saves development cost, shorten the construction cycle.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of the high performance-price ratio simple integral pattern number converter of this utility model embodiment.
Fig. 2 is the design principle figure of the high performance-price ratio simple integral pattern number converter of this utility model embodiment.
Fig. 3 is the waveform diagram of the high performance-price ratio simple integral pattern number converter of this utility model embodiment.
Fig. 4 be this utility model embodiment high performance-price ratio simple integral pattern number converter in the design principle figure of Digital Logic control circuit.
Detailed description of the invention
Embodiment:
Below in conjunction with embodiment and accompanying drawing, this utility model is described in further detail, but embodiment of the present utility model is not limited to this.
As shown in Figure 1, the high performance-price ratio simple integral pattern number converter of the present embodiment includes sawtooth generator, negative-feedback circuit and analog to digital conversion circuit, and analog-digital conversion circuit as described is made up of the first MUX, the first comparator, the first Digital Logic control circuit and the first enumerator；
The sawtooth waveforms outfan of described sawtooth generator connects input and an input of the first comparator of negative-feedback circuit；The outfan of described negative-feedback circuit connects the slope adjustment input of sawtooth generator；Reference voltage Vref=the 2.5V of outside input connects another input of negative-feedback circuit and an input of the first MUX respectively；The voltage Vin to be measured of outside input connects another input of the first MUX；The outfan of described first MUX connects another input of the first comparator；The outfan of described first comparator connects the input of the first Digital Logic control circuit；The sawtooth period pulse digital signal of outside input connects sawtooth generator, negative-feedback circuit, the first Digital Logic control circuit and the clear terminal of the first enumerator；Two outfans of described first Digital Logic control circuit connect selection signal input part and the enable signal input part of the first enumerator of the first MUX respectively；The outfan of described first enumerator is connected to system output, and the outfan of the i.e. first enumerator enters the circuit of rear end as the digital quantity converted；
The sawtooth waveforms outfan of described sawtooth generator connects the inverting input of the first comparator, and the outfan of described first MUX connects the normal phase input end of the first comparator.
The design principle of the high performance-price ratio simple integral pattern number converter of the present embodiment is as shown in Figure 2, in fig. 2 it can be seen that, constant-current source, charge storage module and the 3rd comparator constitute the sawtooth generator in Fig. 1, the slope adjustment of sawtooth generator, realizes by the way of constant-current source controls charge storage module electric discharge；Second MUX, the second comparator, the second Digital Logic control circuit, the second enumerator and PWM module constitute the negative-feedback circuit in Fig. 1, and the negative feedback control mode of negative-feedback circuit is pwm pulse width modulated；The sawtooth waveforms that described sawtooth generator produces rises slope precipitous, that decline by negative-feedback circuit control.
The constant current output end of described constant-current source connects the discharge and recharge input of charge storage module；The level output end of described charge storage module connects the first comparator, the second comparator, the inverting input of the 3rd comparator；The normal phase input end of described 3rd comparator connects fixed level Vmax=3.3V；The outfan of described 3rd comparator connects an input of constant-current source；The outfan of described second enumerator connects the input of PWM module；The outfan of described PWM module connects another input of constant-current source；The sawtooth period pulse digital signal of outside input connects constant-current source, the first Digital Logic control circuit, the second Digital Logic control circuit, the first enumerator, the clear terminal of the second enumerator；
Two inputs of described second MUX connect reference voltage Vref=2.5V and 0V of outside input respectively, the outfan of described second MUX connects the normal phase input end of the second comparator, the outfan of described second comparator connects the input of the second Digital Logic control circuit, and two outfans of described second Digital Logic control circuit connect selection input and the enable input of the second enumerator of the second MUX respectively.
In conjunction with Fig. 2 and Fig. 3, described sawtooth period pulse digital signal is one and is divided the cyclic pulse signal obtained by crystal oscillation signal, and its cycle determines the cycle of sawtooth waveforms；
Described constant-current source starts when sawtooth period pulse digital signal arrives to charge charge storage module, charging process is not by PWM control, charging current is the maximum current that constant-current source can be provided by, charge storage module output end voltage Vramp quickly raises, 3rd comparator compares the size of Vmax Yu Vramp in real time, when Vramp is more than or equal to Vmax, make the Comp3v3 step-down of the 3rd comparator output, during the Comp3v3 signal step-down that constant-current source receives, stop charge storage module being charged, and proceed by constant-current discharge；After input value and ideal value are compared by PWM module, output pwm signal controls the size of current of constant-current source output, and Vramp slowly reduces with fixed slope；Enter next cycle when arriving to next sawtooth period pulse, repeat aforesaid operations.
As it is shown on figure 3, CapCharge is charging and discharging state signal, described charge storage module electric discharge when CapCharge is high, CapCharge charges for described charge storage module time low.
In conjunction with Fig. 2 and Fig. 3, described second Digital Logic control circuit and the second enumerator reset when sawtooth period pulse digital signal arrives, the selection signal Mux2 of the second MUX of the second Digital Logic control circuit output becomes low level, second MUX gating reference voltage Vref, now Vref is more than Vramp, output signal Comp2 of the second comparator is high level, the enable signal CountEn2 of the second enumerator of the second Digital Logic control circuit output is low level, and the second enumerator does not counts.
Vramp quickly raises subsequently；When Vramp is increased to 2.5V, Vref with Vramp magnitude relationship changes, and Comp2 becomes low level；Then Vramp continues to raise, and starts slowly to reduce after reaching 3.3V；During until Vramp drops to 2.5V, Vref with Vramp magnitude relationship changes again, and Comp2 becomes high level.
As shown in Figure 4, being the internal circuit diagram of the first Digital Logic control circuit and the second Digital Logic control circuit, the rising edge CountEn level upset of signal Comp, Mux becomes high level；Resetting during described sawtooth period pulse digital signal high level, CountEn becomes low level, and Mux becomes low level；Comp1, CountEn1, Mux1 of the first Digital Logic control circuit in Comp, CountEn, Mux corresponding diagram 2 respectively and Comp2, CountEn2, Mux2 of the second Digital Logic control circuit.
So, the moment (within 10ns) that Comp2 uprises, described data selector 0 gates 0V, Vramp=2.5V ＞ 0V, and Comp2 becomes low level, and CountEn2 becomes high level, and the second enumerator starts counting up.
Vramp continues to decline subsequently, and as Vramp=0V, Comp2 becomes high level, and CountEn2 becomes low level, and the second enumerator stops counting and count value exported；Vramp continues to decline subsequently, until next sawtooth period pulse digital signal arrives, and system reset, enter next cycle.
Described first MUX, the first comparator, the first Digital Logic control circuit and the analog to digital conversion circuit of the first enumerator composition, ultimate principle is identical with negative-feedback circuit.
In conjunction with Fig. 2 and Fig. 3, first Digital Logic control circuit and the first enumerator reset when sawtooth period pulse arrives, the selection signal Mux1 of the first MUX of the first Digital Logic control circuit output becomes low level, first MUX gating reference voltage Vref, now Vref is more than Vramp, output signal Comp1 of the first comparator is high level, and the enable signal CountEn1 of the first enumerator of the first Digital Logic control circuit output is low level, and the first enumerator does not counts.
Vramp quickly raises subsequently；When Vramp is increased to 2.5V, Vref with Vramp magnitude relationship changes, and Comp1 becomes low level；Then Vramp continues to raise, and starts slowly to reduce after reaching 3.3V；During until Vramp drops to 2.5V, Vref with Vramp magnitude relationship changes again, and Comp1 becomes high level；First Digital Logic control circuit makes CountEn1 level overturn at the rising edge of signal Comp1, makes Mux1 become high level.
So, the moment (＜ 10ns) that Comp1 uprises, first MUX gates voltage Vin to be measured, and (the analog-digital converter range in the present embodiment is (-2.5V, 2.5V)), Vramp=2.5V ＞ Vin, Comp1 becomes low level, and CountEn1 becomes high level, and the first enumerator starts counting up.
Vramp continues to decline subsequently, and as Vramp=Vin, Comp1 becomes high level, and CountEn1 becomes low level, and described first enumerator stops counting and count value exported；Vramp continues to decline subsequently, until next sawtooth period pulse digital signal arrives, and system reset, enter next cycle.
During system work, adjusted the slope of sawtooth waveforms Vramp by PWM negative feedback, make the count value of the second enumerator equal to ideal value RefNum；Finally by count value HexOut and formula Vin/ (the RefNum-HexOut)=Vref/RefNum of the first enumerator, the size of voltage to be measured can be calculated.
In sum, the analog-digital converter of the present utility model control by Digital Logical Circuits, makes in transformation process, and the error that the time delay of the intermediary device such as comparator causes is cancelled, and then reach to improve performance, reduce the purpose of cost, simultaneously by the design of digital circuit, make the component parameter of analog circuit that the impact of systematic function to be reduced, compared with traditional integral analogue-to-digital converter, it is more easy to debugging, saves development cost, shorten the construction cycle.
The above; it is only this utility model patent preferred embodiment; but the protection domain of this utility model patent is not limited thereto; any those familiar with the art is in the scope disclosed in this utility model patent; technical scheme and utility model thereof according to this utility model patent conceive equivalent or change in addition, broadly fall into the protection domain of this utility model patent.
Claims (6)
1. high performance-price ratio simple integral pattern number converter, including sawtooth generator, negative-feedback circuit and analog to digital conversion circuit, analog-digital conversion circuit as described is made up of the first MUX, the first comparator, the first Digital Logic control circuit and the first enumerator, it is characterised in that:
The sawtooth waveforms outfan of described sawtooth generator connects an input and an input of the first comparator of negative-feedback circuit；The outfan of described negative-feedback circuit connects the slope adjustment input of sawtooth generator；The reference voltage of outside input connects another input of negative-feedback circuit and an input of the first MUX respectively；The voltage to be measured of outside input connects another input of the first MUX；The outfan of described first MUX connects another input of the first comparator；The outfan of described first comparator connects the input of the first Digital Logic control circuit；The sawtooth period pulse digital signal of outside input connects sawtooth generator, negative-feedback circuit, the first Digital Logic control circuit and the clear terminal of the first enumerator；Two outfans of described first Digital Logic control circuit connect selection signal input part and the enable signal input part of the first enumerator of the first MUX respectively；The outfan of described first enumerator is connected to system output.
High performance-price ratio simple integral pattern number converter the most according to claim 1, it is characterized in that: the sawtooth waveforms outfan of described sawtooth generator connects the inverting input of the first comparator, the outfan of described first MUX connects the normal phase input end of the first comparator.
High performance-price ratio simple integral pattern number converter the most according to claim 1, it is characterised in that: the negative feedback control mode of described negative-feedback circuit is pwm pulse width modulated.
nullHigh performance-price ratio simple integral pattern number converter the most according to claim 3，It is characterized in that: described negative-feedback circuit is by the second MUX、Second comparator、Second Digital Logic control circuit、Second enumerator and PWM module composition，Two inputs of described second MUX connect reference voltage and the 0V of outside input respectively，The outfan of described second MUX connects the normal phase input end of the second comparator，The outfan of described sawtooth generator connects the inverting input of the second comparator，The outfan of described second comparator connects the input of the second Digital Logic control circuit，Two outfans of described second Digital Logic control circuit connect selection input and the enable input of the second enumerator of the second MUX respectively，The outfan of described second enumerator connects the input of PWM module，The outfan of described PWM module connects the slope adjustment input of sawtooth generator，The sawtooth period pulse digital signal of outside input connects the second Digital Logic control circuit and the clear terminal of the second enumerator.
High performance-price ratio simple integral pattern number converter the most according to claim 1, it is characterised in that: the slope adjustment of described sawtooth generator, realize by the way of constant-current source controls charge storage module electric discharge.
High performance-price ratio simple integral pattern number converter the most according to claim 5, it is characterized in that: described sawtooth generator is made up of constant-current source, charge storage module and the 3rd comparator, the constant current output end of described constant-current source connects the discharge and recharge input of charge storage module；The level output end of described charge storage module connects an input of negative-feedback circuit, and the first comparator and the inverting input of the 3rd comparator；The normal phase input end of described 3rd comparator connects fixed level；The outfan of described 3rd comparator connects an input of constant-current source；The outfan of described negative-feedback circuit connects another input of constant-current source；The sawtooth period pulse digital signal of outside input connects the clear terminal of constant-current source.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105811987A (en) * | 2016-03-09 | 2016-07-27 | 广州龙之杰科技有限公司 | High-cost performance single-integral analog-to-digital converter and conversion method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105811987A (en) * | 2016-03-09 | 2016-07-27 | 广州龙之杰科技有限公司 | High-cost performance single-integral analog-to-digital converter and conversion method thereof |
| CN105811987B (en) * | 2016-03-09 | 2022-12-09 | 广州龙之杰科技有限公司 | Single-integration analog-to-digital converter and conversion method thereof |
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