CN111835355A - TDC (time-to-digital converter) -based time interval digital converter with high repetition rate - Google Patents

TDC (time-to-digital converter) -based time interval digital converter with high repetition rate Download PDF

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CN111835355A
CN111835355A CN202010710991.8A CN202010710991A CN111835355A CN 111835355 A CN111835355 A CN 111835355A CN 202010710991 A CN202010710991 A CN 202010710991A CN 111835355 A CN111835355 A CN 111835355A
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flip
flop
trigger
gate
comparator
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CN111835355B (en
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安永泉
禹健
王萌洁
李晋华
王志斌
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North University of China
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention belongs to the technical field of time interval measurement, and particularly relates to a TDC-based time interval digital converter with a high repetition rate, which comprises a TDC circuit and a TAC circuit, wherein the TDC circuit comprises a first comparator, a second comparator, a first trigger, a second trigger, a third trigger, a fourth trigger, a fifth trigger, a sixth trigger, a seventh trigger, an eighth trigger, a ninth trigger and a tenth trigger, the positive end of the first comparator is connected with a starting voltage, the negative end of the first comparator is connected with a threshold voltage, and the output end of the first comparator is connected with a CP control end of the first trigger. The TDC circuit does not need to carry out special reset operation, and solves the problems that in the prior art, an analog interpolation method based on the time-amplitude conversion principle is adopted to measure time intervals, the measurement result is sensitive to temperature, and the measurement response speed of the circuit is slow during continuous measurement. The invention is used for measuring time intervals.

Description

TDC (time-to-digital converter) -based time interval digital converter with high repetition rate
Technical Field
The invention belongs to the technical field of time interval measurement, and particularly relates to a TDC (time-to-digital converter) based time interval digital converter with a high repetition rate.
Background
The traditional time interval digital converter mostly adopts an analog interpolation method based on a time-amplitude conversion principle to realize the measurement of time intervals, the principle is to convert the length of time into amplitude, combine a direct counting method and the time-amplitude conversion principle to realize the measurement of time intervals with wide range and high resolution, and then output the size of the time intervals to be measured in a digital mode through a TDC circuit.
However, the conventional high-resolution time interval measurement technique has the following problems in measuring time intervals: 1) during continuous measurement, after each time of analog-digital conversion of the voltage of the traditional TDC circuit through the ADC circuit, special reset is required, the next time interval digital conversion can be carried out, and the conversion rate in unit time is low; 2) when the long-distance measurement is carried out, a drift phenomenon exists; 3) the measurement results are sensitive to temperature.
Disclosure of Invention
Aiming at the technical problems that the traditional high-resolution time interval measurement technology is low in conversion rate in unit time, has a drift phenomenon in long-distance measurement and is sensitive to temperature of a measurement result, the invention provides the TDC-based time interval digital converter which is wide in measurement range, high in precision and high in speed.
In order to solve the technical problems, the invention adopts the technical scheme that:
the TDC circuit comprises a first comparator, a second comparator, a first trigger, a second trigger, a third trigger, a fourth trigger, a fifth trigger, a sixth trigger, a seventh trigger, an eighth trigger, a ninth trigger and a tenth trigger, wherein the positive end of the first comparator is connected with a starting voltage, the negative end of the first comparator is connected with a threshold voltage, the output end of the first comparator is connected with a CP control end of the first trigger, the Q end of the first trigger is connected with the D end of the second trigger, and the third trigger is connected with the D end of the second triggerThe Q end of the second trigger is connected with the D end of the third trigger; the positive end of the second comparator is connected with an ending voltage, the negative end of the second comparator is connected with a threshold voltage, the output end of the second comparator is connected with a CP control end of a fourth trigger, the Q end of the fourth trigger is connected with the D end of a fifth trigger, and the Q end of the fifth trigger is connected with the D end of a sixth trigger; the Q end of the first trigger is connected with one input end of the first exclusive-OR gate, the other input end of the first exclusive-OR gate is respectively connected with the Q end of the second trigger and the Q end of the third trigger through the first multi-way switch, the D end of the first trigger is respectively connected with the Q end of the second trigger and the Q end of the third trigger through the second multi-way switch, the D end of the fourth trigger is respectively connected with the Q end of the fourth trigger and the fourth multi-way switch through the third multi-way switch, and the fourth multi-way switch is respectively connected with the Q end of the fifth trigger
Figure BDA0002596535960000021
Of terminal, sixth flip-flop
Figure BDA0002596535960000022
The D end of the fourth trigger is connected with one input end of a second exclusive-OR gate, the other input end of the second exclusive-OR gate is respectively connected with the Q end of a fifth trigger and the Q end of a sixth trigger through a fifth multi-way switch, the TAC circuit comprises a first TAC circuit and a second TAC circuit, the output end of the first exclusive-OR gate is respectively connected with the D ends of the first TAC circuit and the seventh trigger, the output end of the second exclusive-OR gate is respectively connected with the D ends of the second TAC circuit and the eighth trigger, the Q end of the seventh trigger is connected with the D end of the ninth trigger, the Q end of the seventh trigger and the Q end of the ninth trigger are respectively connected with the two input ends of the first exclusive-OR gate, the Q end of the eighth trigger is connected with the D end of the tenth trigger, and the Q ends of the eighth trigger and the tenth triggers are respectively connected with the two input ends of the second exclusive-OR gate, the output ends of the first TAC circuit and the second TAC circuit are connected to the input end of the FPGA module, and the first comparator, the first trigger and the second trigger are connected to the input end of the FPGA moduleThe second comparator, the fourth trigger, the fifth trigger, the sixth trigger, the second exclusive-or gate and the second TAC circuit form a lower interpolation branch.
The R ends of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth and tenth triggers are all connected with a Reset signal Reset, and the CP ends of the second, third, fifth, sixth, seventh, eighth, ninth and tenth triggers are all connected with a clock signal CLK.
The first multi-way switch, the second multi-way switch, the fourth multi-way switch and the fifth multi-way switch are all connected with an interpolation precision mode control bit, the third multi-way switch is connected with an output end of a third exclusive-or gate, the starting voltage sends a Start signal, the Start signal is sent to a CP end of the first trigger through the first comparator, the ending voltage sends a Stop signal, and the Stop signal is sent to a CP end of the fourth trigger through the second comparator.
The first TAC circuit and the second TAC circuit respectively comprise an integrating capacitor, an output current source drive end logic control circuit and a temperature drift suppression circuit, a first constant current source, a second constant current source and a third constant current source are arranged at the input end of the integrating capacitor, the output end of the integrating capacitor is connected with an A/D converter, the first constant current source flows into the integrating capacitor, the second constant current source and the third constant current source flow out of the integrating capacitor, the input end of the first constant current source is connected with the temperature drift suppression circuit, the second constant current source and the third constant current source are both connected with the output current source drive end logic control circuit, the output current source drive end logic control circuit comprises a third comparator, a D trigger, a logic gate, a third OR gate, a first NOT gate and a second NOT gate, the output end of the integrating capacitor is connected with the positive end of the third comparator, and the negative end of the third comparator is grounded, the output end of the third comparator is connected with the D end of a D trigger, the CP end of the D trigger is connected with a CLK signal, the Q end of the D trigger is connected with one end of a AND logic gate, the other end of the AND logic gate is connected with an integral pulse signal, the output end of the AND logic gate is connected with one input end of a third OR gate, the Q end of the D trigger is connected with the other input end of the third OR gate through a first NOT gate, the output end of the third OR gate is connected with a first BJT switch, the output end of the AND logic gate is connected with a second BJT switch through a second NOT gate, the first BJT switch and the second BJT switch respectively control the switches of a second constant current source and a third constant current source, the temperature drift suppression circuit comprises an ADC (analog-to-digital converter), a D/A converter and an analog PID control part, and the output end of the integral capacitor is connected with an A/D converter, the A/D converter is connected with the ADC through sampling, the ADC is connected with the D/A converter through a sixth multi-way switch, the D/A converter is connected with an analog PID control part, and the analog PID control part is connected with the positive end of the first constant current source.
The D flip-flop is triggered by a rising edge.
A method for controlling a TDC-based high repetition rate time interval digitizer, comprising the steps of:
s1, selecting a working mode, wherein the TDC circuit has two working modes, the switching of the working modes is controlled by an interpolation precision mode control bit, when the output of the interpolation precision mode control bit is 0, the working mode is a no dead zone mode, and when the output of the interpolation precision mode control bit is 1, the working mode is a high linear mode;
s2, generating an integral pulse signal;
s3, performing time-amplitude conversion to obtain a first integral pulse signal T1Second integral pulse signal T2；
S4, calculating time interval T12；
S5, calculating the total time interval T, using the formula T ═ T12+T1-T2And calculating T, and outputting the size of the total time interval T in a digital mode.
The method for generating the integration pulse signal in S2 includes: the D end and the Q end of the fourth trigger are connected through a third multi-way switch, a Start signal is sent out, an upper interpolation branch works,before the Stop signal comes, the lower interpolation branch is not allowed to work; after the Stop signal comes, the lower interpolation branch works; if the upper interpolation branch is not working, the lower interpolation branch is not working under any condition, the upper interpolation branch generates the first integral pulse signal T1The lower interpolation branch generates a second integral pulse signal T2。
The first integration pulse signal T is obtained in S31Second integral pulse signal T2The method comprises the following steps: first integral pulse signal T1Second integral pulse signal T2Respectively performing time-amplitude conversion by the first TAC circuit and the second TAC circuit, and generating T by charging and discharging the capacitor through current1/T2The voltage with proportional length is subjected to analog-digital conversion by ADC sampling to obtain a first integral pulse signal T1Second integral pulse signal T2The value of (c).
The time interval T is calculated in the step S412The method comprises the following steps: the two outputs of the TAC circuit are connected to an FPGA module where T is calculated by a 16-bit counter12Every clock rising edge, the Q value of the counter is increased by 1 until the rising edge of the Stop signal comes, and counting is stopped according to T12＝Q*TCLKMeasuring the time interval T12A value of (A), the TCLKIs the period of the clock signal.
Compared with the prior art, the invention has the following beneficial effects:
the TDC circuit does not need to carry out special reset operation, and solves the problems that in the prior art, an analog interpolation method based on the time-amplitude conversion principle is adopted to measure time intervals, the measurement result is sensitive to temperature, and the measurement response speed of the circuit is slow during continuous measurement.
Drawings
FIG. 1 is a circuit diagram of the present invention;
FIG. 2 is a TAC circuit composition diagram of the present invention;
FIG. 3 is a schematic diagram of a TDC circuit in a high linearity mode of operation according to the present invention;
FIG. 4 is a diagram of a TDC circuit in a no-dead-zone operating mode according to the present invention;
FIG. 5 is a graph of the integrated pulse signal generated in the high linearity mode of the present invention;
FIG. 6 is a signal waveform diagram of the main circuit of the TDC of the present invention operating in a high linearity mode;
FIG. 7 is a sampling process in the high linearity mode of the present invention;
FIG. 8 illustrates the generation of an integrated pulse signal in the no dead band mode of the present invention;
FIG. 9 is a signal waveform diagram of the main circuit of the TDC of the present invention operating in the no dead zone mode;
FIG. 10 is a sampling process in the no dead zone mode of the present invention;
wherein: 1 is a TDC circuit, 2 is a first comparator, 3 is a second comparator, TDA1 is a first flip-flop, TDA2 is a second flip-flop, TDA3 is a third flip-flop, TDO1 is a fourth flip-flop, TDO2 is a fifth flip-flop, TDO3 is a sixth flip-flop, TDA4 is a seventh flip-flop, TDO4 is an eighth flip-flop, TDA5 is a ninth flip-flop, TDO5 is a tenth flip-flop, VSTARTTo start voltage, VTHIs a threshold voltage, VSTOPTo terminate the voltage, Q1Is a first multi-way switch, Q2Is a second multi-way switch, Q3Is a third multi-way switch, Q4Is a fourth multi-way switch, Q5Is a fifth multi-way switch, Q6The digital filter is a sixth multi-way switch, 4 is a first TAC circuit, 5 is a second TAC circuit, 6 is an FPGA module, 8 is an integrating capacitor, 9 is an output current source driving end logic control circuit, 10 is a temperature drift suppression circuit, 11 is a first constant current source, 12 is a second constant current source, 13 is a third constant current source, 14 is a third comparator, 15 is a D flip-flop, 16 is a first or gate, 17 is a second or gate, 18 is an and logic gate, 19 is a third or gate, 20 is a first not gate, 21 is a second not gate, 22 is a first BJT switch, 23 is a second BJT switch, 24 is an ADC sample, 25 is a D/a converter, 26 is an analog PID control part, 27 is an interpolation precision mode control bit, 28 is an a/D converter, XOR1 is a first XOR gate, XOR2 is a second XOR gate, and XOR3 is a third XOR gate.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
A TDC-based high repetition rate time interval digital converter, as shown in FIG. 1, includes a TDC circuit 1 and a TAC circuit, the TDC circuit 1 includes a first comparator 2, a second comparator 3, a first flip-flop TDA1, a second flip-flop TDA2, a third flip-flop TDA3, a fourth flip-flop TDO1, a fifth flip-flop TDO2, a sixth flip-flop TDO3, a seventh flip-flop TDA4, an eighth flip-flop TDO4, a ninth flip-flop TDA5, a tenth flip-flop TDO5, a start voltage V is connected to the positive terminal of the first comparator 2STARTThe negative end of the first comparator 2 is connected with a threshold voltage VTHThe output end of the first comparator 2 is connected with the CP control end of the first flip-flop TDA1, the Q end of the first flip-flop TDA1 is connected with the D end of the second flip-flop TDA2, and the Q end of the second flip-flop TDA2 is connected with the D end of the third flip-flop TDA 3; the positive terminal of the second comparator 3 is connected to an end voltage VSTOPThe negative terminal of the second comparator 3 is connected to a threshold voltage VTHThe output end of the second comparator 3 is connected with the CP control end of the fourth flip-flop TDO1, the Q end of the fourth flip-flop TDO1 is connected with the D end of the fifth flip-flop TDO2, and the Q end of the fifth flip-flop TDO2 is connected with the D end of the sixth flip-flop TDO 3; the Q end of the first trigger TDA1 is connected with one input end of a first exclusive-OR gate XOR1, and the other input end of the first exclusive-OR gate XOR1 passes through a first multi-way switch Q1Respectively connected with Q terminal of the second flip-flop TDA2 and Q terminal of the third flip-flop TDA3, and D terminal of the first flip-flop TDA1 is connected with the second multi-way switch Q2Respectively connected with the Q terminal of the second flip-flop TDA2 and the Q terminal of the third flip-flop TDA3, and the D terminal of the fourth flip-flop TDO1 is connected with the Q terminal of the third flip-flop Q3Respectively connected with the Q end of the fourth trigger TDO1 and a fourth multi-way switch Q4Connected, a fourth multi-way switch Q4Respectively with a fifth trigger TDO2
Figure BDA0002596535960000071
Of end, sixth trigger TDO3
Figure BDA0002596535960000072
The D terminal of the fourth flip-flop TDO1 is connected with one input terminal of a second exclusive-OR gate XOR2, and the other input terminal of the second exclusive-OR gate XOR2 passes through a fifth multi-way switch Q5The Q terminal of the eighth flip-flop TDO4 is connected to the D terminal of the tenth flip-flop TDO5, the Q terminal of the eighth flip-flop TDO4, the Q terminal of the tenth flip-flop TDO5 is connected to the Q terminal of the second or gate 16, the Q terminal of the eighth flip-flop TDO5 is connected to the Q terminal of the second or gate 17, the Q terminal of the first flip-flop TDO2 and the Q terminal of the sixth flip-flop TDO3, the TAC circuits include the first TAC circuit 4 and the second TAC circuit 5, the output terminal of the first XOR gate XOR1 is connected to the D terminals of the first TAC circuit 4 and the seventh flip-flop TDA4, the output terminal of the second XOR gate XOR2 is connected to the D terminals of the second TAC circuit 5 and the eighth flip-flop TDO4, the Q terminal of the seventh flip-flop TDA4 is connected to the D terminal of the ninth flip-flop TDA5, the Q terminal of the seventh flip-flop TDA4 and the ninth flip-flop TDA5 are connected to the two input terminals of the first or gate 16, the Q terminal of the eighth flip-flop TDO4 is connected to the two input terminal of, The first flip-flop TDA1, the second flip-flop TDA2, the third flip-flop TDA3, the first exclusive or gate XOR1 and the first TAC circuit 4 constitute an upper interpolation branch, and the second comparator 3, the fourth flip-flop TDO1, the fifth flip-flop TDO2, the sixth flip-flop TDO3, the second exclusive or gate XOR2 and the second TAC circuit 5 constitute a lower interpolation branch.
Further, R terminals of the first flip-flop TDA1, the second flip-flop TDA2, the third flip-flop TDA3, the fourth flip-flop TDO1, the fifth flip-flop TDO2, the sixth flip-flop TDO3, the seventh flip-flop TDA4, the eighth flip-flop TDO4, the ninth flip-flop TDA5, and the tenth flip-flop TDO5 are all connected with a Reset signal Reset, and CP terminals of the second flip-flop TDA2, the third flip-flop TDA3, the fifth flip-flop TDO2, the sixth flip-flop TDO3, the seventh flip-flop TDA4, the eighth flip-flop TDO4, the ninth flip-flop TDA5, and the tenth flip-flop TDO5 are all connected with a clock signal CLK.
Further, a first multi-way switch Q1A second multi-way switch Q2And a fourth multi-way switch Q4And a fifth multi-way switch Q5Are all connected with an interpolation precision mode control bit 27 and a third multi-way switch Q3A third exclusive or gate XOR3 is connected, starting with a voltage VSTARTSending out a Start signal, sending the Start signal into the CP end of a first trigger TDA1 through a first comparator 2, and ending a voltage VSTOPThe Stop signal is output and fed via the second comparator 3 to the CP side of the fourth flip-flop TDO 1.
Further, as shown in fig. 2, the first TAC circuit 4 and the second TAC circuit 5 each include an integrating capacitor 8, an output current source drive end logic control circuit 9, and a temperature drift suppression circuit 10, the input end of the integrating capacitor 8 is provided with a first constant current source 11, a second constant current source 12, and a third constant current source 13, the first constant current source 11 flows into the integrating capacitor 8, the second constant current source 12, and the third constant current source 13 flow out of the integrating capacitor 8, the input end of the first constant current source 11 is connected with the temperature drift suppression circuit 10, the second constant current source 12, and the third constant current source 13 are both connected with the output current source drive end logic control circuit 9, the output current source drive end logic control circuit 9 includes a third comparator 14, a D flip-flop 15, a logic gate 18, a third or gate 19, a first not gate 20, and a second not gate 21, the output end of the integrating capacitor 8 is connected with the positive end of the third comparator 14, the negative end of the, the output end of the third comparator 14 is connected with the D end of the D flip-flop 15, the CP end of the D flip-flop 15 is connected with the CLK signal, the Q end of the D flip-flop 15 is connected with one end of the and logic gate 18, the other end of the and logic gate 18 is connected with the integrated pulse signal, the output end of the and logic gate 18 is connected with one input end of the third or gate 19, the Q end of the D flip-flop 15 is connected with the other input end of the third or gate 19 through the first not gate 20, the output end of the third or gate 19 is connected with the first BJT switch 22, the output end of the and logic gate 18 is connected with the second BJT switch 23 through the second not gate 21, the first BJT switch 22 and the second BJT switch 23 respectively control the switching of the second constant current source 12 and the third constant current source 13, the temperature drift suppression circuit 10 includes an ADC sample 24, a D/a converter 25 and an analog PID control part 26, the output end of the integrating, the A/D converter is connected to an ADC sample 24, and the ADC sample 24 passes through a sixth multi-way switch Q6And D/A conversionThe D/a converter 25 is connected, the analog PID control part 26 is connected to the D/a converter 25, and the analog PID control part 26 is connected to the positive terminal of the first constant current source 11.
Further, preferably, the D flip-flop 15 is a rising edge flip-flop.
A method for controlling a TDC-based high repetition rate time interval digitizer, comprising the steps of:
s1, selecting a working mode, wherein the TDC circuit has two working modes, the switching of the working modes is controlled by an interpolation precision mode control bit, when the output of the interpolation precision mode control bit is 0, the working mode is a no dead zone mode, and when the output of the interpolation precision mode control bit is 1, the working mode is a high linear mode;
high linearity mode as shown in FIG. 3, generates an integrated pulse signal
The above interpolation branch generates an integral pulse signal T1For example, as shown in FIG. 5.
In the high linearity mode, at the initial time, the Reset signal Reset sets the Q terminal of the first, second, and third flip-flops TDA1, TDA2, and TDA3 to zero, and the Q terminal of the first, second, and third flip-flops TDA1, TDA2, and TDA3
Figure BDA0002596535960000091
End placement 1; at this time, the output T of the first XOR gate XOR11Is 0. Of the third flip-flop TDA3
Figure BDA0002596535960000092
Terminal passes through a second multi-way switch Q2Connected to the D terminal of the first flip-flop TDA1, the D terminal of the first flip-flop TDA1 at the reset time is therefore 1.
Clock signal t1At a certain time of the cycle, the event signal Start/Stop arrives, the Start/Stop signal is sent to the CP end of the first flip-flop TDA1 through the comparator, and the Q end of the first flip-flop TDA1 is 1. One path of the Q terminal of the first flip-flop TDA1 is directly sent to the first XOR gate XOR1, and at this time, two paths of the input of the first XOR gate XOR1 are respectively 1 and 0 at the Q terminals of the first flip-flop TDA1 and the third flip-flop TDA 3. Therefore, the output terminal T of the first XOR gate XOR11Becomes 1. Time-of-arrivalClock signal t2At the falling edge of the cycle, the Q terminal of the third flip-flop TDA3 is set to 1, passing through the first multi-way switch Q1Sending the signals into a first exclusive-or gate XOR1, wherein the Q ends of two paths of input first flip-flop TDA1 and third flip-flop TDA3 of the first exclusive-or gate XOR1 are 1 and 1 respectively, and outputting T1Becomes 0. The Q terminal of the third flip-flop TDA3 and the D terminal of the first flip-flop TDA1 are zeroed.
Over a number of clock cycles, the clock signal tnAt a certain time of the cycle, the next event signal Start/Stop arrives, at this time, the D terminal of the first flip-flop TDA1 is 0, the Q terminal of the first flip-flop TDA1 is 0, one path of the Q terminal of the first flip-flop TDA1 is directly sent to the first XOR gate XOR1, at this time, two paths of the first XOR gate XOR1 are input to the Q terminals of the first flip-flop TDA1 and the third flip-flop TDA3, which are respectively 0 and 1. Therefore, the output terminal T of the first XOR gate XOR11Becomes 1. The other path of the first flip-flop TDA1 is fed to the next second flip-flop TDA2, and then fed to the third flip-flop TDA3 via the second flip-flop TDA 2. To the next clock cycle (t)n+1Cycle), the Q terminal of the third flip-flop TDA3 is set to 0, passing through the first multi-way switch Q1Sending the signals to a first exclusive-or gate XOR1, wherein the Q end of the first flip-flop TDA1 and the Q end of the third flip-flop TDA3 of the two paths of input of the first exclusive-or gate XOR1 are respectively 0 and 0, and outputting T1Becomes 0. The Q terminal of the third flip-flop TDA3 and the D terminal of the first flip-flop TDA1 are set to 1. The state of each signal in the circuit is restored to the Reset time as shown in fig. 6.
The integrated pulse signal T in the high linearity mode of the TDC circuit is generated by the above process1. In the same way, T can be obtained2。
In order to obtain the output voltage value of the integrating capacitor before and after the pulse integration comes, the following sampling process is adopted in the high linearity mode:
taking 6 clock cycles as an example, the sampling time is the rising edge of the clock cycle.
The first sampling is an effective sampling of the output voltage in the hold state. Integration begins when the event signal Start/Stop arrives, and the second period (t) after integration begins3Period) ends the integration at the moment when the falling clock edge arrives.
The second sampling occurs after the integration begins, but the capacitor charging is not yet completed (i.e., the integration is not yet completed), and therefore the second sampling is an invalid sampling, and the data obtained by the invalid sampling is discarded.
The third sampling is effective sampling after the capacitor discharge is completed, and the acquired data is effective data.
The fourth sampling is valid sampling as the third sampling, and the acquired data is valid data at this time.
The fifth sampling, similar to the second sampling, occurs during the capacitor charging period, and the data of the invalid sampling is discarded.
The sixth sampling is similar to the third sampling, and occurs after the integration is finished, the sampling is effective sampling, the output voltage of the integration capacitor is stable at the moment, and the acquired data is effective data at the moment.
As shown in fig. 7, the sampling mode in the high linearity mode is performed at the time when the output voltage of the integrating capacitor is stabilized. This mode has the advantage of a high linearity of the integration process, with the disadvantage that the event signal Start/Stop can only be triggered during the interval period.
No dead band mode As shown in FIG. 4, an integrated pulse signal is generated
The above interpolation branch generates an integral pulse signal T1For example, the no dead zone mode generates the integration pulse signal T1/T2The working process comprises the following steps:
in the no dead zone mode, at an initial time, the Reset signal Reset sets the Q terminals of the first and second flip-flops TDA1 and TDA2 to zero, and the Q terminals of the first and second flip-flops TDA1 and TDA2 are Reset
Figure BDA0002596535960000111
End placement 1; at this time, the Q terminals of the two paths of inputs of the first flip-flop TDA1 and the second flip-flop TDA2 of the first exclusive or gate XOR1 are 0 and 0, respectively, and the output T of the first exclusive or gate XOR1 is1Is 0. Of the second flip-flop TDA2
Figure BDA0002596535960000121
Terminal passes through the second multi-way switchOff Q2Connected to the D terminal of the first flip-flop TDA1, the D terminal of the first flip-flop TDA1 at the reset time is therefore 1.
Clock signal t1At a certain time of the cycle, the event signal Start/Stop arrives, the Start/Stop signal is sent to the CP end of the first flip-flop TDA1 through the comparator, and the Q end of the first flip-flop TDA1 is 1. One path of the Q terminal of the first flip-flop TDA1 is directly sent to the first XOR gate XOR1, at this time, two paths of the first XOR gate XOR1 are input to the Q terminals of the first flip-flop TDA1 and the second flip-flop TDA2 and are respectively 1 and 0, and the output terminal T of the first XOR gate XOR11Is 1; the other of the Q terminals of the first flip-flop TDA1 is routed to the next second flip-flop TDA 2. To the clock signal t2At the rising edge of the cycle, the Q terminal of the second flip-flop TDA2 is set to 1, passing through the first multi-way switch Q1The signals are sent to a first exclusive-or gate XOR1, at this time, Q ends of two paths of input first flip-flop TDA1 and second flip-flop TDA2 of the first exclusive-or gate XOR1 are 1 and 1 respectively, so that an output T is output1Becomes 0. Of the second flip-flop TDA2
Figure BDA0002596535960000123
Terminal and the D terminal of the first flip-flop TDA1 are set to zero.
Over a number of clock cycles, the clock signal tnAt a certain time of the cycle, the next event signal Start/Stop arrives, at this time, the D terminal of the first flip-flop TDA1 is 0, the Q terminal of the first flip-flop TDA1 is 0, one path of the Q terminal of the first flip-flop TDA1 is directly sent to the first XOR gate XOR1, at this time, two paths of the first XOR gate XOR1 are input to the Q terminals of the first flip-flop TDA1 and the second flip-flop TDA2 are 0 and 1, respectively, so the output terminal T of the first XOR gate XOR1 is T terminal T11Is 1. The other way of the Q terminal of the first flip-flop TDA1 feeds into the next second flip-flop TDA 2. To the next clock cycle (t)n+1Cycle), the Q terminal of the second flip-flop TDA2 is set to 0, passing through the first multi-way switch Q1Sending the signals into a first exclusive-or gate XOR1, wherein the Q ends of two paths of input first flip-flop TDA1 and second flip-flop TDA2 of the first exclusive-or gate XOR1 are respectively 0 and 0, and outputting T1Becomes 0. Of the third flip-flop TDA3
Figure BDA0002596535960000122
Terminal 1 is set to terminal D of the first flip-flop TDA 1. The restoration of the state of each signal in the circuit to Reset time is shown in fig. 9.
The integrated pulse signal T in the TDC circuit no-dead-zone mode is generated by the process1. In the same way, T can be obtained2。
In order to obtain the output voltage value of the integrating capacitor before and after the pulse integration comes, the sampling process shown in fig. 10 is adopted in the no dead zone mode.
Taking 5 clock cycles as an example, 5 samples are all valid samples.
Sampling at time at Δ T from the rising edge of the clock is employed in the no dead band mode. When sampling occurs at the moment when the integration capacitor is not integrated, the sampling value is equal to the value before the integration moment; when sampling occurs at the integration moment of the integrating capacitor, the sampling value is added with delta UCIs the value at the end of integration. Since the rate of charging of the capacitor is constant, Δ UCIs a fixed value.
Therefore, the problem that sampling can not be carried out at the moment that the output of the integrating capacitor is not stable in a high linearity mode is well solved in the no-dead-zone mode.
S2, generating an integral pulse signal;
s3, performing time-amplitude conversion to obtain a first integral pulse signal T1Second integral pulse signal T2；
S4, calculating time interval T12；
S5, calculating the total time interval T, using the formula T ═ T12+T1-T2And calculating T, and outputting the size of the total time interval T in a digital mode.
Further, the method for generating the integration pulse signal in S2 is: the D end and the Q end of the fourth trigger are connected through a third multi-way switch, a Start signal is sent, the upper interpolation branch works, and the lower interpolation branch is not allowed to work before a Stop signal comes; and after the Stop signal comes, the lower interpolation branch works. If the upper interpolation branch is not active, the lower interpolation branch is not active under any conditions. The upper interpolation branch generates a first integral pulse signal T1Lower interpolation branchGenerating a second integration pulse signal T2. The first integration pulse signal T is obtained in S31Second integral pulse signal T2The method comprises the following steps: first integral pulse signal T1Second integral pulse signal T2Respectively performing time-amplitude conversion by the first TAC circuit and the second TAC circuit, and generating T by charging and discharging the capacitor through current1/T2The voltage with proportional length is subjected to analog-digital conversion by ADC sampling to obtain a first integral pulse signal T1Second integral pulse signal T2The value of (c).
Further, the time interval T is calculated in S412The method comprises the following steps: the two outputs of the TAC circuit are connected to an FPGA module where T is calculated by a 16-bit counter12Every clock rising edge, the Q value of the counter is increased by 1 until the rising edge of the Stop signal comes, and counting is stopped according to T12＝Q*TCLKMeasuring the time interval T12The value of (c).
Although only the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention within the knowledge of those skilled in the art, and all changes are encompassed in the scope of the present invention.

Claims (9)

1. A TDC-based high repetition rate time interval digitizer, comprising: the TDC circuit (1) comprises a TDC circuit (1) and a TAC circuit, wherein the TDC circuit (1) comprises a first comparator (2), a second comparator (3), a first trigger (TDA1), a second trigger (TDA2), a third trigger (TDA3), a fourth trigger (TDO1), a fifth trigger (TDO2), a sixth trigger (TDO3), a seventh trigger (TDA4), an eighth trigger (TDO4), a ninth trigger (TDA5) and a tenth trigger (TDO5), and the positive end of the first comparator (2) is connected with a starting voltage (V5)START) The negative end of the first comparator (2) is connected with a threshold voltage (V)TH) The output end of the first comparator (2) is connected with a CP control end of a first trigger (TDA1), and the second end of the first trigger is connected with a second comparatorThe Q end of a flip-flop (TDA1) is connected with the D end of a second flip-flop (TDA2), and the Q end of the second flip-flop (TDA2) is connected with the D end of a third flip-flop (TDA 3); the positive end of the second comparator (3) is connected with an end voltage (V)STOP) The negative end of the second comparator (3) is connected with a threshold voltage (V)TH) The output end of the second comparator (3) is connected with a CP control end of a fourth flip-flop (TDO1), the Q end of the fourth flip-flop (TDO1) is connected with the D end of a fifth flip-flop (TDO2), and the Q end of the fifth flip-flop (TDO2) is connected with the D end of a sixth flip-flop (TDO 3); the Q end of the first flip-flop (TDA1) is connected with one input end of a first exclusive-OR gate (XOR1), and the other input end of the first exclusive-OR gate (XOR1) passes through a first multi-way switch (Q)1) Respectively connected with the Q end of a second flip-flop (TDA2) and the Q end of a third flip-flop (TDA3), and the D end of the first flip-flop (TDA1) passes through a second multi-way switch (Q)2) Respectively connected with the Q terminal of a second flip-flop (TDA2) and the Q terminal of a third flip-flop (TDA3), and the D terminal of the fourth flip-flop (TDO1) is connected with a third multi-way switch (Q)3) Respectively connected with the Q end of a fourth trigger (TDO1) and a fourth multi-way switch (Q)4) Connected, the fourth multi-way switch (Q)4) Respectively with a fifth flip-flop (TDO2)
Figure FDA0002596535950000012
Of the end, sixth flip-flop (TDO3)
Figure FDA0002596535950000011
A terminal of the fourth flip-flop (TDO1) is connected with one input terminal of a second exclusive-OR gate (XOR2), and the other input terminal of the second exclusive-OR gate (XOR2) passes through a fifth multi-way switch (Q)5) The voltage regulator is connected with a Q end of a fifth flip-flop (TDO2) and a Q end of a sixth flip-flop (TDO3) respectively, the TAC circuits comprise a first TAC circuit (4) and a second TAC circuit (5), an output end of the first XOR gate (XOR1) is connected with D ends of the first TAC circuit (4) and the seventh flip-flop (TDA4) respectively, an output end of the second XOR gate (XOR2) is connected with D ends of the second TAC circuit (5) and the eighth flip-flop (TDO4) respectively, and a Q end of the seventh flip-flop (TDA4) is connected with a Q end of the ninth flip-flop (TD 3)A5) The Q terminal of the seventh flip-flop (TDA4) and the Q terminal of the ninth flip-flop (TDA5) are respectively connected to two input terminals of the first or gate (16), the Q terminal of the eighth flip-flop (TDO4) is connected to the D terminal of the tenth flip-flop (TDO5), the Q terminal of the eighth flip-flop (TDO4) and the Q terminal of the tenth flip-flop (TDO5) are respectively connected to two input terminals of the second or gate (17), the output terminals of the first TAC circuit (4) and the second TAC circuit (5) are respectively connected to the input terminals of the FPGA module (6), the first comparator (2), the first flip-flop (TDA1), the second flip-flop (TDA2), the third flip-flop (TDA3), the first exclusive or gate (XOR1) and the first TAC circuit (4) form an upper interpolation branch, and the second comparator (3), the fourth flip-flop (TDA1), the sixth flip-flop (TDO3) and the sixth flip-flop (TDO2) are respectively connected to the input terminals of the second or gate (17), and the second or gate (TDO5), and the output terminal of the FPGA module (4, The second exclusive or gate (XOR2) and the second TAC circuit (5) form a lower interpolation branch.
2. The TDC-based high repetition rate time interval digitizer as claimed in claim 1, wherein: the Reset signal Reset is connected to R terminals of the first flip-flop (TDA1), the second flip-flop (TDA2), the third flip-flop (TDA3), the fourth flip-flop (TDO1), the fifth flip-flop (TDO2), the sixth flip-flop (TDO3), the seventh flip-flop (TDA4), the eighth flip-flop (TDO4), the ninth flip-flop (TDA5), and the tenth flip-flop (TDO5), and CP terminals of the second flip-flop (TDA2), the third flip-flop (TDA3), the fifth flip-flop (TDO2), the sixth flip-flop (TDO3), the seventh flip-flop (TDA4), the eighth flip-flop (TDO4), the ninth flip-flop (TDA5), and the tenth flip-flop (TDO) are connected to a 5.
3. The TDC-based high repetition rate time interval digitizer as claimed in claim 1, wherein: said first multi-way switch (Q)1) A second multi-way switch (Q)2) And a fourth multi-way switch (Q)4) And a fifth multi-way switch (Q)5) Are connected with an interpolation precision mode control bit (27), and the third multi-way switch (Q)3) An output of a third exclusive-or gate (XOR3) is connected, the starting voltage (V)START) Sending a Start signal, said Start signal being fed in by a first comparator (2)CP terminal of first flip-flop (TDA1), the termination voltage (V)STOP) A Stop signal is generated, which is fed via a second comparator (3) to the CP terminal of a fourth flip-flop (TDO 1).
4. The TDC-based high repetition rate time interval digitizer as claimed in claim 1, wherein: the first TAC circuit (4) and the second TAC circuit (5) respectively comprise an integrating capacitor (8), an output current source driving end logic control circuit (9) and a temperature drift suppression circuit (10), the output end of the integrating capacitor (8) is connected with an A/D converter (28), the input end of the integrating capacitor (8) is provided with a first constant current source (11), a second constant current source (12) and a third constant current source (13), the first constant current source (11) flows into the integrating capacitor (8), the second constant current source (12) and the third constant current source (13) flow out of the integrating capacitor (8), the input end of the first constant current source (11) is connected with the temperature drift suppression circuit (10), the second constant current source (12) and the third constant current source (13) are respectively connected with the output current source driving end logic control circuit (9), and the output current source driving end logic control circuit (9) comprises a third comparator (14), A D trigger (15), a AND logic gate (18), a third OR gate (19), a first NOT gate (20) and a second NOT gate (21), wherein the output end of the integrating capacitor (8) is connected with the positive end of a third comparator (14), the negative end of the third comparator (14) is grounded, the output end of the third comparator (14) is connected with the D end of the D trigger (15), the CP end of the D trigger (15) is connected with a CLK signal, the Q end of the D trigger (15) is connected with one end of the AND logic gate (18), the other end of the AND logic gate (18) is connected with an integrating pulse signal, the output end of the AND logic gate (18) is connected with one input end of the third OR gate (19), the Q end of the D trigger (15) is connected with the other input end of the third OR gate (19) through the first NOT gate (20), and the output end of the third OR gate (19) is connected with a first BJT switch (22), the output end of the AND logic gate (18) is connected with a second BJT switch (23) through a second NOT gate (21), the first BJT switch (22) and the second BJT switch (23) respectively control the switch of a second constant current source (12) and a third constant current source (13), the temperature drift suppression circuit (10) comprises an ADC (analog to digital converter) sampling part (24), a D/A (digital to analog) converter (25) and an analog PID (proportion integration differentiation) control part (26),the output end of the integrating capacitor (8) is connected with an A/D converter, the A/D converter is connected with an ADC (analog to digital converter) sample (24), and the ADC sample (24) passes through a sixth multi-way switch (Q)6) The D/A converter (25) is connected, the D/A converter (25) is connected with an analog PID control part (26), and the analog PID control part (26) is connected with the positive end of the first constant current source (11).
5. The TDC-based high repetition rate time interval digitizer as claimed in claim 1, wherein: the D flip-flop (15) is triggered by a rising edge.
6. A method for controlling a TDC-based high repetition rate time interval digitizer, comprising: comprises the following steps:
s1, selecting a working mode, wherein the TDC circuit has two working modes, the switching of the working modes is controlled by an interpolation precision mode control bit, when the output of the interpolation precision mode control bit is 0, the working mode is a no dead zone mode, and when the output of the interpolation precision mode control bit is 1, the working mode is a high linear mode;
s2, generating an integral pulse signal;
s3, performing time-amplitude conversion to obtain a first integral pulse signal T1Second integral pulse signal T2；
S4, calculating time interval T12；
S5, calculating the total time interval T, using the formula T ═ T12+T1-T2And calculating T, and outputting the size of the total time interval T in a digital mode.
7. The method as claimed in claim 6, wherein the TDC further comprises: the method for generating the integration pulse signal in S2 includes: the D end and the Q end of the fourth trigger are connected through a third multi-way switch, a Start signal is sent, the upper interpolation branch works, and the lower interpolation branch is not allowed to work before a Stop signal comes; when Stop signal comes, the lower interpolation branch works(ii) a If the upper interpolation branch is not working, the lower interpolation branch is not working under any condition, the upper interpolation branch generates the first integral pulse signal T1The lower interpolation branch generates a second integral pulse signal T2。
8. The method as claimed in claim 6, wherein the TDC further comprises: the first integration pulse signal T is obtained in S31Second integral pulse signal T2The method comprises the following steps: first integral pulse signal T1Second integral pulse signal T2Respectively performing time-amplitude conversion by the first TAC circuit and the second TAC circuit, and generating T by charging and discharging the capacitor through current1/T2The voltage with proportional length is subjected to analog-digital conversion by ADC sampling to obtain a first integral pulse signal T1Second integral pulse signal T2The value of (c).
9. The method as claimed in claim 6, wherein the TDC further comprises: the time interval T is calculated in the step S412The method comprises the following steps: the two outputs of the TAC circuit are connected to an FPGA module where T is calculated by a 16-bit counter12Every clock rising edge, the Q value of the counter is increased by 1 until the rising edge of the Stop signal comes, and counting is stopped according to T12＝Q*TCLKMeasuring the time interval T12A value of (A), the TCLKIs the period of the clock signal.
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