CN109525239B - Digital output two-stage double-precision biomedical capacitance sensor interface circuit - Google Patents

Digital output two-stage double-precision biomedical capacitance sensor interface circuit Download PDF

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CN109525239B
CN109525239B CN201910067022.2A CN201910067022A CN109525239B CN 109525239 B CN109525239 B CN 109525239B CN 201910067022 A CN201910067022 A CN 201910067022A CN 109525239 B CN109525239 B CN 109525239B
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precision
capacitance
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signal
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CN109525239A (en
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徐卫林
王涛涛
刘俊昕
孙晓菲
韦保林
韦雪明
段吉海
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Guilin University of Electronic Technology
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017581—Coupling arrangements; Interface arrangements programmable
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Measurement Of Resistance Or Impedance (AREA)

Abstract

The invention discloses a digital output two-stage double-precision biomedical capacitance sensor interface circuit, which consists of a capacitance time conversion circuit and a time digital conversion circuit. A two-stage double-precision oscillator is adopted to generate low-precision and high-precision two paths of reference signals, double-precision measurement is carried out on the measured capacitor, and measurement time is reduced while the measurement precision of the capacitor is improved; meanwhile, the capacitance value of an external reference capacitor and the frequency division multiple of an externally controlled programmable frequency divider can be adjusted according to the size of the measured capacitor, so that the capacitance detection with non-fixed, wide range and high precision is realized; the logic control unit structure enables the double-precision reference signal to finish measurement in one period of the measured signal after frequency division, and reduces measurement time; the change of the capacitance is directly converted into digital coding output, so that an analog-digital conversion unit can be reduced, the analog-digital conversion unit can be conveniently cascaded with a subsequent chip, and the capacitance measurement error is reduced.

Description

Digital output two-stage double-precision biomedical capacitance sensor interface circuit
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to a digital output two-stage double-precision biomedical capacitance sensor interface circuit.
Background
Along with the development of wearable intelligent medical equipment and the rising of internet of things technology, biomedical capacitance sensors are widely used in various wearable intelligent medical equipment, and as a bridge bridging the sensors and processing chips, sensor interface circuits are also continuously developed and innovated. The requirements of people on wearable multi-physiological signal monitoring systems are continuously improved, the detectable precision of biomedical capacitance sensors is required to be continuously improved, the detection range is continuously expanded, the requirements on sensor interface circuits are also continuously improved, and low-error, high-precision and low-power consumption are the main challenges of the biomedical sensor interface circuits.
The interface circuit of the traditional biomedical capacitive sensor outputs a continuous analog voltage signal, cannot be directly cascaded with a signal processing chip, and needs to be converted again through an analog-to-digital converter. The traditional digital output type capacitive sensor interface circuit adopts a single-precision detection mode, the measurement range is fixed, and the measurement precision and flexibility are limited.
Disclosure of Invention
The invention aims to solve the problems of the traditional biomedical capacitance sensor interface circuit and provides a digital output two-stage double-precision biomedical capacitance sensor interface circuit.
In order to solve the problems, the invention is realized by the following technical scheme:
the digital output two-stage double-precision biomedical capacitance sensor interface circuit comprises an interface circuit body, wherein the interface circuit body consists of a capacitance time conversion circuit and a time digital conversion circuit.
The capacitance time conversion circuit comprises a reference capacitance C R2 Reference capacitance C R3 Sensor oscillator OSC 1 Low precision oscillator OSC 2 And a high precision oscillator OSC 3 The method comprises the steps of carrying out a first treatment on the surface of the Sensor oscillator OSC 1 The input end of the interface circuit body is formed and connected with the external tested capacitor C M Connecting; reference capacitor C R2 And reference capacitance C R3 Respectively connected with low-precision oscillators OSC 2 And a high precision oscillator OSC 3 Is provided; sensor oscillator OSC 1 The generated output signal T M To programmable frequency divider A 1 Is provided; low precision oscillator OSC 2 The generated output signal T L And a high precision oscillator OSC 3 The generated output signal T H Respectively send to a logic control module A 2 Is provided, 2 inputs of (c) are provided.
The time-to-digital conversion circuit comprises a programmable frequency divider A 1 Logic control module A 2 Counter CNT, registerReg0 and register Reg1; the externally input N-bit binary frequency division value N is sent to the programmable frequency divider A 1 Programmable frequency divider a 1 For output signal T M Signal go 2 N+1 After frequency division processing, the frequency division processing is sent to a logic control module A 2 Is provided; the counter CNT comprises 1 clock terminal and 2 n Each output end, logic control module A 2 The output counting clock signal CLK is sent to the clock end of the counter CNT; register Reg0 and register Reg1 are both 2 n The D flip-flops are composed, 1D flip-flop of the register Reg0 corresponds to 1D flip-flop of the register Reg1, and the D ends of the 2D flip-flops are simultaneously connected with one output end of the counter CNT; logic control module A 2 The output register clock signal Reg0_CLK is simultaneously coupled to 2 of register Reg0 n Clock end of D trigger, logic control module A 2 The output register clock signal Reg1_CLK is simultaneously connected to 2 of register Reg1 n Clock ends of the D triggers; 2 of register Reg0 n The output of the D flip-flop and 2 of register Reg1 n The output ends of the D flip-flops form 2 of the interface circuit body n+1 And a plurality of output terminals.
In the above scheme, the programmable frequency divider A 1 The frequency division value N (decimal number) inputted by the control terminal of (a) is composed of N-bit binary signals. Where N is related to the number of D flip-flops in registers Reg0 and Reg1, and N determines the programmable divider A 1 For output signal T M Frequency division ratio of the signal. If n=4, the value range of the frequency division value N is between 0 and 16. At this time, if the input 4-bit binary signal is 0000, the frequency division value n=0, the programmable divider a 1 For output signal T M Dividing the frequency of the signal by 2; if the input 4-bit binary signal is 0011, the frequency division value n=3, programmable divider a 1 For output signal T M The signal is divided by 16.
Compared with the prior art, the invention has the following characteristics:
1. a two-stage double-precision oscillator is adopted to generate low-precision and high-precision two paths of reference signals, double-precision measurement is carried out on the measured capacitor, and measurement time is reduced while measurement precision is improved;
2. the external reference capacitor and the external control programmable frequency divider structure are adopted, the reference capacitor value can be properly adjusted according to the size of the measured capacitor, and the frequency division multiple is controlled by the outside to realize the non-fixed, wide-range and high-precision capacitor detection;
3. the logic control unit structure is adopted, so that the double-precision reference signal can finish measurement in one period of the measured signal after frequency division, and the measurement time is reduced; the change of the capacitance is directly converted into digital coding output, so that an analog-digital conversion unit can be reduced, the analog-digital conversion unit is conveniently cascaded with a subsequent chip, and the measurement error is reduced.
Drawings
Fig. 1 is a block diagram (n=4) of a digital output two-stage dual-precision biomedical capacitive sensor interface circuit.
FIG. 2 is a timing diagram of a logic control module.
Fig. 3 is a simulation diagram of the square wave period generated by the oscillator at different supply voltages.
Fig. 4 is a simulation of the square wave period generated by the oscillator at different temperatures.
FIG. 5 is D CM And outputting a result and a relative error simulation diagram.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings, in conjunction with the specific example (n=4).
A digital output two-stage double-precision biomedical capacitance sensor interface circuit is shown in figure 1, and consists of a capacitance time conversion circuit and a time digital conversion circuit.
The capacitance time conversion circuit comprises a reference capacitance C R2 Reference capacitance C R3 Sensor oscillator OSC 1 Low precision oscillator OSC 2 And a high precision oscillator OSC 3 . Sensor oscillator OSC 1 The input end of the interface circuit body and the external tested capacitor C are formed M Connected with reference capacitor C R2 And reference capacitance C R3 Respectively connected with low-precision oscillatorsOSC 2 And a high precision oscillator OSC 3 Is provided. Sensor oscillator OSC 1 The generated output signal T M To programmable frequency divider A 1 Low precision oscillator OSC 2 The generated output signal T L And a high precision oscillator OSC 3 The generated output signal T H Respectively send to a logic control module A 2 Is provided, 2 inputs of (c) are provided.
The time-to-digital conversion circuit comprises a programmable frequency divider A 1 Logic control module A 2 A counter CNT, a register Reg0 and a register Reg1. Register Reg0 is formed by 16D flip-flops DFF 0_0 ～DFF 0_15 Register Reg1 consists of 16D flip-flops DFF 1_0 ～DFF 1_15 Composition is prepared. The counter CNT includes 1 clock terminal and 16 output terminals Q0 to Q15. The externally input 4-bit binary frequency division value N (10) is sent to the programmable frequency divider A 1 Is provided. Programmable frequency divider A 1 For output signal T M Signal go 2 N+1 After frequency division processing, the frequency division processing is sent to a logic control module A 2 Is provided. Logic control module A 2 The output count clock signal CLK is supplied to the clock terminal of the counter CNT. The 1D flip-flop of register Reg0 corresponds to the 1D flip-flop of register Reg1, and the D terminals of these 2D flip-flops are simultaneously connected to one of the output terminals of counter CNT. Logic control module A 2 The output register clock signal Reg0_CLK is simultaneously connected with the clock ends of 16D flip-flops of the register Reg0, and the logic control module A 2 The output register clock signal reg1_clk is simultaneously connected to the clock terminals of 16D flip-flops of the register reg1. For example, the output terminal Q0 of the counter CNT is connected with the D flip-flop DFF in the register Reg0 and the register Reg1 simultaneously 0_0 、DFF 1_0 D terminal of (c). The output end Q1 of the counter CNT is connected with the register Reg0 and the D trigger DFF in the register Reg1 0_1 、DFF 1_1 D terminal of (c). DFF connected in turn to D flip-flop 0_15 、DFF 1_15 . Logic control module A 2 The output register clock signal Reg0_CLK is simultaneously connected with the clock ends of 16D flip-flops of the register Reg0, and the logic control module A 2 Output register clock signalReg1_clk is connected to the clock terminals of the 16D flip-flops of register Reg1 at the same time. 2 of register Reg0 n The output of the D flip-flop and 2 of register Reg1 n The output ends of the D flip-flops form 2 of the interface circuit body n+1 And a plurality of output terminals.
The working principle of the invention is as follows:
as shown in fig. 1, the capacitance C is measured M Through a sensor oscillator OSC 1 Generating a period of T M Is a square wave signal of (a); t (T) M The signal passes through a programmable frequency divider A 1 After the frequency division process, generate 2 N+1 ·T M Is a square wave signal of (a); reference capacitor C R2 Through a low-precision oscillator OSC 2 Generating a period of T L Is a square wave signal of (a); reference capacitor C R3 Through a high-precision oscillator OSC 3 Generating a period of T H Is a square wave signal of (a).
As shown in fig. 2, the logic control module a 2 At 2 N+1 ·T M During the period that the signal is high level, the state 1 signal is set to be high level, and the rest time state 1 signal is set to be low level; logic control module A 2 At 2 N+1 ·T M Signal falling edge and 2 N+1 ·T M T after the signal falling edge L During the first rising edge of the signal, the state 2 signal is set high and the remaining time the state 2 signal is set low.
During the period of high level of the state 1 signal, T L Signal pair 2 N+1 ·T M The signal is measured, and the measurement result is stored by a register Reg 0; during the period of high level of the state 2 signal, T H Signal pair 2 N+1 ·T M The signal is measured and the measurement result is stored in a register Reg1.
When the state 1 signal is switched from low level to high level, the counter CNT is cleared once, and when the state 1 signal is at high level, the counter CNT is cleared once by T L Is to be tested 2 N+1 ·T M When the state 1 signal is converted from high level to low level, generating a clock signal reg0_clk of a register reg0, wherein the register reg0 stores the current value of the counter CNT; state 2 signal is composed ofWhen the low level is converted into the high level, the counter CNT is cleared once, and when the state 2 signal is the high level, the counter CNT is cleared by T H Is to be tested 2 N+1 ·T M When the state 2 signal is converted from high level to low level, a clock signal reg1_clk of a register reg1 is generated, and the register reg1 stores the current value of the counter CNT.
Since the low-precision, high-precision and sensor oscillator is an RC relaxation oscillator structure, the period T of the square wave output by the oscillator is:
T＝2·RC (1)
setting reference signal T generated by low-precision and high-precision oscillators L 、T H The integer ratio of the period of (2) is K (TL/TH) Representing a T L The signal period includes T H Number of complete cycles:
in equation (2), the ceil function may return a minimum integer greater than or equal to the expression, C R2 、C R3 And R is R OSC2 、R OSC3 The equivalent resistance and the external reference capacitance of the low-precision oscillator and the high-precision oscillator are respectively adopted.
The register Reg0 stores a value which is represented by the low precision reference signal T L Results of measurement:
in the formula (3), C M Is an externally connected measured capacitor R M Is the equivalent resistance of the sensor oscillator.
The register Reg1 stores the reference signal T with high precision H To measure therein by low precision reference signal T L A portion of less than one complete measurement cycle after the measurement;
the relation expression of the final measured capacitance and the reference capacitance is as follows:
the Cadence spectrum simulator is used for referencing the capacitor C at the power supply voltage of 1.4-1.8V and the temperature of 0-80 DEG C R2 、C R3 With 1pF, the capacitance C is measured M Simulation and verification were performed under conditions in the range of 1 to 10 pF.
Fig. 3 and 4 show graphs of the oscillator input capacitance versus output square wave period at a fixed temperature, different voltages and at a fixed voltage, respectively.
As shown by simulation results, the fluctuation of voltage and temperature can cause the output square wave period of the low-precision and high-precision oscillators to change to a certain extent, but the linearity of the oscillator is not affected. The oscillator is not easily influenced by external factors, and has good power supply voltage and temperature fluctuation suppression capability.
As shown in FIG. 5, under different temperature and voltage conditions, the capacitor C is externally connected R2 、C R3 All are 1pF, N is set to 3, namely the input binary signal is 0011, and the measured capacitance C M When the power consumption of the circuit is changed within the range of 1-10 pF, the power consumption of the circuit test is only 160.6uW, and the result D is output CM Linear relation with the measured capacitance; capacitance C to be measured M When the frequency is 3-4 pF, outputting a result D CM The relative error of (2) is only 1.25%, so that the measured capacitance C is selected by selecting an appropriate reference capacitance while the external input N remains unchanged M Is C R2 About 3-4 times, and can maximize the circuit detection precision.
The invention adopts the externally controlled programmable frequency divider to realize 1-2 16 Dividing frequency by any integer between them, and measuring capacitance C M The square wave T generated M Amplification 2 N+1 After doubling, the reference capacitor C is used R2 、C R3 The square wave T generated L 、T H The measurement can effectively improve the measurement accuracy. If the measured capacitance is about 5.2pF, the reference capacitance C R2 、C R3 All are standard 1pF, and the programmable frequency divider is set to 2 3 Frequency divisionThe measurement error is only 1.25%, and high-precision capacitance detection is realized. Under 180nm CMOS process standard, the software simulation result shows that under the condition of 1.8V power supply, the detectable capacitance range is between 1pF and 10pF, the highest detection precision can reach 0.15fF, and the power consumption is only 160.6uW.
The invention is suitable for weak capacitance detection during biomedical signal acquisition, and can realize external controllability of capacitance measurement precision through proper selection of the reference capacitance and control of the frequency division ratio of the programmable frequency divider so as to meet the application requirements of the biomedical field on low error, high precision and low power consumption of capacitance detection.
It should be noted that, although the examples described above are illustrative, this is not a limitation of the present invention, and thus the present invention is not limited to the above-described specific embodiments. Other embodiments, which are apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein, are considered to be within the scope of the invention as claimed.

Claims (3)

1. The digital output two-stage double-precision biomedical capacitance sensor interface circuit comprises an interface circuit body and is characterized in that the interface circuit body consists of a capacitance time conversion circuit and a time digital conversion circuit;
the capacitance time conversion circuit comprises a reference capacitance C R2 Reference capacitance C R3 Sensor oscillator OSC 1 Low precision oscillator OSC 2 And a high precision oscillator OSC 3 The method comprises the steps of carrying out a first treatment on the surface of the Sensor oscillator OSC 1 The input end of the interface circuit body is formed and connected with the external tested capacitor C M Connecting; reference capacitor C R2 And reference capacitance C R3 Respectively connected with low-precision oscillators OSC 2 And a high precision oscillator OSC 3 Is provided; sensor oscillator OSC 1 The generated output signal T M To programmable frequency divider A 1 Is provided; low precision oscillator OSC 2 The generated output signal T L And a high precision oscillator OSC 3 The generated output signal T H Respectively send to logicControl module A 2 2 inputs of (a);
the time-to-digital conversion circuit comprises a programmable frequency divider A 1 Logic control module A 2 A counter CNT, a register Reg0 and a register Reg1; the externally input N-bit binary frequency division value N is sent to the programmable frequency divider A 1 Programmable frequency divider a 1 For output signal T M Signal go 2 N+1 After frequency division processing, the frequency division processing is sent to a logic control module A 2 Is provided; the counter CNT comprises 1 clock terminal and 2 n Each output end, logic control module A 2 The output counting clock signal CLK is sent to the clock end of the counter CNT; register Reg0 and register Reg1 are both 2 n The D flip-flops are composed, 1D flip-flop of the register Reg0 corresponds to 1D flip-flop of the register Reg1, and the D ends of the 2D flip-flops are simultaneously connected with one output end of the counter CNT; logic control module A 2 The output register clock signal Reg0_CLK is simultaneously coupled to 2 of register Reg0 n Clock end of D trigger, logic control module A 2 The output register clock signal Reg1_CLK is simultaneously connected to 2 of register Reg1 n Clock ends of the D triggers; 2 of register Reg0 n The output of the D flip-flop and 2 of register Reg1 n The output ends of the D flip-flops form 2 of the interface circuit body n+1 And a plurality of output terminals.
2. The digital output two-stage double-precision biomedical capacitance sensor interface circuit according to claim 1, wherein n has a value ranging from 2 to 5.
3. A digital output two-stage dual precision biomedical capacitive sensor interface circuit as claimed in claim 2, wherein n=4.
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CN104485938A (en) * 2015-01-13 2015-04-01 合肥工业大学 Low-power-consumption capacitance type sensor interface circuit
CN209201054U (en) * 2019-01-24 2019-08-02 桂林电子科技大学 A kind of numeral output two-stage double precision biomedicine capacitance sensor interface circuit

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