CN113411085B - Successive approximation type capacitance detection circuit - Google Patents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
Abstract
The invention discloses a successive approximation type capacitance detection circuit which comprises a step counter module, wherein an upper counter and a lower counter respectively receive voltage to be detected and an inversion value of the voltage to be detected, and a four-bit digital code is output in a successive approximation mode to control a current switch array. The current array is coupled with the four-bit output of the asynchronous counter and charges the boosting resistor to output a voltage value after successive approximation. The comparison module is used for receiving the charging voltage from the capacitor to be tested by the comparator and comparing the charging voltage with the output of the current switch array, and outputting the charging voltage as a selection signal of a next counter for comparison again to achieve the purpose of successive approximation; the adoption of the open loop comparator can enhance the overall operation speed and effectively improve the gain.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a successive approximation type capacitance detection circuit.
Background
With the development of computer technology, multimedia technology, signal processing technology and microelectronics technology, the popularity of IC chips is increasing, which promotes the IC chips to have great changes in process, structure, performance and reliability requirements, and to develop toward high speed, low power consumption, small volume and on-chip integration.
In the aspect of analog design, the detection of capacitance is an important part, and once the matching condition of the input capacitance is insufficient, huge errors can be caused to the whole function, and even the service life of the chip is influenced.
The traditional capacitor size detection circuit mainly adopts an analog-to-digital converter ADC, and firstly, a capacitor to be detected is converted into physical quantities such as voltage, frequency or time through a AFE (Analog Front End) architecture, for example, a charge amplifier structure. The input capacitance variation is then converted to a digital signal output by ADC (Analog to Digital Converter), mainly a SAR ADC (successive approximation analog-to-digital converter), or a TDC architecture. The circuit is complex, different reference voltages are needed to be provided, and complex time sequence signal control logic is needed, so that the influence of external environment interference (temperature change and humidity change) on parasitic capacitance is high, and the reliability is low.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a successive approximation type capacitance detection circuit.
In order to achieve the aim of the invention, the invention adopts the following technical scheme:
a successive approximation type capacitance detection circuit comprises a comparison selection module, a step counter module, a current array module and a sampling switch;
one input end of the comparison selection module is connected with a charging current source and is grounded through a capacitor to be tested, and the other input end of the comparison selection module is connected with the output end of the current array module;
the input end of the step counter module is connected with the output end of the comparison selection module;
the input end of the current array module is connected with the output end of the step counting module, and the output end of the current array module is used as the output of the successive approximation type capacitance detection circuit after passing through the sampling switch;
the sampling switch is also grounded through a sampling capacitor.
The counter used by the output stage has the advantages of simple structure, high efficiency and high speed, and is quicker than the successive approximation voltage of the SAR ADC; the range of the capacitor to be measured is higher, the mode setting is simple, and the needed time sequence signal control logic is simple and efficient; the structure is simple and convenient to upgrade, and the whole test circuit can be obviously improved through the improvement of the number of bits of the counter or the improvement of the performance of the comparator; the integral comparison circuit is started only when the capacitor is charged, so that the integral comparison circuit is shut down when the system is in an overvoltage state, and power consumption is reduced.
Further, the comparison selection module comprises a comparator, a counter D6, NAND gates NAND1, NAND2, NAND3, NAND4 and NAND5, and NOR gates NOR15 and NOR16, wherein the input end of the comparator is respectively connected with the output of the successive approximation type capacitance detection circuit and a charging current source, and the output end of the comparator is connected with the D end of the counter D6; the CLK of the counter D6 is accessed to a clock signal, and the Q end is sequentially output to the step counter module through the NAND gate NAND1 and the NAND gate NAND2 and is sequentially output to the step counter module through the NOR gate NOR15, the NAND gate NAND4 and the NAND gate NAND 5; the input end of the NAND gate NAND3 is respectively connected with a reset signal of the step counter, and the output end of the NAND gate NAND3 is connected with one input end of the NOR gate NOR16 and is respectively output to the other input ends of the NAND gate NAND2 and the NAND gate NAND5 through the NOR gate NOR 16; the other input of NAND gate NAND1 is connected to a clock signal, the other input of NOR gate NOR15, and the other input of NOR gate NOR16 is connected to ground.
The beneficial effects of the above-mentioned further scheme are: the comparison selection module uses a simple D trigger to store the level, the opening of each counter is controlled by the output of the comparator and the RESET signal of the counter, and a series of gates are used for controlling the selection of the counter AB. The feedback structure is simple and the speed is high, so that the transmission delay is effectively reduced.
Further, the comparator adopts a two-stage open-loop comparator.
The beneficial effects of the above-mentioned further scheme are: the amplifier circuit formed by cascade connection of the two-stage amplifiers working in an open loop mode overcomes the defect of insufficient gain and bandwidth, and meanwhile, the amplifier circuit has the advantages of small offset voltage, higher precision and higher speed for the whole comparator structure.
Further, the step counter module comprises a first step counter and a second step counter, the first step counter comprises rising edge triggers D1, D2, D3, D4 and D5, NOR gates NOR1, NOR2, NOR3, NOR4, NOR5, NOR6, NOR7, NOR8, NOR9, NOR10, NOR11, NOR12, NOR13 and NOR14, exclusive OR gates XOR1, XOR2, XOR3 and XOR4, wherein D ends and Q non-ends of the rising edge triggers D1, D2, D3, D4 and D5 are short-circuited to form an asynchronous counter; one input end of the NOR gate NOR1 is connected to the output end of the NAND gate NAND2 in the comparison and selection module, the other input end of the NOR gate NOR1 is grounded, and the output end of the NOR gate NOR1 is connected with the CLK end of the rising edge trigger D1; the Q end of the rising edge trigger D1 is output to one input end of the NOR gate NOR2 and is sequentially output to the current array module through NOR gates NOR13 and NOR14 and the exclusive OR gate XOR 1; the output end of the NOR gate NOR2 is connected with the CLK end of the rising edge trigger D2; the Q end of the rising edge trigger D2 is output to one input end of the NOR gate NOR3 and sequentially output to the current array module through NOR gates NOR11 and NOR12 and an exclusive OR gate XOR 2; the output end of the NOR gate NOR3 is connected with the CLK end of the rising edge trigger D3; the Q end of the rising edge trigger D3 is output to one input end of the NOR gate NOR4 and sequentially output to the current array module through NOR gates NOR9 and NOR10 and the exclusive OR gate XOR 3; the output end of the NOR gate NOR4 is connected with the CLK end of the rising edge trigger D4; the Q end of the rising edge trigger D4 is output to one input end of the NOR gate NOR5 and sequentially output to the current array module through NOR gates NOR7 and NOR8 and the exclusive OR gate XOR 4; the output end of the NOR gate NOR5 is connected to the CLK end of the rising edge trigger D5, the Q end of the rising edge trigger D5 is output to one input end of the NOR gate NOR6, and the reset signal of the step counter of the NOR gate NOR6 is output to one input end of the NAND gate NAND3 and to the other input ends of the exclusive or gates XOR1, XOR2, XOR3 and XOR 4; the other input ends of the NOR gates NOR1 to NOR14 are grounded; the second step counter has the same structure as the first step counter. The outputs of the exclusive or gates XOR1, XOR2, XOR3, and XOR4 output a four-bit binary code as the output of the first ladder counter.
The beneficial effects of the above-mentioned further scheme are: the step counter structure adds limitation to each counting cycle in a state identification mode, so that the jump from the counting to the limit value can be avoided, the jump of the output current and the output voltage value is further avoided, and the error is greatly reduced.
Further, the current array module comprises a first current array, a second current array, a power ICC and a charging resistor Rc, wherein the input end of the first current array is connected with the output end of the first step counter, and the input end of the second current array is connected with the output end of the second step counter; the first current array module comprises current sources I1, I2, I3 and I4, current limiting diodes Dio1, dio2, dio3 and Dio4, and switches SW1, SW2, SW3 and SW4; the second current array module comprises current sources I5, I6, I7 and I8, current limiting diodes Dio5, dio6, dio7 and Dio8, and switches SW5, SW6, SW7 and SW8, wherein the current source I1 and the current limiting diode Dio1 are connected in parallel, one end of a parallel structure formed by the current source I1 and the current limiting diode Dio1 is connected with a high level of a system, and the other end of the parallel structure formed by the current source I1 and the current limiting diode Dio1 is grounded through the switch SW1, the switch SW5 and a parallel structure formed by the current source I5 and the current limiting diode Dio5 in sequence; the current source I2 and the current-limiting diode Dio2 are connected in parallel, the current source I6 and the current-limiting diode Dio6 are connected in parallel, one end of a parallel structure formed by the current source I2 and the current-limiting diode Dio2 is connected with a system high level, and the other end of the parallel structure formed by the current source I2 and the current-limiting diode Dio6 is grounded through a switch SW2 and a switch SW6 in sequence; the current source I3 and the current-limiting diode Dio3 are connected in parallel, the current source I7 and the current-limiting diode Dio7 are connected in parallel, one end of a parallel structure formed by the current source I3 and the current-limiting diode Dio3 is connected with a system high level, and the other end of the parallel structure formed by the current source I3 and the current-limiting diode Dio7 is grounded through a switch SW3 and a switch SW7 in sequence; the current source I4 and the current-limiting diode Dio4 are connected in parallel, the current source I8 and the current-limiting diode Dio8 are connected in parallel, one end of a parallel structure formed by the current source I4 and the current-limiting diode Dio4 is connected with a system high level, and the other end of the parallel structure formed by the current source I4 and the current-limiting diode Dio8 is grounded through a switch SW4 and a switch SW8 in sequence; the four-bit binary codes output by the first step counter are respectively output to the switches SW1, SW2, SW3 and SW4; the four-bit binary codes output by the second step counter are respectively output to switches SW5, SW6, SW7 and SW8; one end of the power ICC is connected to the system power end, and the other end of the power ICC is grounded through a charging resistor Rc.
The beneficial effects of the above-mentioned further scheme are: the current array is simple in structure, the current sources are not mutually influenced, the current array is controlled only by the output four-bit binary code of the counter, the interference possibility is reduced, and the accuracy of the current in charging is improved.
Further, when the binary codes received by the switches SW1 to SW8 are 1, the corresponding switches are turned off; when the received binary code is 0, the corresponding switch is turned on and charges the charging resistor Rc.
The beneficial effects of the above-mentioned further scheme are: only half of the current array is awakened by the corresponding switch, and the switch which is not charged and the current source are in an off state, so that the power consumption of the whole switch array is reduced.
Further, the midpoints of the switches SW1 and SW5, the midpoints of the switches SW2 and S6, the midpoints of the switches SW3 and SW7, the midpoints of the switches SW4 and SW8, and the midpoint of the power ICC and the charging resistor Rc are shorted as the output of the current array module. The ratio of the current values of the current sources I1, I2, I3 and I3 to the ratio of the current sources I5, I6, I7 and I8 are all 1:2:4:8.
the beneficial effects of the above-mentioned further scheme are: the output is determined by the intermediate values of the upper array and the lower array, the size of the charging current source corresponds to the binary code bit number, the output result is directly connected with the output result of the comparator, the result is more accurate, and the accuracy of successive approximation can be improved.
Drawings
Fig. 1 is a schematic diagram of a successive approximation type capacitance detection circuit according to the present invention.
Fig. 2 is a schematic diagram of a ladder counter circuit according to an embodiment of the invention.
FIG. 3 is a schematic diagram of a current array according to an embodiment of the invention.
FIG. 4 is a schematic diagram of a comparison selection module according to an embodiment of the invention.
Fig. 5 is a schematic diagram of a comparator circuit according to an embodiment of the invention.
FIG. 6 is a simulation graph of the capacitance detection input voltage and the output voltage according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and all the inventions which make use of the inventive concept are protected by the spirit and scope of the present invention as defined and defined in the appended claims to those skilled in the art.
A successive approximation type capacitance detection circuit, as shown in figure 1, comprises a comparison selection module, a step counter module, a current array module and a sampling switch;
one input end of the comparison selection module is connected with a charging current source and is grounded through a capacitor to be tested, and the other input end of the comparison selection module is connected with the output end of the current array module;
the input end of the step counter module is connected with the output end of the comparison selection module;
the input end of the current array module is connected with the output end of the step counting module, and the output end of the current array module is used as the output of the successive approximation type capacitance detection circuit after passing through the sampling switch;
the sampling switch is also grounded through a sampling capacitor.
Specifically, as shown in fig. 4, the comparison selection module includes a comparator, a counter D6, NAND gates NAND1, NAND2, NAND3, NAND4, NAND5, NOR gates NOR15, NOR16, wherein an input end of the comparator is connected to an output of the successive approximation type capacitance detection circuit and a charging current source, and an output end of the comparator is connected to a D end of the counter D6; the CLK of the counter D6 is accessed to a clock signal, and the Q end is sequentially output to the step counter module through the NAND gate NAND1 and the NAND gate NAND2 and is sequentially output to the step counter module through the NOR gate NOR15, the NAND gate NAND4 and the NAND gate NAND 5; the input end of the NAND gate NAND3 is respectively connected with a reset signal of the step counter, and the output end of the NAND gate NAND3 is connected with one input end of the NOR gate NOR16 and is respectively output to the other input ends of the NAND gate NAND2 and the NAND gate NAND5 through the NOR gate NOR 16; the other input of NAND gate NAND1 is connected to a clock signal, the other input of NOR gate NOR15, and the other input of NOR gate NOR16 is connected to ground.
In this embodiment, the comparison control module is mainly divided into two parts, one is a key-comparator of the successive approximation circuit, and the purpose of measuring the voltage is achieved by multiple comparisons. In the embodiment of the invention, a two-stage open-loop comparator is adopted, and the specific structure of the two-stage open-loop comparator is shown in fig. 5.
The comparator adopted by the embodiment of the invention is based on the SMIC0.13 technology, and the specific parameter requirements are as follows: the power supply voltage is 3V and 5V, the gain is larger than 50dB, the unit gain bandwidth is larger than 50MHz, the transmission delay is smaller than 100ns, and the power supply voltage is 2.8V-5.2V. When the power supply voltage is 5V, the output high level is more than 4.5V, the output low level is less than 1V, and the input range is as follows: 1V-4.5V, load capacitance of 1pF, slew rate of more than 1000V/us and power consumption of less than 1mW.
In order to obtain a larger common-mode input range, a folded cascode differential amplifier is used as an input stage of the comparator, and a common-source amplifier is used as an output amplifier stage. The amplifier circuit formed by cascade connection of the two-stage amplifiers working in an open loop mode overcomes the defect of insufficient gain and bandwidth, and simultaneously has the advantages of small offset voltage, higher precision and higher speed for the integral comparator mechanism. In the figure, M1 and M2 are differential input ends, and M6 and M8 form a cascode current mirror to serve as a load.
In small signal analysis, all MOS tubes in the comparator are kept in a saturation region to be used as a basis for determining a common mode input range. According to the circuit configuration in the figure, the common-mode input range of the comparator can be expressed as:
V in max ＝VDD-V SD7 +V THN
the common mode input range of the differential amplifier relative to the common current mirror load is as follows:
V in max ＝VDD-V GS3 +V THN
V inmin ＝V GS1 +V DS5
VGS is typically much larger than VDS, and therefore the common mode input range is increased.
The embodiment of the invention adopts the structure of the comparator to simplify the folding cascode structure. Because the gain requirement is not high, the drain terminal voltage of M3 can be used as the bias of M6-M9, NMOS corresponding to M6-M9 is simplified into current mirrors M3 and M4, bias is provided by VREF, two bias circuits are saved under the condition of compromising a part of gain, and the whole area is reduced. In small signals, the transmission delay of the comparator is mainly determined by the input voltage and the minimum resolution voltage, and when the input voltage is gradually increased, the comparator enters a large signal state, the transmission delay depends on the co-location of the output stages of the comparator or the capability of sucking out current, and the total small signal gain is the product of the gains of the two stages of amplifiers.
The integral comparator structure is responsible for comparing the charging voltage of the capacitor to be detected with the conversion voltage after successive approximation of the counters, and outputting high and low levels to control selection of the positive and negative AB counters in the next round. If the voltage is too low, the comparator outputs 1, the counter A works to charge the upper part of the current array, and the current on the charging resistor is increased. When the voltage is too high, the comparator outputs 0, the counter B works to charge the lower part of the current array, and the current on the charging resistor is reduced. So as to reach Vout to approach the voltage Vc to be measured again.
Wherein the comparator output is connected to a D flip-flop (D6) which is used to achieve the function of saving the level value.
In the embodiment of the invention, the starting of each counter is controlled by the output of the comparator and the RESET signal of the counter, and a series of gates are used for controlling the selection of the counter AB.
As shown in fig. 4, the specific working principle is as follows:
the high-low level output by the comparator and the clock signal are first passed through the NAND gate NAND1, taking the example that the charging voltage is higher than the conversion voltage after the successive approximation of the counter:
according to the working principle of the NAND gate:
Y＝(A·B)'＝A'+B'
when the conversion voltage after successive approximation of the counter is lower, the high level output by the comparator can only pass when the CLK signal is high, and the output level passes through the NAND gate NAND2. Meanwhile, the RESET signal output by the up-down counter passes through a NAND gate NAND3, and since the up-down counter only has one operation at the same time, when the counter finishes one cycle, the reset_a and the reset_b must have one 1 and the other 0, and the NAND gate NAND3 output must have 1. The value ratio outputted by the inverter INV1 is 0, and is connected to the NAND2. Therefore, when the comparator output is 0 or the counter a output RESET signal is 1, the Count pulse (count_a) is 1, and the upper counter a starts to operate, compensating for the lower switching voltage.
The charging voltage is lower than the conversion voltage after the successive approximation of the counter, and the NAND4 and the NAND5 act on the NAND1 and the NAND2 are the same. However, since the charging voltage is lower than 1 output from the switching voltage comparator after successive approximation of the counter, it is necessary to switch it to a low level by the inverter INV 2. And then the counter B is started through the NAND4 and the NAND5, so that the aim of reducing the conversion voltage after successive approximation is finally fulfilled.
As shown in fig. 2, the step counter module includes a first step counter and a second step counter, the first step counter includes rising edge flip-flops D1, D2, D3, D4, and D5, NOR gates NOR1, NOR2, NOR3, NOR4, NOR5, NOR6, NOR7, NOR8, NOR9, NOR10, NOR11, NOR12, NOR13, and NOR14, exclusive or gates XOR1, XOR2, XOR3, and XOR4, wherein D and Q non-ends of the rising edge flip-flops D1, D2, D3, D4, and D5 are shorted to form an asynchronous counter; one input end of the NOR gate NOR1 is connected to the output end of the NAND gate NAND2 in the comparison and selection module, the other input end of the NOR gate NOR1 is grounded, and the output end of the NOR gate NOR1 is connected with the CLK end of the rising edge trigger D1; the Q end of the rising edge trigger D1 is output to one input end of the NOR gate NOR2 and is sequentially output to the current array module through NOR gates NOR13 and NOR14 and the exclusive OR gate XOR 1; the output end of the NOR gate NOR2 is connected with the CLK end of the rising edge trigger D2; the Q end of the rising edge trigger D2 is output to one input end of the NOR gate NOR3 and sequentially output to the current array module through NOR gates NOR11 and NOR12 and an exclusive OR gate XOR 2; the output end of the NOR gate NOR3 is connected with the CLK end of the rising edge trigger D3; the Q end of the rising edge trigger D3 is output to one input end of the NOR gate NOR4 and sequentially output to the current array module through NOR gates NOR9 and NOR10 and the exclusive OR gate XOR 3; the output end of the NOR gate NOR4 is connected with the CLK end of the rising edge trigger D4; the Q end of the rising edge trigger D4 is output to one input end of the NOR gate NOR5 and sequentially output to the current array module through NOR gates NOR7 and NOR8 and the exclusive OR gate XOR 4; the output end of the NOR gate NOR5 is connected to the CLK end of the rising edge trigger D5, the Q end of the rising edge trigger D5 is output to one input end of the NOR gate NOR6, and the reset signal of the step counter of the NOR gate NOR6 is output to one input end of the NAND gate NAND3 and to the other input ends of the exclusive or gates XOR1, XOR2, XOR3 and XOR 4; the other input ends of the NOR gates NOR1 to NOR14 are grounded; the second step counter has the same structure as the first step counter.
In this embodiment, the output terminals of the exclusive or gates XOR1, XOR2, XOR3, and XOR4 output the four-bit binary code as the output terminal of the first ladder counter.
The asynchronous counter principle is as follows:
the inputs of the edge D flip-flops triggered by the four rising edges are all connected to Q non-forming asynchronous counters, so each D flip-flop also forms a divide-by-two, while the four flip-flops are connected, also forming a modulo-16 counter. The output of the counter is decremented down in sequence every time a clock falling edge passes. When the 16 th clock falling edge is reached, the output of the counter is decremented to the last count state 0000 and then ready for the next cycle, so that a down counter is formed of 4 edge D flip-flops.
In the ladder counter provided by the embodiment of the invention, 4 rising edge triggered edge D triggers (D1, D2, D3 and D4) are adopted, so that a modulo-16 counter of 1111 to 0000 is formed. In contrast, as shown in fig. 2, an inverter (NOR 1, NOR2, NOR3, NOR 4) is connected to the clock terminal of each D flip-flop input, and then turns into an addition counter of 0000 to 1111. The inverter is composed of one end of a NOR gate circuit and ground.
Except for the input inverters, the remaining inverters are used to increase the driving capability so that the signal has good rising and falling edges, and so that the resistance is optimized in terms of the power consumption delay product when the required driving capability is obtained, wherein the latter inverter is twice as large as the former one, for example, the NOR14 is twice as large as the NOR 13.
When each round of counting process reaches 1111, an inverter and a D trigger (D5) are adopted to record the inversion value 0 of the bit value 1 of the counter at the moment, the output of the trigger is connected to one end of the exclusive-OR gate, and the other end of the trigger is connected to the output of each bit. According to the logical expression of the exclusive or gate:
the next round of output of 1111 is output after exclusive-or operation with 0, which is 1111. At this point 1111 acts as the end of each counting cycle, and then the counter operation no longer affects the current array switches, the specific principles being described by the comparison control module in the following section.
Further, the current array module comprises a first current array, a second current array, a power ICC and a charging resistor Rc, wherein the input end of the first current array is connected with the output end of the first step counter, and the input end of the second current array is connected with the output end of the second step counter; the first current array module comprises current sources I1, I2, I3 and I4, current limiting diodes Dio1, dio2, dio3 and Dio4, and switches SW1, SW2, SW3 and SW4; the second current array module comprises current sources I5, I6, I7 and I8, current limiting diodes Dio5, dio6, dio7 and Dio8, and switches SW5, SW6, SW7 and SW8, wherein the current source I1 and the current limiting diode Dio1 are connected in parallel, one end of a parallel structure formed by the current source I1 and the current limiting diode Dio1 is connected with a high level of a system, and the other end of the parallel structure formed by the current source I1 and the current limiting diode Dio1 is grounded through the switch SW1, the switch SW5 and a parallel structure formed by the current source I5 and the current limiting diode Dio5 in sequence; the current source I2 and the current-limiting diode Dio2 are connected in parallel, the current source I6 and the current-limiting diode Dio6 are connected in parallel, one end of a parallel structure formed by the current source I2 and the current-limiting diode Dio2 is connected with a system high level, and the other end of the parallel structure formed by the current source I2 and the current-limiting diode Dio6 is grounded through a switch SW2 and a switch SW6 in sequence; the current source I3 and the current-limiting diode Dio3 are connected in parallel, the current source I7 and the current-limiting diode Dio7 are connected in parallel, one end of a parallel structure formed by the current source I3 and the current-limiting diode Dio3 is connected with a system high level, and the other end of the parallel structure formed by the current source I3 and the current-limiting diode Dio7 is grounded through a switch SW3 and a switch SW7 in sequence; the current source I4 and the current-limiting diode Dio4 are connected in parallel, the current source I8 and the current-limiting diode Dio8 are connected in parallel, one end of a parallel structure formed by the current source I4 and the current-limiting diode Dio4 is connected with a system high level, and the other end of the parallel structure formed by the current source I4 and the current-limiting diode Dio8 is grounded through a switch SW4 and a switch SW8 in sequence; the four-bit binary codes output by the first step counter are respectively output to the switches SW1, SW2, SW3 and SW4; the four-bit binary codes output by the second step counter are respectively output to switches SW5, SW6, SW7 and SW8; one end of the power ICC is connected to the system power end, and the other end of the power ICC is grounded through a charging resistor Rc.
When the binary codes received by the switches SW1 to SW8 are 1, the corresponding switches are turned off; when the received binary code is 0, the corresponding switch is turned on and charges the charging resistor Rc.
The midpoints of the switches SW1 and SW5, the midpoints of the switches SW2 and S6, the midpoints of the switches SW3 and SW7, the midpoints of the switches SW4 and SW8, and the midpoint of the power ICC and the charging resistor Rc are shorted as the outputs of the current array module.
The ratio of the current values of the current sources I1, I2, I3 and I3 to the ratio of the current sources I5, I6, I7 and I8 are all 1:2:4:8.
in this embodiment, the current array is composed of upper and lower switch current source groups, as shown in fig. 3, only the upper half or the lower half works in each successive approximation voltage process, and the two groups are respectively connected with the counter by the front end control. The two counters respectively measure the voltage to be compared and the opposite phase value, and each switch current source group is provided with four switches and four current sources. Wherein, current source I1: i2: and I3: the ratio of I4 is 1:2:4:8 (the ratio of I5, I6, I7 and I8 is the same), the charge and discharge of the current source is controlled by the corresponding switch Sw corresponding to the output Q1, Q2, Q3 and Q4 of the asynchronous counter, the charging resistor is charged by the upper current group and the lower current group to form an output voltage, and the diode (Dio 1-8) only has a limiting function, namely only uses the current source for charging. The power ICC is set to be the intermediate value of the upper current array and the lower current array, namely, the value of the charging resistor flowing when the current arrays do not work is guaranteed to be the same as I1.
In the embodiment of the invention, the output of the counter A or B is a four-bit binary code, and when 1 is received, the switch is turned off and the resistor is not charged; when a 0 is received, the switch is turned on, charging the resistor, generating the voltage Vout to form a measurement of the magnitude of the input voltage.
Overall, according to the capacitance charging formula:
where it=q represents the charge amount of the whole capacitor, and U represents the voltage between the capacitors. When the charging current I and the charging time T are fixed, the charging voltage between the capacitors is measured, and the capacitor size can be deduced through a formula.
In the embodiment of the invention, the charging capacitor is charged by the charging current source Iref, so that the charging current Iref is fixed.
The charging time T is set by the clock signal CLK, and the whole circuit is started only when CLK is high. Meanwhile, when CLK is high, the counter module starts to operate, and the charging time T is set to half period T/2 of the clock signal CLK.
Finally, the charging voltage of the capacitor is tested by a successive approximation circuit, the current array under the control of the counter charges the charging resistor (Rc) to simulate the charging voltage u=vout of the capacitor, and it should be noted that the charging time and the charging current of the capacitor need to be kept appropriate to prevent the ineffective charging time after the capacitor is fully pressed.
As shown in fig. 6, vout approximates Vc in each charging of the current array by the counter operation, the size of the two determines the next counter a or B, and after multiple approximations, the final Vout approaches Vc until the error between the two is smaller than the input range of the comparator.
In the embodiment of the invention, the charging current source Iref is set to 2uA, the clock period is 2uS, and Vout is measured to be 1.8V. Then according to the capacitance charge formula:
C＝(2uA*1us)/1.8V＝1.1pf
the whole capacitance measurement precision is determined by the counter bit number, the measurement range is determined by the capacitance charging time length and the charging current source size, and the measurement voltage is between 1V and 4.5V of the input range of the comparator. Therefore, the whole measuring circuit is simple and convenient to upgrade, the superposition of counter digits can bring about improvement of precision, the charging time and the charging current can bring about promotion of range, and the power consumption increase brought by circuit upgrade is very weak and belongs to the fully controllable range.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The principles and embodiments of the present invention have been described in detail with reference to specific examples, which are provided to facilitate understanding of the method and core ideas of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Those of ordinary skill in the art will recognize that the embodiments described herein are for the purpose of aiding the reader in understanding the principles of the present invention and should be understood that the scope of the invention is not limited to such specific statements and embodiments. Those of ordinary skill in the art can make various other specific modifications and combinations from the teachings of the present disclosure without departing from the spirit thereof, and such modifications and combinations remain within the scope of the present disclosure.
Claims (8)
1. The successive approximation type capacitance detection circuit is characterized by comprising a comparison selection module, a step counter module, a current array module and a sampling switch;
one input end of the comparison selection module is connected with a charging current source and is grounded through a capacitor to be tested, and the other input end of the comparison selection module is connected with the output end of the current array module;
the input end of the step counter module is connected with the output end of the comparison selection module, specifically, the step counter module comprises a first step counter and a second step counter, the first step counter comprises rising edge triggers D1, D2, D3, D4 and D5, NOR gates NOR1, NOR2, NOR3, NOR4, NOR5, NOR6, NOR7, NOR8, NOR9, NOR10, NOR11, NOR12, NOR13 and NOR14, and exclusive OR gates XOR1, XOR2, XOR3 and XOR4, wherein the D ends and Q non-ends of the rising edge triggers D1, D2, D3, D4 and D5 are short-circuited to form an asynchronous counter; one input end of the NOR gate NOR1 is connected into the comparison selection module, the other input end of the NOR gate NOR1 is grounded, and the output end of the NOR gate NOR1 is connected with the CLK end of the rising edge trigger D1; the Q end of the rising edge trigger D1 is output to one input end of the NOR gate NOR2 and is sequentially output to the current array module through NOR gates NOR13 and NOR14 and the exclusive OR gate XOR 1; the output end of the NOR gate NOR2 is connected with the CLK end of the rising edge trigger D2; the Q end of the rising edge trigger D2 is output to one input end of the NOR gate NOR3 and sequentially output to the current array module through NOR gates NOR11 and NOR12 and an exclusive OR gate XOR 2; the output end of the NOR gate NOR3 is connected with the CLK end of the rising edge trigger D3; the Q end of the rising edge trigger D3 is output to one input end of the NOR gate NOR4 and sequentially output to the current array module through NOR gates NOR9 and NOR10 and the exclusive OR gate XOR 3; the output end of the NOR gate NOR4 is connected with the CLK end of the rising edge trigger D4; the Q end of the rising edge trigger D4 is output to one input end of the NOR gate NOR5 and sequentially output to the current array module through NOR gates NOR7 and NOR8 and the exclusive OR gate XOR 4; the output end of the NOR gate NOR5 is connected to the CLK end of the rising edge trigger D5, the Q end of the rising edge trigger D5 is output to one input end of the NOR gate NOR6, and the reset signal of the step counter of the NOR gate NOR6 is output to the comparison selection module and the other input ends of the exclusive or gates XOR1, XOR2, XOR3 and XOR 4; the other input ends of the NOR gates NOR1 to NOR14 are grounded; the second step counter has the same structure as the first step counter;
the input end of the current array module is connected with the output end of the step counting module, and the output end of the current array module is used as the output of the successive approximation type capacitance detection circuit after passing through the sampling switch;
the sampling switch is also grounded through a sampling capacitor.
2. The successive approximation type capacitance detection circuit according to claim 1, wherein the comparison selection module comprises a comparator, a counter D6, NAND gates NAND1, NAND2, NAND3, NAND4 and NAND5, NOR gates NOR15 and NOR16, wherein an input end of the comparator is connected to an output of the successive approximation type capacitance detection circuit and a charging current source, respectively, and an output end of the comparator is connected to a D end of the counter D6; the CLK of the counter D6 is accessed to a clock signal, and the Q end is sequentially output to the step counter module through the NAND gate NAND1 and the NAND gate NAND2 and is sequentially output to the step counter module through the NOR gate NOR15, the NAND gate NAND4 and the NAND gate NAND 5; the input end of the NAND gate NAND3 is respectively connected with a reset signal of the step counter, and the output end of the NAND gate NAND3 is connected with one input end of the NOR gate NOR16 and is respectively output to the other input ends of the NAND gate NAND2 and the NAND gate NAND5 through the NOR gate NOR 16; the other input of NAND gate NAND1 is connected to a clock signal, the other input of NOR gate NOR15, and the other input of NOR gate NOR16 is connected to ground.
3. The successive approximation type capacitance detection circuit according to claim 2, wherein the comparator employs a two-stage open loop comparator.
4. The successive approximation type capacitance detection circuit according to claim 1, wherein the output terminals of the exclusive or gates XOR1, XOR2, XOR3, and XOR4 output a four-bit binary code as the output terminal of the first step counter.
5. The successive approximation type capacitance detection circuit according to claim 4, wherein the current array module comprises a first current array, a second current array, a power source ICC and a charging resistor Rc, an input end of the first current array is connected with an output end of a first step counter, and an input end of the second current array is connected with an output end of a second step counter; the first current array module comprises current sources I1, I2, I3 and I4, current limiting diodes Dio1, dio2, dio3 and Dio4, and switches SW1, SW2, SW3 and SW4; the second current array module comprises current sources I5, I6, I7 and I8, current limiting diodes Dio5, dio6, dio7 and Dio8, and switches SW5, SW6, SW7 and SW8, wherein the current source I1 and the current limiting diode Dio1 are connected in parallel, one end of a parallel structure formed by the current source I1 and the current limiting diode Dio1 is connected with a high level of a system, and the other end of the parallel structure formed by the current source I1 and the current limiting diode Dio1 is grounded through the switch SW1, the switch SW5 and a parallel structure formed by the current source I5 and the current limiting diode Dio5 in sequence; the current source I2 and the current-limiting diode Dio2 are connected in parallel, the current source I6 and the current-limiting diode Dio6 are connected in parallel, one end of a parallel structure formed by the current source I2 and the current-limiting diode Dio2 is connected with a system high level, and the other end of the parallel structure formed by the current source I2 and the current-limiting diode Dio6 is grounded through a switch SW2, a switch SW6 and a parallel structure formed by the current source I6 and the current-limiting diode Dio6 in sequence; the current source I3 and the current-limiting diode Dio3 are connected in parallel, the current source I7 and the current-limiting diode Dio7 are connected in parallel, one end of a parallel structure formed by the current source I3 and the current-limiting diode Dio3 is connected with a system high level, and the other end of the parallel structure formed by the current source I3 and the current-limiting diode Dio7 is grounded through a switch SW3 and a switch SW7 in sequence; the current source I4 and the current-limiting diode Dio4 are connected in parallel, the current source I8 and the current-limiting diode Dio8 are connected in parallel, one end of a parallel structure formed by the current source I4 and the current-limiting diode Dio4 is connected with a system high level, and the other end of the parallel structure formed by the current source I4 and the current-limiting diode Dio8 is grounded through a switch SW4 and a switch SW8 in sequence; the four-bit binary codes output by the first step counter are respectively output to the switches SW1, SW2, SW3 and SW4; the four-bit binary codes output by the second step counter are respectively output to switches SW5, SW6, SW7 and SW8; one end of the power ICC is connected to the system power end, and the other end of the power ICC is grounded through a charging resistor Rc.
6. The successive approximation type capacitance detection circuit according to claim 5, wherein when the binary code received by the switches SW1 to SW8 is 1, the corresponding switch is turned off; when the received binary code is 0, the corresponding switch is turned on and charges the charging resistor Rc.
7. The successive approximation type capacitance detection circuit according to claim 6, wherein the midpoints of the switches SW1 and SW5, the midpoints of the switches SW2 and S6, the midpoints of the switches SW3 and SW7, the midpoints of the switches SW4 and SW8, and the midpoint of the power source ICC and the charging resistor Rc are shorted as the output of the current array module.
8. The successive approximation type capacitance detection circuit according to claim 7, wherein the current magnitude ratio of the current sources I1, I2, I3 and the ratio of the current sources I5, I6, I7 and I8 are each 1:2:4:8.
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