CN111816561A - 一种半导体结构及其制备方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000002360 preparation method Methods 0.000 title abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 13
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 230000008021 deposition Effects 0.000 claims abstract description 8
- 238000004519 manufacturing process Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 23
- 229920005591 polysilicon Polymers 0.000 claims description 17
- 239000000126 substance Substances 0.000 claims description 9
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 5
- 238000005121 nitriding Methods 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims 2
- 238000004140 cleaning Methods 0.000 abstract description 8
- 238000005530 etching Methods 0.000 abstract description 7
- 239000000463 material Substances 0.000 abstract description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 9
- 229910052721 tungsten Inorganic materials 0.000 description 9
- 239000010937 tungsten Substances 0.000 description 9
- 238000011534 incubation Methods 0.000 description 6
- 230000007547 defect Effects 0.000 description 5
- 239000012528 membrane Substances 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- -1 titanium strontium nitride Chemical class 0.000 description 3
- 238000012876 topography Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
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Abstract
本发明涉及一种半导体结构及其制备方法。一种半导体结构,包括半导体衬底,所述半导体衬底上沉积有多层物质,该多层物质形成有多重界面的表面,所述多重界面的表面上依次沉积有等离子氮化层和Si3N4层。一种半导体结构的制备方法,包括下列步骤:在具有多重界面的半导体载体上进行等离子体氮化(Plasma Nitridation,PN)处理,然后沉积Si3N4。本发明解决了湿清洁半导体结构时多晶硅被刻蚀引发器件不良的问题。
Description
技术领域
本发明涉及半导体制作领域,特别涉及一种半导体结构及其制备方法。
背景技术
在半导体器件中通常需要镀Si3N4膜作为绝缘层,并且器件构造中与Si3N4膜相邻的通常为多重界面(interface)构造,例如存储器与逻辑器件中的门阵列(Gate)。以存储器中的BL位线(Bit Line)为例,其制作过程是:在半导体载衬底上蒸镀多重物质(例如多晶硅(Poly Si)、钨(Tungsten,W)、钛锶氮化物等),选取部分具有两重界面的结构如图1所示,经过图形化及刻蚀后,再蒸镀Si3N4膜。在蒸镀Si3N4膜时,由于多重界面的存在导致不同界面的孵化时间不同,这样会导致不同物质界面上的Si3N4膜厚不一致,如图2所示,该膜厚的差异会再后续的湿清洁时产生如下问题:薄的Si3N4膜上产生针孔(pin hole),进而导致下层的多晶硅被刻蚀。多晶硅被刻蚀会引发器件不良,特别是使用空气侧墙(Air Gap Spacer)时,为了去除BL位线上的氧化物杂质,刻蚀剂会再次流入Si3N4膜之间,让不良变得更严重。然而现有技术尚未发现更好的方法解决上述问题。
发明内容
本发明的第一目的在于提供一种半导体结构,该结构解决了湿清洁半导体结构时多晶硅(或者其他功能性界面物质)被刻蚀引发器件不良的问题。
本发明的第二目的在于提供一种半导体结构的制备方法,该方法解决了现有制备方法容易引发器件不良的问题。
为了实现以上目的,本发明提供了以下技术方案:
一种半导体结构,包括半导体衬底,
所述半导体衬底上沉积有多层物质,该多层物质形成有多重界面的表面,所述多重界面的表面上依次沉积有等离子氮化层和Si3N4层。
在该半导体结构中,在多重界面上增加的等离子体氮化层可以掩盖多重界面性质不同、沉积相同物质时孵化时间不同的缺点,即通过修饰将多重界面的性质一致化,沉积其他物质时孵化时间相同,进而使得上层沉积的Si3N4可以有均匀的膜厚,此时即使在后续湿清洁时会有刻蚀问题,也不至于薄的Si3N4被完全刻蚀掉进而刻蚀至多重界面的物质中。
其中,所述半导体衬底上沉积的“多层物质”的构造可以是:不同物质上下堆叠且在表面上有“首尾”相邻的关系,或者没有上下堆叠,仅仅在暴露在外的表面上有首尾相邻的关系。本发明对此并不作限制,只要暴露在外的表面有多重界面即可。
所述“等离子氮化层”是指通过等离子体渗氮技术形成的等离子氮化层。
一种半导体结构的制备方法,包括下列步骤:
在具有多重界面的半导体载体上进行等离子体氮化(Plasma Nitridation,PN)处理,然后沉积Si3N4。
与上述原理相同,该方法也解决了湿清洁半导体结构时多晶硅(或者其他功能性界面物质)被刻蚀引发器件不良的问题。
附图说明
通过阅读下文优选实施方式的详细描述,各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的,而并不认为是对本发明的限制。而且在整个附图中,用相同的参考符号表示相同的部件。
图1为具有两重界面的半导体结构;
图2为在图1的多重界面上直接沉积Si3N4膜后的形貌;
图3为在含有多晶硅、钨和氮化物的三重界面上直接沉积Si3N4膜后的形貌;
图4为图3的结构经过湿清洁后的形貌;
图5为在含有多晶硅、钨和氮化物的三重界面上采用本发明的方法沉积Si3N4膜后的形貌;
图6为图5的结构经过湿清洁后的形貌;
图7为含多晶硅和钨的两重界面上等离子体氮化处理后的形貌;
图8为在图7的结构上沉积Si3N4膜后的形貌。
具体实施方式
以下,将参照附图来描述本发明的实施例。但是应该理解,这些描述只是示例性的,而并非要限制本发明的范围。此外,在以下说明中,省略了对公知结构和技术的描述,以避免不必要地混淆本发明的概念。
在附图中示出了根据本发明实施例的各种结构示意图。这些图并非是按比例绘制的,其中为了清楚表达的目的,放大了某些细节,并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的,实际中可能由于制造公差或技术限制而有所偏差,并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本发明的上下文中,当将一层/元件称作位于另一层/元件“上”时,该层/元件可以直接位于该另一层/元件上,或者它们之间可以存在居中层/元件。另外,如果在一种朝向中一层/元件位于另一层/元件“上”,那么当调转朝向时,该层/元件可以位于该另一层/元件“下”。
实施例
如图3所示,在含有多晶硅、钨和氮化物(Nitride)形成的多重界面的半导体结构中,直接在多重界面上沉积Si3N4膜101后的结构如图3所示。从图中可以看出,由于孵化时间的差异导致钨层上沉积的膜厚和多晶硅上沉积的膜厚有显著差异,多晶硅上沉积的膜明显薄,如果在该结构上继续后续的湿清洁和等离子体氧化,会发生如图4所示的现象,参见被刻蚀的Si3N4膜102,即多晶硅界面的Si3N4膜被完全刻蚀掉,且多晶硅也被连带刻蚀(即图中箭头所指的poly Si burst),这会引发器件的不良。
如图5所示,在含有多晶硅、钨和氮化物形成的多重界面的半导体结构中,先进行等离子体氮化处理,使得多重界面上具有相同的孵化时间,此时再沉积Si3N4膜201,得到的结构如图5所示,Si3N4膜201厚度相同,如果在该结构上继续后续的湿清洁和等离子体氧化,则会得到如图6所示的效果,即使有针孔现象,由于均匀的膜厚不会导致多晶硅上的Si3N4膜202被完全刻蚀,就不会出现多晶硅被刻蚀的问题。
以上实施方式中等离子体氮化的方式是任选的,可以采用偏压法或非偏压法。
等离子体氮化处理采用的设备也是任选的,包括但不限于集群式设备、炉管式设备或旋转式设备(Merry-go-round)。
等离子体氮化处理采用的工艺气体也是任选适宜等离子体处理的,包括但不限于:NH3、N2以及Ar。
不同方式、不同设备或不同工艺调节都可以达到与如图3和4相同的效果,即使多重界面的孵化时间相同,沉积的Si3N4膜厚相同,即具有较高的保形性。
如上文所述,本发明的主要技术构思是在沉积Si3N4前,进行等离子体氮化预处理。因此,本发明的应用不受多重界面的界面数量(例如两重、四重、五重等更多重界面)、界面物质的类型以及不同图形或者不同半导体类型的限制。例如,图3和图5中的氮化物可以是任意类型的氮化物,包括但不限于常见的氮化钛、氮化锶。上述实施例中的钨也可以用其他的导电材料来代替,例如可以是金属材料,本发明对此不做限制。
本发明还可用于两重界面的Si3N4沉积,如图1所示,在钨和多晶硅的两重界面上,经过等离子体氮化处理形成如图7所示的结构,在沉积Si3N4,形成的结构如图8所示,膜厚均匀,保形性高。
另外,出现多重界面结构的半导体器件均适用于本发明,例如存储器结构或逻辑器件结构,包括但不限于DRAM,2D NAND,3D NAND或LCD。
本发明中沉积的Si3N4层的功能并不限于绝缘,也可以作为掩模或者阻挡材料,只要承载Si3N4的界面为多重界面都适用于本发明。
在以上的描述中,对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解,可以通过各种技术手段,来形成所需形状的层、区域等。另外,为了形成同一结构,本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外,尽管在以上分别描述了各实施例,但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本发明的实施例进行了描述。但是,这些实施例仅仅是为了说明的目的,而并非为了限制本发明的范围。本发明的范围由所附权利要求及其等价物限定。不脱离本发明的范围,本领域技术人员可以做出多种替代和修改,这些替代和修改都应落在本发明的范围之内。
Claims (12)
1.一种半导体结构,其特征在于,包括半导体衬底,
所述半导体衬底上沉积有多层物质,该多层物质形成有多重界面的表面,所述多重界面的表面上依次沉积有等离子氮化层和Si3N4层。
2.根据权利要求1所述的半导体结构,其特征在于,所述半导体结构为包含BL位线的结构。
3.根据权利要求1所述的半导体结构,其特征在于,所述半导体结构为存储器结构或逻辑器件结构。
4.根据权利要求3所述的半导体结构,其特征在于,所述半导体结构为DRAM,2D NAND,3D NAND或LCD。
5.根据权利要求1所述的半导体结构,其特征在于,所述多层物质包括以下中的至少两种:多晶硅、金属以及氮化物。
6.一种半导体结构的制备方法,其特征在于,包括下列步骤:
在具有多重界面的半导体载体上进行等离子体氮化处理,然后沉积Si3N4。
7.根据权利要求6所述的制备方法,其特征在于,所述具有多重界面的半导体载体为存储器结构或逻辑器件结构。
8.根据权利要求6所述的制备方法,其特征在于,所述等离子体氮化处理的方法为偏压法或非偏压法。
9.根据权利要求8所述的制备方法,其特征在于,所述等离子体氮化处理时所用的工艺气体为以下中的至少一种:NH3、N2以及Ar。
10.根据权利要求6-9任一项所述的制备方法,其特征在于,所述等离子体氮化处理采用集群式设备、炉管式设备或旋转式设备(Merry-go-round)。
11.根据权利要求6-9任一项所述的制备方法,其特征在于,所述半导体结构为DRAM,2DNAND,3D NAND或LCD。
12.根据权利要求6-9任一项所述的制备方法,其特征在于,所述多重界面为以下中的至少两种物质形成的界面:多晶硅、金属以及氮化物。
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US6686277B1 (en) * | 2000-09-11 | 2004-02-03 | Oki Electric Industry Co., Ltd. | Method of manufacturing semiconductor device |
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US6686277B1 (en) * | 2000-09-11 | 2004-02-03 | Oki Electric Industry Co., Ltd. | Method of manufacturing semiconductor device |
US20040121526A1 (en) * | 2002-12-20 | 2004-06-24 | Naoki Yamamoto | Fabrication process of a semiconductor integrated circuit device |
KR100860469B1 (ko) * | 2007-06-26 | 2008-09-25 | 주식회사 동부하이텍 | 플래쉬 메모리 제조방법 |
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