CN111785808A - Method for removing plated polysilicon of TOPCon battery and application - Google Patents
Method for removing plated polysilicon of TOPCon battery and application Download PDFInfo
- Publication number
- CN111785808A CN111785808A CN202010667851.7A CN202010667851A CN111785808A CN 111785808 A CN111785808 A CN 111785808A CN 202010667851 A CN202010667851 A CN 202010667851A CN 111785808 A CN111785808 A CN 111785808A
- Authority
- CN
- China
- Prior art keywords
- silicon layer
- layer
- psg
- polycrystalline silicon
- phosphorus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 69
- 238000000034 method Methods 0.000 title claims abstract description 48
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 60
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 60
- 239000010703 silicon Substances 0.000 claims abstract description 60
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 31
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052796 boron Inorganic materials 0.000 claims abstract description 23
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 20
- 239000011574 phosphorus Substances 0.000 claims abstract description 20
- 230000005641 tunneling Effects 0.000 claims abstract description 17
- 238000007747 plating Methods 0.000 claims abstract description 16
- 238000004804 winding Methods 0.000 claims abstract description 16
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims abstract description 15
- 238000009792 diffusion process Methods 0.000 claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 claims abstract description 11
- 238000000137 annealing Methods 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims abstract description 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 26
- 239000000243 solution Substances 0.000 claims description 19
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 239000003513 alkali Substances 0.000 claims description 7
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 3
- 239000012670 alkaline solution Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 3
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 2
- 238000007667 floating Methods 0.000 claims description 2
- 229910017604 nitric acid Inorganic materials 0.000 claims description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 31
- 239000005360 phosphosilicate glass Substances 0.000 description 26
- 239000005388 borosilicate glass Substances 0.000 description 23
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- 239000000654 additive Substances 0.000 description 6
- 230000000996 additive effect Effects 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 230000000717 retained effect Effects 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229940051841 polyoxyethylene ether Drugs 0.000 description 2
- 229920000056 polyoxyethylene ether Polymers 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a method for removing plated polysilicon of a TOPCon battery and application thereof, wherein the method comprises the following steps: obtaining a silicon substrate with a front surface covered with a boron emitter and BSG and a back surface polished; fabricating a tunneling oxide layer on the back surface; depositing amorphous silicon layers on the two sides of the silicon substrate by LPCVD; crystallizing the amorphous silicon layer on the back into a phosphorus-doped polycrystalline silicon layer by phosphorus diffusion annealing, and forming PSG on the surface of the phosphorus-doped polycrystalline silicon layer; removing PSG on the surface of the winding plating polycrystalline silicon layer on the front surface and the side surface of the silicon substrate; removing the winding-plated polysilicon layer; the front BSG and the back PSG are removed. According to the invention, the amorphous silicon layer is deposited on the back surface, and simultaneously a layer of amorphous silicon layer is deposited on the front surface and the side surface, so that the phenomenon that the amorphous silicon layer is not uniform on the front surface in the prior art is solved, and the boron emitter on the front surface is protected from being damaged; the leakage current of the battery is greatly reduced; the process flow is simplified; and other devices are not required to be additionally arranged, so that the production cost is reduced.
Description
Technical Field
The invention relates to the technical field of crystalline silicon solar cells, in particular to a method for removing plated polysilicon of a TOPCon cell and application thereof.
Background
Low Pressure Chemical Vapor Deposition (LPCVD) is a key technology for fabricating tunnel oxide passivation contact (TOPCon) cell backside amorphous silicon layer. When an amorphous silicon layer is deposited on the back surface of a silicon wafer by LPCVD, the front surface of the silicon wafer generates winding plating amorphous silicon at the edge of the silicon wafer due to the winding plating phenomenon, and the amorphous silicon is converted into polycrystalline silicon after phosphorus diffusion annealing. Because the polysilicon layer has a high absorption coefficient, once the polysilicon layer appears on the front side of the battery, the absorption of sunlight on the front side of the battery is influenced, and meanwhile, the conductivity of the polysilicon layer causes serious electric leakage at the edge of the battery.
In the existing method for removing LPCVD (low pressure chemical vapor deposition) winding-plated polycrystalline silicon, before single-side deposition of amorphous silicon on a silicon wafer, a layer of borosilicate glass (BSG) is reserved on the surface of a boron emitter on the front side and is used as a mask on the front side of the silicon wafer when the winding-plated polycrystalline silicon is removed, phosphosilicate glass (PSG) formed by phosphorus diffusion annealing after the deposition of the amorphous silicon is used as a mask on the back side of the silicon wafer, then the PSG on the surface of the winding-plated polycrystalline silicon is removed, and the winding-plated polycrystalline silicon is. Although the characteristic that the BSG and the PSG have lower corrosion rate in the alkaline solution is utilized to protect the front boron emitter and the back polysilicon layer from being corroded, the change of the BSG property caused by phosphorus doping is ignored. Because phosphorus element enters BSG which is not covered with the winding-plated polycrystalline silicon in the phosphorus diffusion annealing process, the reaction rate of the BSG and HF acid is greatly improved due to the introduction of the phosphorus element, so that the BSG which is not covered with the winding-plated polycrystalline silicon in the PSG removing process on the surface of the winding-plated polycrystalline silicon is greatly removed, and further, a boron emitter on the front surface of a silicon wafer is easily damaged in the subsequent winding-plated polycrystalline silicon removing process, and the efficiency of a battery is reduced. Therefore, an extra process step is usually required, and a layer of mask is prepared on the front surface of the silicon wafer to solve the problem of damage to the front boron emitter when the spin-on polysilicon is removed, so that the process flow is complex and the period is long.
Disclosure of Invention
The purpose of the invention is as follows: the invention aims to provide a method for removing the plating-around polysilicon of a TOPCon battery, which can not only avoid the condition that a boron emitter on the front surface of a silicon wafer is damaged in the process of removing the plating-around polysilicon, but also simplify the process flow.
The invention also aims to provide the application of the method for removing the plating-wound polycrystalline silicon in the manufacture of TOPCon batteries.
The technical scheme is as follows: the technical scheme adopted by the invention is a method for removing plated polysilicon of a TOPCon battery, which comprises the following steps:
(1) obtaining a silicon substrate with a front surface covered with a boron emitter and BSG and a back surface polished;
(2) manufacturing a tunneling oxide layer on the back surface of the silicon substrate;
(3) depositing amorphous silicon layers on the two sides of the silicon substrate by LPCVD;
(4) crystallizing the amorphous silicon layer into a phosphorus-doped polycrystalline silicon layer by phosphorus diffusion annealing, and forming PSG on the surface of the phosphorus-doped polycrystalline silicon layer;
(5) removing PSG on the surface of the winding plating polycrystalline silicon layer on the front surface and the side surface of the silicon substrate;
(6) removing the winding plating polycrystalline silicon layer positioned on the front surface and the side surface of the silicon substrate;
(7) and removing the BSG on the front surface and the PSG on the surface, far away from the tunneling oxide layer, of the phosphorus-doped polycrystalline silicon layer on the back surface.
Wherein, in step (1), the BSG covers the boron emitter.
In the step (2), the tunneling oxide layer is prepared by nitric acid oxidation, thermal oxidation, ozone oxidation or LPCVD (low pressure chemical vapor deposition) in-situ growth method.
Wherein, in the step (2), the thickness of the tunneling oxide layer is 0.5-3 nm.
In the step (3), the thickness of the amorphous silicon layer is 30-300 nm.
Wherein in the step (4), the concentration of the phosphorus element in the phosphorus-doped polycrystalline silicon layer is 1E 19-1E 22/cm3The thickness of the PSG is 1-40 nm.
And (5) removing the PSG on the surface of the winding plating polycrystalline silicon layer in a hydrofluoric acid water floating mode. Further, the concentration of the hydrofluoric acid solution is 0.5-10%, and the time is 5-300 s.
And (6) removing the winding-plated polycrystalline silicon layer by adopting an alkaline solution etching mode. Further, the concentration of the alkali solution is 0.5-10%, the temperature is 25-70 ℃, and the time is 20-1200 s. Furthermore, the proportion of the additive in the alkali solution is 0.5-10%. Still further, the additive comprises fatty alcohol-polyoxyethylene ether.
And (7) cleaning and removing the BSG on the front surface and the PSG on the back surface by adopting hydrofluoric acid. Further, the concentration of the hydrofluoric acid solution is 5-15%, the temperature is room temperature, and the cleaning time is 10-1800 s.
The invention also provides application of the method for removing the winding plating polycrystalline silicon in the manufacture of the TOPCon battery.
The invention provides a method for removing plated polysilicon of a TOPCon battery, which comprises the following steps:
obtaining a silicon substrate with a front surface covered with a boron emitter and BSG and a back surface polished;
manufacturing a tunneling oxide layer on the back surface of the silicon substrate;
inserting the silicon substrate into the wafer independently to enable the front surface, the back surface and the side surfaces of the silicon substrate to be completely exposed to atmosphere, depositing amorphous silicon layers on the two surfaces of the silicon substrate by LPCVD, specifically, depositing the amorphous silicon layers on the surfaces, far away from the silicon substrate, of the back surface tunneling oxide layer, and the amorphous silicon layers deposited on the front surface and the side surfaces are called as winding-plated amorphous silicon layers;
crystallizing the amorphous silicon layer on the back into a phosphorus-doped polycrystalline silicon layer by utilizing phosphorus diffusion annealing, forming PSG on the surface of the phosphorus-doped polycrystalline silicon layer, crystallizing the winding-plated amorphous silicon layers on the front surface and the side surface of the silicon substrate into a winding-plated polycrystalline silicon layer, and forming PSG on the surface of the winding-plated polycrystalline silicon layer;
removing PSG on the surface of the winding plating polycrystalline silicon layer on the front surface and the side surface of the silicon substrate;
removing the winding plating polycrystalline silicon layer positioned on the front surface and the side surface of the silicon substrate;
and removing the BSG on the front surface and the PSG on the surface of the phosphorus-doped polycrystalline silicon layer, which is far away from the tunneling oxide layer, on the back surface.
According to the invention, while the amorphous silicon layer is deposited on the back surface, a uniform winding-plated amorphous silicon layer is deposited on the front surface and the side surface to serve as a mask layer, and the winding-plated amorphous silicon layer can prevent phosphorus element from entering BSG on the front surface in the phosphorus diffusion annealing process, so that a part of BSG is prevented from being removed due to the doping of the phosphorus element when the PSG is subsequently removed, and further a boron emitter on the front surface is prevented from being damaged; and secondly, when the PSG on the surface of the plating-around polycrystalline silicon is removed, the BSG can be completely isolated from being contacted with hydrofluoric acid solution, so that the front boron emitter is prevented from being damaged. Therefore, the tunneling oxide layer and the phosphorus-doped polycrystalline silicon layer on the front boron emitter and the back of the silicon substrate are completely reserved.
Has the advantages that: compared with the prior art, the invention has the following remarkable advantages:
(1) according to the invention, the amorphous silicon layer is deposited on the back surface, and simultaneously the amorphous silicon layers are deposited on the front surface and the side surfaces, so that the problem that the amorphous silicon layer is not uniform on the front surface in the prior art is solved, and the amorphous silicon layer on the front surface is used as a front mask layer to protect a boron emitter on the front surface from being damaged;
(2) the invention simplifies the process flow, does not need to add steps to manufacture the front mask layer, prepares the front mask while manufacturing the amorphous silicon layer on the back surface, and is simple and easy to implement;
(3) the invention greatly reduces the leakage current of the finished battery and improves the conversion efficiency of the finished battery;
(4) the invention can be realized by using the existing production equipment of the solar cell line without additionally adding other equipment, thereby reducing the production cost.
Drawings
FIG. 1 is a process flow diagram of the present invention.
Detailed Description
The technical solution of the present invention is further described below with reference to the accompanying drawings and examples.
The silicon substrate is an N-type silicon wafer, the front surface of the silicon substrate is covered with a boron emitter and BSG, and the back surface of the silicon substrate is a polished surface, wherein the BSG is positioned on the surface of the boron emitter far away from the silicon substrate.
Further, the process of obtaining the silicon substrate with the front surface covered with the boron emitter and the BSG and the back surface polished comprises the steps of obtaining an original N-type silicon wafer, texturing the original N-type silicon wafer, performing boron diffusion on the surface of the textured silicon wafer, and polishing the back surface of the silicon wafer.
Example 1
This embodiment provides a method for preparing a TOPCon battery, as shown in fig. 1, which mainly includes the following steps:
(S1) taking a back-polished N-type silicon wafer whose front surface is covered with a boron emitter and BSG.
(S2) depositing a tunneling oxide layer with the thickness of 3nm on the back of the silicon wafer through thermal oxidation.
(S3) independently inserting the silicon wafer, exposing the front surface, the back surface and the side surface of the silicon wafer to an atmosphere environment, and depositing an amorphous silicon layer with the thickness of 200nm on the surface of the tunneling oxide layer on the back surface by LPCVD, wherein the amorphous silicon layer with the thickness of 200nm is also deposited on the surface of the BSG on the front surface and the side surface, which is called as a winding-plating amorphous silicon layer.
(S4) the front side and the front side of the silicon wafer are closely attached, the silicon wafer is placed into a diffusion furnace tube for phosphorus diffusion annealing, the amorphous silicon layer on the back side can be crystallized into a phosphorus-doped polycrystalline silicon layer, the winding-plated amorphous silicon layers on the front side and the side can be crystallized into a winding-plated polycrystalline silicon layer, PSG with the thickness of 40nm is formed on the surface of the phosphorus-doped polycrystalline silicon layer, and the concentration of phosphorus element in the phosphorus-doped polycrystalline silicon is 1E22/cm3. Due to the effect of the winding and expanding, PSG with certain thickness can be formed on the surfaces of the winding and plating polycrystalline silicon layers on the front surface and the side surfaces, but the thickness of the PSG on the front surface is far smaller than that of the PSG on the back surface, and the front surface is uniformly covered by the winding and plating polycrystalline silicon layer and is used as a front surface mask, so that phosphorus elements are effectively prevented from entering the BSG on the front surface in the phosphorus diffusion annealing process.
(S5) the silicon wafer was floated with the front side down on a hydrofluoric acid solution with a concentration of 5% for removing PSG around the surface of the polysilicon layer on the front and side surfaces for 150 seconds.
(S6) etching to remove the wound-plated polysilicon, adopting 5% NaOH solution, heating to 25 ℃, keeping the temperature for 1200S, adding 5% of additive into the alkali liquor, wherein the additive contains fatty alcohol-polyoxyethylene ether and other substances, so as to reduce the reaction rate of PSG on the surface of the phosphorus-doped polysilicon in the alkali solution.
(S7) the front side BSG and the back side PSG were removed by cleaning, and the substrate was cleaned with a 5% hydrofluoric acid solution at room temperature for 1000 seconds.
(S8) preparing passivation layers on the front and back sides of the silicon wafer, respectively.
(S9) preparing a front electrode and a back electrode on the front surface and the back surface of the silicon chip respectively to obtain the TOPCon battery.
The silicon wafer of this example completely retained the front boron emitter, the tunnel oxide layer and the phosphorus-doped polysilicon layer on the back, and the size of the prepared TOPCon cell leakage (Irev 2) was 0.213A.
Example 2
This example provides a method for preparing a TOPCon battery, which is the same as example 1 except that:
(S2) depositing a tunneling oxide layer with the thickness of 0.5nm on the back of the silicon wafer through ozone oxidation.
(S3) the amorphous silicon layer has a thickness of 300 nm.
(S4) the thickness of PSG on the back of the silicon wafer is 20nm, and the concentration of phosphorus element in the phosphorus-doped polysilicon is 1E19/cm3。
(S5) the hydrofluoric acid solution has a concentration of 10% for 5 seconds.
(S6) KOH solution with the concentration of 10% is adopted, the temperature is 70 ℃, the time is 20S, and additives with the proportion of 0.5% are also added into the alkali liquor.
(S7) washing the substrate with 15% hydrofluoric acid solution at room temperature for 10S.
The silicon wafer of this example completely retained the front boron emitter, the tunnel oxide layer and the phosphorus-doped polysilicon layer on the back, and the size of the prepared TOPCon cell leakage (Irev 2) was 0.124A.
Example 3
This example provides a method for preparing a TOPCon battery, which is the same as example 1 except that:
(S2) growing a tunneling oxide layer with the thickness of 2nm on the back of the silicon wafer in situ by LPCVD.
(S3) the amorphous silicon layer has a thickness of 30 nm.
(S4) silicon waferThe thickness of the PSG on the back surface is 1nm, and the concentration of phosphorus element in the phosphorus-doped polysilicon is 1E19/cm3。
(S5) the hydrofluoric acid solution has a concentration of 0.5% for 300S.
(S6) adopting 0.5% NaOH solution, at 70 deg.C for 300S, and adding 10% additive into the alkali solution.
(S7) cleaning the substrate for 1800S at room temperature by using a hydrofluoric acid solution with a concentration of 5%.
The silicon wafer of this example completely retained the front boron emitter, the tunnel oxide layer and the phosphorus-doped polysilicon layer on the back, and the size of the prepared TOPCon cell leakage (Irev 2) was 0.292A.
Comparative example
The difference from example 1 is that amorphous silicon is deposited on one side of the silicon wafer in the step (S3), that is, amorphous silicon is deposited on two adjacent silicon wafers with the front sides close to the front sides. The TOPCon cell prepared for the comparative example had a leakage (Irev 2) size of 0.501A.
Comparing the TOPCon cells prepared in examples 1-3 and the comparative example, it can be seen that the method for removing the winding-plated polysilicon reduces the leakage current of the finished cell to 0.124-0.292A, greatly reduces the leakage current of the finished cell, and does not add extra steps to prepare the front mask.
Claims (10)
1. A method for removing plated polysilicon of a TOPCon battery is characterized by comprising the following steps:
(1) obtaining a silicon substrate with a front surface covered with a boron emitter and BSG and a back surface polished;
(2) manufacturing a tunneling oxide layer on the back surface of the silicon substrate;
(3) depositing amorphous silicon layers on the two sides of the silicon substrate by LPCVD;
(4) crystallizing the amorphous silicon layer into a phosphorus-doped polycrystalline silicon layer by phosphorus diffusion annealing, and forming PSG on the surface of the phosphorus-doped polycrystalline silicon layer;
(5) removing PSG on the surface of the winding plating polycrystalline silicon layer on the front surface and the side surface of the silicon substrate;
(6) removing the winding plating polycrystalline silicon layer positioned on the front surface and the side surface of the silicon substrate;
(7) and removing the BSG on the front surface and the PSG on the surface, far away from the tunneling oxide layer, of the phosphorus-doped polycrystalline silicon layer on the back surface.
2. The method as claimed in claim 1, wherein the method comprises the steps of: in the step (2), the tunneling oxide layer is prepared by nitric acid oxidation, thermal oxidation, ozone oxidation or LPCVD (low pressure chemical vapor deposition) in-situ growth method.
3. The method as claimed in claim 1, wherein the method comprises the steps of: in the step (2), the thickness of the tunneling oxide layer is 0.5-3 nm.
4. The method as claimed in claim 1, wherein the method comprises the steps of: in the step (3), the thickness of the amorphous silicon layer is 30-300 nm.
5. The method as claimed in claim 1, wherein the method comprises the steps of: in the step (4), the thickness of the PSG is 1-40 nm.
6. The method as claimed in claim 1, wherein the method comprises the steps of: and (5) removing the PSG on the surface of the winding plating polycrystalline silicon layer in a hydrofluoric acid water floating mode.
7. The method as claimed in claim 6, wherein the method comprises the steps of: in the step (5), the concentration of the hydrofluoric acid solution is 0.5-10%, and the time is 5-300 s.
8. The method as claimed in claim 1, wherein the method comprises the steps of: and (6) removing the winding plating polycrystalline silicon layer by adopting an alkaline solution etching mode.
9. The method as claimed in claim 8, wherein the method comprises the steps of: in the step (6), the concentration of the alkali solution is 0.5-10%, the temperature is 25-70 ℃, and the time is 5-1200 s.
10. Use of the method of removing the spiral-wound polysilicon as claimed in any one of claims 1 to 9 in the fabrication of TOPCon cells.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010667851.7A CN111785808A (en) | 2020-07-13 | 2020-07-13 | Method for removing plated polysilicon of TOPCon battery and application |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010667851.7A CN111785808A (en) | 2020-07-13 | 2020-07-13 | Method for removing plated polysilicon of TOPCon battery and application |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111785808A true CN111785808A (en) | 2020-10-16 |
Family
ID=72768076
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010667851.7A Pending CN111785808A (en) | 2020-07-13 | 2020-07-13 | Method for removing plated polysilicon of TOPCon battery and application |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111785808A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114122195A (en) * | 2021-11-24 | 2022-03-01 | 湖南红太阳新能源科技有限公司 | Cleaning process for winding-plated polycrystalline silicon |
| CN114613881A (en) * | 2022-02-24 | 2022-06-10 | 浙江晶科能源有限公司 | Solar cell, preparation method thereof and photovoltaic module |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109686816A (en) * | 2018-12-06 | 2019-04-26 | 国家电投集团西安太阳能电力有限公司 | The preparation method of passivation contact N-type solar cell |
| CN109698254A (en) * | 2018-12-26 | 2019-04-30 | 浙江晶科能源有限公司 | A method of removal LPCVD polysilicon is around plating |
| CN110257072A (en) * | 2019-06-13 | 2019-09-20 | 常州时创能源科技有限公司 | Silicon wafer one texture-etching side and etching edge additive and its application |
| CN110416359A (en) * | 2019-07-19 | 2019-11-05 | 常州时创能源科技有限公司 | A kind of preparation method of TOPCon structure battery |
| CN110459642A (en) * | 2018-11-06 | 2019-11-15 | 协鑫集成科技股份有限公司 | Passivation contact battery and preparation method thereof |
| CN110660881A (en) * | 2019-08-30 | 2020-01-07 | 泰州中来光电科技有限公司 | Method for removing polycrystalline silicon of passivated contact cell by winding plating without mask |
| CN111029438A (en) * | 2019-12-04 | 2020-04-17 | 江苏杰太光电技术有限公司 | Preparation method of N-type passivated contact solar cell |
| CN111180544A (en) * | 2020-01-06 | 2020-05-19 | 浙江晶科能源有限公司 | Passivated contact crystalline silicon solar cell and manufacturing method thereof |
-
2020
- 2020-07-13 CN CN202010667851.7A patent/CN111785808A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110459642A (en) * | 2018-11-06 | 2019-11-15 | 协鑫集成科技股份有限公司 | Passivation contact battery and preparation method thereof |
| CN109686816A (en) * | 2018-12-06 | 2019-04-26 | 国家电投集团西安太阳能电力有限公司 | The preparation method of passivation contact N-type solar cell |
| CN109698254A (en) * | 2018-12-26 | 2019-04-30 | 浙江晶科能源有限公司 | A method of removal LPCVD polysilicon is around plating |
| CN110257072A (en) * | 2019-06-13 | 2019-09-20 | 常州时创能源科技有限公司 | Silicon wafer one texture-etching side and etching edge additive and its application |
| CN110416359A (en) * | 2019-07-19 | 2019-11-05 | 常州时创能源科技有限公司 | A kind of preparation method of TOPCon structure battery |
| CN110660881A (en) * | 2019-08-30 | 2020-01-07 | 泰州中来光电科技有限公司 | Method for removing polycrystalline silicon of passivated contact cell by winding plating without mask |
| CN111029438A (en) * | 2019-12-04 | 2020-04-17 | 江苏杰太光电技术有限公司 | Preparation method of N-type passivated contact solar cell |
| CN111180544A (en) * | 2020-01-06 | 2020-05-19 | 浙江晶科能源有限公司 | Passivated contact crystalline silicon solar cell and manufacturing method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114122195A (en) * | 2021-11-24 | 2022-03-01 | 湖南红太阳新能源科技有限公司 | Cleaning process for winding-plated polycrystalline silicon |
| CN114122195B (en) * | 2021-11-24 | 2024-04-30 | 湖南红太阳新能源科技有限公司 | Cleaning process for coiled plating polysilicon |
| CN114613881A (en) * | 2022-02-24 | 2022-06-10 | 浙江晶科能源有限公司 | Solar cell, preparation method thereof and photovoltaic module |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111029438B (en) | Preparation method of N-type passivated contact solar cell | |
| CN111834493B (en) | Preparation method of TOPCon solar cell | |
| CN115312633B (en) | Mask-layer-free combined passivation back contact battery and preparation method thereof | |
| WO2023029059A1 (en) | Method for removing polycrystalline silicon plated on backside of n-topcon battery | |
| CN109616528B (en) | Preparation method of selective emitter of solar cell | |
| CN111640823B (en) | N-type passivated contact battery and preparation method thereof | |
| CN110854240A (en) | PERC battery and preparation method thereof | |
| CN105118898A (en) | Silicon chip surface passivation method and manufacturing method of N type double-face cell based thereon | |
| CN111883614B (en) | Edge isolation method and preparation method of passivated contact battery | |
| CN111785808A (en) | Method for removing plated polysilicon of TOPCon battery and application | |
| CN111987188A (en) | Preparation method of passivated contact battery | |
| CN114267753A (en) | TOPCon solar cell, preparation method thereof and photovoltaic module | |
| CN112349802B (en) | Manufacturing method of ingot casting single crystal or polycrystalline amorphous silicon heterojunction solar cell | |
| CN117153948A (en) | Passivation contact solar cell preparation method | |
| CN112466960A (en) | Solar cell structure and preparation method thereof | |
| CN116936651A (en) | Preparation method of novel TOPCON battery | |
| CN112133793A (en) | Back-junction back-contact solar cell and manufacturing method thereof | |
| CN114335237A (en) | Preparation method of crystalline silicon solar cell and crystalline silicon solar cell | |
| CN109755330B (en) | Pre-diffusion sheet for passivating contact structures, and preparation method and application thereof | |
| CN107749396B (en) | Plasma edge-etching method for diffusion-made crystalline silicon solar cell | |
| CN114937706B (en) | Laminated passivation film for crystalline silicon solar cell and preparation method thereof | |
| CN111180544B (en) | Passivated contact crystalline silicon solar cell and manufacturing method thereof | |
| CN114664954A (en) | Manufacturing method of passivated back contact solar cell | |
| CN210956692U (en) | PERC battery | |
| CN114038941A (en) | Solar cell preparation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20201016 |
|
| RJ01 | Rejection of invention patent application after publication |