CN111785782A - 一种适用于平面工艺的新型InAs-GaSb TFET - Google Patents
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Abstract
本发明涉及一种适用于平面工艺的新型InAs‑GaSb TFET,包括衬底;源区,设置在所述衬底上;第一漏区,设置在所述衬底上,且位于所述源区中;沟道层,设置在所述源区上;第二漏区,设置在所述第一漏区上;栅介质层,设置在所述沟道层和所述第二漏区上;栅极,设置在所述栅介质层上;源极,设置在所述源区上;漏极,设置在所述第二漏区上。本发明的新型InAs‑GaSb TFET,设置有第一漏区和第二漏区,第一漏区位于源区中,通过先外延、后注入的优化工艺引入了重掺杂漏区pn结,利用反偏pn结的电学阻隔特点在电学上实现源区与漏区间的有效电学隔断,而且制备工艺简单,与传统平面CMOS工艺高度兼容。
Description
技术领域
本发明属于微电子技术领域,具体涉及一种适用于平面工艺的新型 InAs-GaSbTFET。
背景技术
CMOS(Complementary Metal Oxide Semiconductor,互补金属氧化物半导体)作为超大规模集成电路最基础的单元一直以来备受学术界和工业界的关注。为了持续不断的提高集成电路的性能,CMOS器件的尺寸一直在缩小,这样就可以在同样大小的集成电路芯片中容纳更多的晶体管。随着CMOS器件尺寸的不断减小,芯片中晶体管的密度越来越大,但是在超高密度集成电路性能提升的同时,芯片的功耗密度也会急剧上升,由于功耗密度导致的发热问题会严重影响集成电路的可靠性。而且,随着 MOSFET(Metal-Oxide-Semiconductor Field Effect Transistor,金属-氧化物半导体场效应晶体管)特征尺寸继续减小到纳米量级,栅极的控制很难使得器件彻底关断,器件的关态泄漏功耗密度随晶体管尺寸的减小而指数倍增加,这会进一步增加发热而降低芯片性能以及可靠性。
基于带带隧穿工作机理的TFET(Tunneling Field EffectTransistor,隧穿场效应晶体管)可以突破传统MOSFET亚阈摆率不低于60mV/dec的限制,被认为是最有希望应用于超低功耗领域的半导体器件。但是,目前的Si基 TFET仍然面临着开态电流太低的问题。InAs/GaSb构成的异质结为第三类异质结,隧穿结开启时隧穿势垒高度理论上为零,可以实现非常高的隧穿电流,而且载流子有效质量小,隧穿更加容易,GaSb和InAs之间非常小的晶格失配可以形成高质量的InAs/GaSb隧穿异质结。
目前,有关于InAs/GaSb TFET的研究,大多都是纵向结构,另外,为达到源漏有效隔离,需通过湿法腐蚀形成“空气桥”结构或者“悬臂式”结构,此种结构的制备工艺极其复杂,与传统平面工艺难以兼容,而且悬空的沟道极易断裂,会造成严重的可靠性问题。
发明内容
为了解决现有技术中存在的上述问题,本发明提供了一种适用于平面工艺的新型InAs-GaSb TFET。本发明要解决的技术问题通过以下技术方案实现:
本发明提供了一种适用于平面工艺的新型InAs-GaSb TFET,包括:
衬底;
源区,设置在所述衬底上;
第一漏区,设置在所述衬底上,且位于所述源区中;
沟道层,设置在所述源区上;
第二漏区,设置在所述第一漏区上;
栅介质层,设置在所述沟道层和所述第二漏区上;
栅极,设置在所述栅介质层上;
源极,设置在所述源区上;
漏极,设置在所述第二漏区上。
在本发明的一个实施例中,所述源极与所述源区的界面为欧姆接触,所述漏极与所述第二漏区的界面为欧姆接触。
在本发明的一个实施例中,所述衬底为N型GaSb,掺杂浓度为 1×1017cm-3。
在本发明的一个实施例中,所述源区为P型GaSb,掺杂浓度为5×1017 cm-3-1×1019cm-3。
在本发明的一个实施例中,所述第一漏区为N型GaSb,掺杂浓度为 1×1018cm-3-5×1019cm-3。
在本发明的一个实施例中,所述沟道层为InAs,其厚度为5-20nm。
在本发明的一个实施例中,所述沟道层与所述源区接触区的长度为 30-70nm。
在本发明的一个实施例中,所述第二漏区为N型InAs,掺杂浓度为 1×1018cm-3-5×1019cm-3。
在本发明的一个实施例中,所述栅极与所述漏极之间的距离为 100-500nm。
与现有技术相比,本发明的有益效果在于:
1、本发明的适用于平面工艺的新型InAs-GaSb TFET,设置有第一漏区和第二漏区,第一漏区位于源区中,通过先外延、后注入的优化工艺引入了重掺杂漏区pn结,利用反偏pn结的电学阻隔特点在电学上实现源区与漏区间的有效电学隔断。
2、本发明的适用于平面工艺的新型InAs-GaSb TFET与传统的InAs/GaSb TFET相比,不需要引入“空气桥”结构或者“悬臂式”结构,避免了由于悬空的沟道断裂而造成的可靠性问题,而且本发明的InAs-GaSb TFET制备工艺简单,与传统平面CMOS工艺高度兼容。
3、本发明的适用于平面工艺的新型InAs-GaSb TFET通过先外延、后注入的优化工艺,有效避免了离子注入对隧穿结界面的损伤,完好的保障了异质隧穿结的界面质量,使得InAs-GaSb TFET器件具有开态电流大、亚阈值摆幅陡峭以及匹配性设计灵活的优点。
上述说明仅是本发明技术方案的概述,为了能够更清楚了解本发明的技术手段,而可依照说明书的内容予以实施,并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂,以下特举较佳实施例,并配合附图,详细说明如下。
附图说明
图1是本发明实施例提供的一种适用于平面工艺的新型InAs-GaSb TFET的结构示意图;
图2-图6是本发明实施例提供的新型InAs-GaSb TFET的制备方法示意图。
附图标记说明
1-衬底;2-源区;3-第一漏区;4-沟道层;5-第二漏区;6-栅介质层; 7-栅极;8-源极;9-漏极。
具体实施方式
为了进一步阐述本发明为达成预定发明目的所采取的技术手段及功效,以下结合附图及具体实施方式,对依据本发明提出的一种适用于平面工艺的新型InAs-GaSb TFET进行详细说明。
有关本发明的前述及其他技术内容、特点及功效,在以下配合附图的具体实施方式详细说明中即可清楚地呈现。通过具体实施方式的说明,可对本发明为达成预定目的所采取的技术手段及功效进行更加深入且具体地了解,然而所附附图仅是提供参考与说明之用,并非用来对本发明的技术方案加以限制。
目前,有关于InAs/GaSb TFET的研究,大多都是纵向结构,为了达到源区、漏区有效隔离,需通过湿法腐蚀形成“空气桥”结构或者“悬臂式”结构,这不仅对InAs沟道层的厚度有严格要求,而且悬空的沟道极易断裂,会造成严重的可靠性问题,给实际的制备与应用带来及大的不可控因素。另外,也有报道通过在衬底上引入p-i-n结构实现源区、漏区的电学隔离。但是,这种结构需要先在衬底上进行重掺杂的离子注入,形成源区与漏区,然后再进行沟道层的外延生长。该方法会在TFET器件的隧穿结界面处会存在大量缺陷,这是由于离子注入造成界面损伤而引起的,这些缺陷会通过辅助隧穿的形式参与器件导电,会导致器件的亚阈特性以及关态特性恶化,对器件的性能产生不良的影响。
实施例一
请参见图1,图1是本发明实施例提供的一种适用于平面工艺的新型 InAs-GaSbTFET的结构示意图。如图所示,该器件包括:
衬底1;
源区2,设置在衬底1上;
第一漏区3,设置在衬底1上,且位于源区2中;
沟道层4,设置在源区2上;
第二漏区5,设置在第一漏区3上;
栅介质层6,设置在沟道层4和第二漏区5上;
栅极7,设置在栅介质层6上;
源极8,设置在源区2上;
漏极9,设置在第二漏区5上。
在本实施例中,源极8与源区2的界面为欧姆接触,漏极9与第二漏区5的界面为欧姆接触,源极8和漏极9为Ti/Pt/Au金属。
具体地,衬底1为N型GaSb,优选地,N型GaSb的掺杂浓度为 1×1017cm-3。
进一步地,源区2为P型GaSb,掺杂剂为Be,优选地,P型GaSb的掺杂浓度为5×1017cm-3-1×1019cm-3。
进一步地,第一漏区3为N型GaSb,掺杂剂为S、Se或Te,优选地,掺杂浓度为1×1018cm-3-5×1019cm-3。
进一步地,沟道层4为InAs,其厚度为5-20nm,在本实施例中,栅控的沟道层4与源区2接触区的长度为30-70nm,栅极7与隧穿结的平行设计使得电场在隧穿结处近似均匀分布,在增大有效隧穿面积的同时可以进一步优化器件的亚阈值特性。
进一步地,第二漏区5为N型InAs,掺杂剂为S、Se或Te,优选地,掺杂浓度为1×1018cm-3-5×1019cm-3。
进一步地,在本实施例中,栅介质层6为Al2O3,栅极7为TiN,栅极 7的等效氧化层厚度为1nm。
进一步地,在本实施例中,栅极7与漏极9之间的距离为100-500nm。
本实施例的适用于平面工艺的新型InAs-GaSb TFET,N型GaSb作为第一漏区3,N型InAs作为第二漏区5,第一漏区3位于P型GaSb的源区 2中,且N型GaSb和N型InAs为重掺杂漏区,通过先外延、后注入的优化工艺引入重掺杂漏区pn结,利用反偏pn结的电学阻隔特点在电学上实现源区与漏区间的有效电学隔断。与传统的InAs/GaSb TFET相比,不需要引入“空气桥”结构或者“悬臂式”结构,避免了由于悬空的沟道断裂而造成的可靠性问题。
请参见图2-图6,图2-图6是本发明实施例提供的新型InAs-GaSb TFET 的制备方法示意图。在上述实施例的基础上,本实施例较为详细地对 InAs-GaSb TFET器件的制备流程进行介绍,包括:
S101:衬底材料选取。选取掺杂浓度为1×1017cm-3,晶向为<100>的N 型GaSb为衬底材料1。
S102:外延片生长制备。如图2所示,在轻掺杂的N型GaSb半导体衬底上,通过分子束外延技术,首先生长150nm厚的P型GaSb,掺杂剂为Be,掺杂浓度为1×1019cm-3,然后再生长3nm非掺杂的GaSb层作为过渡,外延生长的GaSb层为源区2。最后在顶层异质外延20nm厚的InAs 作为沟道层4;
S103:InAs层湿法腐蚀。如图3所示,在InAs沟道层4上涂覆光刻胶后,在空气环境中用热盘烘烤5min,温度为100℃,然后冷却5min后,使用柠檬酸溶液与双氧水的体积配比为2:1的溶液湿法腐蚀4min,腐蚀之后在流动的去离子水中至少冲洗1min停止刻蚀,最后用丙酮去除光刻胶,并在甲醇、异丙醇中清洗,然后用氮气吹干。
S104:重掺杂漏区形成。如图4所示,以光刻胶掩膜进行离子注入,其工艺同CMOS工艺中的N+注入条件,掺杂剂为S、Se或者Te,离子注入能量为5~30keV,剂量为1×1018cm-3-5×1019cm-3,形成N型GaSb第一漏区3和N型InAs第二漏区5。在600~900℃温度下快速退火5s,激活注入杂质。
S105:栅极形成。如图5所示,在沟道层4和第二漏区5上采用 ALD(Atomic layerdeposition,原子层沉积)工艺形成10nm的Al2O3作为栅介质层6,在栅介质层6上溅射100nm的TiN,然后进行剥离,形成栅极7。
S106:欧姆接触形成。如图6所示,利用光刻胶进行掩膜,在需要欧姆接触的区域利用BOE溶液进行腐蚀,去除多余的Al2O3栅介质。之后在稀盐酸溶液中浸泡30s去除表面氧化层,其中,HCl(37%):H2O=1:10,然后用去离子水清洗,在15%的(NH4)2S溶液浸泡30s,以防止表面再氧化,最后用去离子水清洗之后,电子束蒸发Ti/Pt/Au(30/30/100nm),分别与P型GaSb和N型InAs形成欧姆接触,作为TFET器件的源极8和漏极9。
S107:进行常规CMOS后道工序,包括淀积钝化层、开接触孔及金属化等,即可制得隧穿场效应晶体管。
本实施例的适用于平面工艺的新型InAs-GaSb TFET,通过先外延、后注入的优化工艺,有效避免了离子注入对隧穿结界面的损伤,完好的保障了异质隧穿结的界面质量,使得InAs-GaSb TFET器件具有开态电流大、亚阈值摆幅陡峭以及匹配性设计灵活的优点,而且制备工艺简单,与传统平面CMOS工艺高度兼容。
需要说明的是,在本申请文件中,诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来,而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且,术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含,从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素,而且还包括没有明确列出的其他要素,或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下,由语句“包括一个”限定的要素,并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明,不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干简单推演或替换,都应当视为属于本发明的保护范围。
Claims (9)
1.一种适用于平面工艺的新型InAs-GaSb TFET,其特征在于,包括:
衬底(1);
源区(2),设置在所述衬底(1)上;
第一漏区(3),设置在所述衬底(1)上,且位于所述源区(2)中;
沟道层(4),设置在所述源区(2)上;
第二漏区(5),设置在所述第一漏区(3)上;
栅介质层(6),设置在所述沟道层(4)和所述第二漏区(5)上;
栅极(7),设置在所述栅介质层(6)上;
源极(8),设置在所述源区(2)上;
漏极(9),设置在所述第二漏区(5)上。
2.根据权利要求1所述的适用于平面工艺的新型InAs-GaSb TFET,其特征在于,所述源极(8)与所述源区(2)的界面为欧姆接触,所述漏极(9)与所述第二漏区(5)的界面为欧姆接触。
3.根据权利要求1所述的适用于平面工艺的新型InAs-GaSb TFET,其特征在于,所述衬底(1)为N型GaSb,掺杂浓度为1×1017cm-3。
4.根据权利要求1所述的适用于平面工艺的新型InAs-GaSb TFET,其特征在于,所述源区(2)为P型GaSb,掺杂浓度为5×1017cm-3-1×1019cm-3。
5.根据权利要求1所述的适用于平面工艺的新型InAs-GaSb TFET,其特征在于,所述第一漏区(3)为N型GaSb,掺杂浓度为1×1018cm-3-5×1019cm-3。
6.根据权利要求1所述的适用于平面工艺的新型InAs-GaSb TFET,其特征在于,所述沟道层(4)为InAs,其厚度为5-20nm。
7.根据权利要求1所述的适用于平面工艺的新型InAs-GaSb TFET,其特征在于,所述沟道层(4)与所述源区(2)接触区的长度为30-70nm。
8.根据权利要求1所述的适用于平面工艺的新型InAs-GaSb TFET,其特征在于,所述第二漏区(5)为N型InAs,掺杂浓度为1×1018cm-3-5×1019cm-3。
9.根据权利要求1所述的适用于平面工艺的新型InAs-GaSb TFET,其特征在于,所述栅极(7)与所述漏极(9)之间的距离为100-500nm。
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