CN111755503A - 一种可变横向掺杂的终端结构及其制作方法 - Google Patents
一种可变横向掺杂的终端结构及其制作方法 Download PDFInfo
- Publication number
- CN111755503A CN111755503A CN202010662037.6A CN202010662037A CN111755503A CN 111755503 A CN111755503 A CN 111755503A CN 202010662037 A CN202010662037 A CN 202010662037A CN 111755503 A CN111755503 A CN 111755503A
- Authority
- CN
- China
- Prior art keywords
- layer
- deep
- metal level
- well
- terminal structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000002161 passivation Methods 0.000 claims abstract description 17
- 238000002347 injection Methods 0.000 claims abstract description 11
- 239000007924 injection Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 7
- 230000003647 oxidation Effects 0.000 claims abstract description 4
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 4
- 239000012535 impurity Substances 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 238000009792 diffusion process Methods 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 239000004642 Polyimide Substances 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- -1 boron ions Chemical class 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 2
- 238000004886 process control Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 230000008859 change Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8613—Mesa PN junction diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
本发明公布了一种可变横向掺杂的终端结构及其制作方法，主要包括终端结构本体，所述终端结构本体主要包括N型外延衬底及设置在N型外延衬底顶部外表面上的氧化层，所述N型外延衬底的其中一侧设置有深N阱区，N型外延衬底的另一侧通过P阱注入窗口设置有深P阱掺杂区，所述深P阱掺杂区的面积大于所述深N阱区的面积；所述深P阱掺杂区的上表面设置有第一金属层，所述深N阱区的上表面设置有与所述第一金属层高度对应的第二金属层，且所述第二金属层的宽度小于所述第一金属层的宽度，第二金属层的顶部设置有与所述氧化层的顶部接触然后向第一金属层一侧延伸并与所述第一金属层接触的钝化层；它具有工艺控制简单、可靠性高等特点。
Description
技术领域
本发明涉及功率器件的平面终端结构及其制作技术领域，具体涉及一种可变横向掺杂的终端结构及其制作方法。
背景技术
功率器件需要终端结构以避免器件反向阻断时，由于主PN结边缘的球面或者圆柱形区域出现电场集中而造成漏电流大或者提前击穿等现象。特别是600V~6500V等中高压器件如IGBT，FRD和整流二极管，都需要终端结构的优化设计来达到接近平面PN结的击穿电压。通常采用的技术如场限环（field limiting rings）和场板（field plate）和场限环的组合结构，如果需要达到接近平面PN结的击穿电压，因场限环本身不能全部耗尽，所以需要较大的横向面积；工艺过程中形成的氧化层电荷以及大电场容易引起漏电流增加或降低击穿电压，所以需要减小环间距并增加场限环数量或与场板组合使用。
相比上述终端结构，横向面积利用率高并且容易达到接近平面PN结击穿电压的结构为可变横向参杂（Variation in Lateral Doping简称“VLD”结构）技术。VLD结构特点是通过不同开口尺寸注入离子并扩散形成可控并横向渐变的参杂形貌，在器件反向阻断时，可完全耗尽，因而相比场限环结构具有更高的横向尺寸利用率。
发明内容
本发明要解决的技术问题在于，针对现有技术的上述缺陷，提供一种工艺控制简单，且可靠性高的可变横向掺杂的终端结构及其制作方法。
本发明的目的是通过如下技术方案来完成的，一种可变横向掺杂的终端结构，主要包括终端结构本体，所述终端结构本体主要包括N型外延衬底及设置在N型外延衬底顶部外表面上的氧化层，所述N型外延衬底的其中一侧设置有深N阱区，N型外延衬底的另一侧通过P阱注入窗口设置有深P阱掺杂区，所述深P阱掺杂区的面积大于所述深N阱区的面积；所述深P阱掺杂区的上表面设置有第一金属层，所述深N阱区的上表面设置有与所述第一金属层高度对应的第二金属层，且所述第二金属层的宽度小于所述第一金属层的宽度，第二金属层的顶部设置有与所述氧化层的顶部接触然后向第一金属层一侧延伸并与所述第一金属层接触的钝化层，所述钝化层的厚度大于所述第一金属层和第二金属层的厚度。
进一步地，所述N型外延衬底包括N-外延层及设置在N-外延层底部的N+衬底层，所述N-外延层的厚度大于所述N+衬底层的厚度，所述N+衬底层的底部设置有背面金属层。
进一步地，所述氧化层包括半绝缘多晶硅及包覆在所述半绝缘多晶硅上表面上的氧化硅。
一种可变横向掺杂的终端结构的制作方法，所述制作方法主要包括如下步骤：
（1）在选定的N型外延衬底或区熔片或MCZ或带有背面扩散层的圆片上定义有源区和终端区，生长场区氧化层；
（2）根据终端结构的设计，选择性的制作深N阱，形成场截止环；
（3）根据器件电压等级，在终端区，从有源区到场截止环方向，通过光刻或者刻蚀氧化层来形成宽度逐渐变窄、间距逐渐变大的P型杂质注入窗口，二极管有源区可以选择性的定义注入VLD P杂质，并通过高温扩散形成往截止环方向逐渐变浅的PN结；
（4）在终端区域，刻蚀并完全清除硅表面的氧化层或者进一步刻蚀硅表面0.05um~0.5um，然后淀积半绝缘多晶硅和氮化硅并退火致密，形成终端结构特殊钝化层；
（5）完成器件有源区所需的其他工艺步骤，最后淀积钝化层，完成顶层结构的制作；
（6）将硅片背面减薄到特定的厚度，并根据器件要求形成背面电极。
进一步地，步骤（3）中，所述P型杂质注入窗口的宽度变化范围为2um~100um，间距变化范围为1um~10um；所述VLD P杂质为硼离子，且VLD P杂质的注入剂量选择范围为1.E12到 5E12cm-2；经过高温扩散形成深度为10~20um的PN结。
进一步地，步骤（5）中，所述钝化层由氧化硅、氮化硅或聚酰亚胺中的其中一种材料制作而成。
进一步地，该制作方法可用于全电压等级的IGBT以及FRD器件的有源区外围的终端结构或者成为有源区。
本发明的有益技术效果在于：本发明所述的可变横向掺杂的终端结构及其制作方法制作工艺控制简单，与通用的集成电路以及IGBT和二极管工艺兼容，并且利用较小的横向尺寸就可以实现高可靠性的终端结构。
附图说明
图1为深N阱的光刻以及离子注入示意图；
图2为终端区VLD P阱的定义示意图；
图3为终端区VLD P阱的扩散结示意图；
图4为SIPOS以及金属的定义示意图；
图5为钝化层的定义示意图；
图6为二极管器件结构图示意图；
图7为IGBT器件结构图；
图8为 VLD结构扩散结深变化规律图。
具体实施方式
为使本领域的普通技术人员更加清楚地理解本发明的目的、技术方案和优点，以下结合附图和实施例对本发明做进一步的阐述。
在本发明的描述中，需要理解的是，“上”、“下”、“左”、“右”、“内”、“外”、“横向”、“竖向”等术语所指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明，而不是指示或暗示所指的装置或原件必须具有特定的方位，因此不能理解为对本发明的限制。
如图1-8所示，本发明所述的一种可变横向掺杂的终端结构，主要包括终端结构本体1，所述终端结构本体1主要包括N型外延衬底及设置在N型外延衬底顶部外表面上的氧化层，所述N型外延衬底的其中一侧设置有深N阱区2，N型外延衬底的另一侧通过P阱注入窗口设置有深P阱掺杂区3，所述深P阱掺杂区3的面积大于所述深N阱区2的面积；所述深P阱掺杂区3的上表面设置有第一金属层4，所述深N阱区2的上表面设置有与所述第一金属层4高度对应的第二金属层5，且所述第二金属层5的宽度小于所述第一金属层4的宽度，第二金属层5的顶部设置有与所述氧化层的顶部接触然后向第一金属层4一侧延伸并与所述第一金属层4接触的钝化层6，所述钝化层6的厚度大于所述第一金属4层和第二金属层5的厚度。
参照图5所示，所述N型外延衬底包括N-外延层7及设置在N-外延层7底部的N+衬底层8，所述N-外延层7的厚度大于所述N+衬底层8的厚度，所述N+衬底层8的底部设置有背面金属层，所述氧化层包括半绝缘多晶硅9及包覆在所述半绝缘多晶硅9上表面上的氧化硅10。
一种可变横向掺杂的终端结构的制作方法，所述制作方法主要包括如下步骤：
（1）在选定的N型外延衬底或区熔片或MCZ或带有背面扩散层的圆片上定义有源区和终端区，生长场区氧化层；
（2）根据终端结构的设计，选择性的制作深N阱，形成场截止环；
（3）根据器件电压等级，在终端区，从有源区到场截止环方向，通过光刻或者刻蚀氧化层来形成宽度逐渐变窄、间距逐渐变大的P型杂质注入窗口，P型杂质注入窗口的宽度变化范围为2um~100um，间距变化范围为1um~10um；二极管有源区可以选择性的定义注入VLD P杂质，VLD P杂质为硼离子，且VLD P杂质的注入剂量选择范围为1.E12 到 5E12cm-2,并通过高温扩散形成往截止环方向逐渐变浅的PN结；
（4）在终端区域，刻蚀并完全清除硅表面的氧化层或者进一步刻蚀硅表面0.05um~0.5um，然后淀积半绝缘多晶硅（SIPOS）和氮化硅等绝缘材料并退火致密，形成终端结构的特殊钝化层；绝缘材料上覆盖通用的钝化层，如氧化层或碳化硅或聚酰亚胺或组合使用上述保护材料等；
（5）完成器件有源区所需的其他工艺步骤，最后淀积钝化层，完成顶层结构的制作；
（6）将硅片背面减薄到特定的厚度，并根据器件要求形成背面电极。
该制作方法可用于全电压等级的IGBT以及FRD器件的有源区外围的终端结构或者成为有源区。
本文中所描述的具体实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，但凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。
Claims (7)
1.一种可变横向掺杂的终端结构，主要包括终端结构本体，其特征在于：所述终端结构本体主要包括N型外延衬底及设置在N型外延衬底顶部外表面上的氧化层，所述N型外延衬底的其中一侧设置有深N阱区，N型外延衬底的另一侧通过P阱注入窗口设置有深P阱掺杂区，所述深P阱掺杂区的面积大于所述深N阱区的面积；所述深P阱掺杂区的上表面设置有第一金属层，所述深N阱区的上表面设置有与所述第一金属层高度对应的第二金属层，且所述第二金属层的宽度小于所述第一金属层的宽度，第二金属层的顶部设置有与所述氧化层的顶部接触然后向第一金属层一侧延伸并与所述第一金属层接触的钝化层，所述钝化层的厚度大于所述第一金属层和第二金属层的厚度。
2.根据权利要求1所述的可变横向掺杂的终端结构，其特征在于：所述N型外延衬底包括N-外延层及设置在N-外延层底部的N+衬底层，所述N-外延层的厚度大于所述N+衬底层的厚度，所述N+衬底层的底部设置有背面金属层。
3.根据权利要求1或2所述的可变横向掺杂的终端结构，其特征在于：所述氧化层包括半绝缘多晶硅及包覆在所述半绝缘多晶硅上表面上的氧化硅。
4.一种如权利要求3所述可变横向掺杂的终端结构的制作方法，其特征在于：所述制作方法主要包括如下步骤：
（1）在选定的N型外延衬底或区熔片或MCZ或带有背面扩散层的圆片上定义有源区和终端区，生长场区氧化层；
（2）根据终端结构的设计，选择性的制作深N阱，形成场截止环；
（3）根据器件电压等级，在终端区，从有源区到场截止环方向，通过光刻或者刻蚀氧化层来形成宽度逐渐变窄、间距逐渐变大的P型杂质注入窗口，二极管有源区可以选择性的定义注入VLD P杂质，并通过高温扩散形成往截止环方向逐渐变浅的PN结；
（4）在终端区域，刻蚀并完全清除硅表面的氧化层或者进一步刻蚀硅表面0.05um~0.5um，然后淀积半绝缘多晶硅和氮化硅并退火致密，形成终端结构特殊钝化层；
（5）完成器件有源区所需的其他工艺步骤，最后淀积钝化层，完成顶层结构的制作；
（6）将硅片背面减薄到特定的厚度，并根据器件要求形成背面电极。
5.根据权利要求4所述的制作方法，其特征在于：步骤（3）中，所述P型杂质注入窗口的宽度变化范围为2um~100um，间距变化范围为1um~10um；所述VLD P杂质为硼离子，且VLD P杂质的注入剂量选择范围为1.0E12 到 5E12cm-2；经过高温扩散形成深度为10~20um的PN结。
6.根据权利要求4所述的制作方法，其特征在于：步骤（5）中，所述钝化层由氧化硅、氮化硅或聚酰亚胺中的其中一种材料制作而成。
7.根据权利要求4所述的制作方法，其特征在于：该制作方法可用于全电压等级的IGBT以及FRD器件的有源区外围的终端结构或者成为有源区。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010662037.6A CN111755503A (zh) | 2020-07-10 | 2020-07-10 | 一种可变横向掺杂的终端结构及其制作方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010662037.6A CN111755503A (zh) | 2020-07-10 | 2020-07-10 | 一种可变横向掺杂的终端结构及其制作方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111755503A true CN111755503A (zh) | 2020-10-09 |
Family
ID=72711156
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010662037.6A Pending CN111755503A (zh) | 2020-07-10 | 2020-07-10 | 一种可变横向掺杂的终端结构及其制作方法 |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111755503A (zh) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112271210A (zh) * | 2020-10-22 | 2021-01-26 | 吉林华微电子股份有限公司 | 半导体功率及其制作方法 |
| CN112420812A (zh) * | 2020-11-18 | 2021-02-26 | 华北电力大学 | 一种高压功率芯片的深结复合终端结构及其制备方法 |
| CN113314599A (zh) * | 2021-06-22 | 2021-08-27 | 珠海市浩辰半导体有限公司 | 复合终端结构及其制备方法 |
| CN113451137A (zh) * | 2021-06-29 | 2021-09-28 | 深圳铨力半导体有限公司 | 晶体管制造方法、设备、计算机可读存储介质与程序产品 |
| CN113658996A (zh) * | 2021-08-20 | 2021-11-16 | 电子科技大学 | 一种横向变掺杂终端结构及其设计方法 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108155225A (zh) * | 2017-12-27 | 2018-06-12 | 电子科技大学 | 恒流器件及其制造方法 |
| CN111211175A (zh) * | 2020-03-23 | 2020-05-29 | 上海道之科技有限公司 | 一种快恢复二极管器件结构及其制作方法 |
-
2020
- 2020-07-10 CN CN202010662037.6A patent/CN111755503A/zh active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108155225A (zh) * | 2017-12-27 | 2018-06-12 | 电子科技大学 | 恒流器件及其制造方法 |
| CN111211175A (zh) * | 2020-03-23 | 2020-05-29 | 上海道之科技有限公司 | 一种快恢复二极管器件结构及其制作方法 |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112271210A (zh) * | 2020-10-22 | 2021-01-26 | 吉林华微电子股份有限公司 | 半导体功率及其制作方法 |
| CN112420812A (zh) * | 2020-11-18 | 2021-02-26 | 华北电力大学 | 一种高压功率芯片的深结复合终端结构及其制备方法 |
| CN113314599A (zh) * | 2021-06-22 | 2021-08-27 | 珠海市浩辰半导体有限公司 | 复合终端结构及其制备方法 |
| CN113451137A (zh) * | 2021-06-29 | 2021-09-28 | 深圳铨力半导体有限公司 | 晶体管制造方法、设备、计算机可读存储介质与程序产品 |
| CN113658996A (zh) * | 2021-08-20 | 2021-11-16 | 电子科技大学 | 一种横向变掺杂终端结构及其设计方法 |
| CN113658996B (zh) * | 2021-08-20 | 2023-09-29 | 电子科技大学 | 一种横向变掺杂终端结构及其设计方法 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111755503A (zh) | 一种可变横向掺杂的终端结构及其制作方法 | |
| EP0632503B1 (en) | Integrated edge structure for high voltage semiconductor devices and related manufacturing process | |
| JP3413250B2 (ja) | 半導体装置及びその製造方法 | |
| CN111602250B (zh) | 具有用于场截止和反向传导的三维背侧结构的igbt器件 | |
| US20240055484A1 (en) | Field stop igbt with grown injection region | |
| TW201904057A (zh) | Lv/mv超級結溝槽功率mosfet元件及其製備方法 | |
| US8907351B2 (en) | Bipolar junction transistor in silicon carbide with improved breakdown voltage | |
| US20160240608A1 (en) | Field-stop reverse conducting insulated gate bipolar transistor and manufacturing method therefor | |
| EP2341528A1 (en) | Power Semiconductor Device and its manufacturing method | |
| CN110419111B (zh) | 自对准且稳健的绝缘栅双极晶体管器件 | |
| US5923065A (en) | Power MOSFET device manufactured with simplified fabrication processes to achieve improved ruggedness and product cost savings | |
| CN111341832B (zh) | 结终端结构及其制备方法 | |
| US20180019348A1 (en) | High Speed Schottky Rectifier | |
| CN111164759B (zh) | 具有高电流容量的馈线设计 | |
| CN113990945B (zh) | 一种绝缘栅双极型晶体管结构及其制造方法 | |
| CN113345954A (zh) | 一种全超结mosfet器件结构及其制造方法 | |
| CN113471301A (zh) | 一种沟槽肖特基二极管及其制备方法 | |
| CN110931548A (zh) | 一种半导体器件结构及其制造方法 | |
| US20220013625A1 (en) | Vertical power semiconductor device and manufacturing method | |
| CN215342615U (zh) | 一种全超结mosfet器件结构 | |
| CN203260588U (zh) | 一种功率mosfet的沟槽终端结构 | |
| CN116613217B (zh) | 一种抑制表面漏电流的肖特基势垒二极管 | |
| CN103117308A (zh) | 一种沟槽mosfet功率整流器件及其制造方法 | |
| JPH10335630A (ja) | 半導体装置及びその製造方法 | |
| CN107946352B (zh) | 一种欧姆接触和肖特基接触超级势垒整流器及其制作方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |