CN111751707A

CN111751707A - Test circuit and chip

Info

Publication number: CN111751707A
Application number: CN202010600867.6A
Authority: CN
Inventors: 杜占坤; 吕循洪
Original assignee: Xinbai Microelectronic Beijing Co ltd
Current assignee: Xinbai Microelectronic Beijing Co ltd
Priority date: 2020-06-28
Filing date: 2020-06-28
Publication date: 2020-10-09
Anticipated expiration: 2040-06-28
Also published as: CN111751707B

Abstract

The invention discloses a test circuit and a chip, wherein the test circuit comprises a system unit and a test unit; the control module sends test information to the transmission module through the transceiving module; the processing module receives the test information through the transmission module, calls the component library module and the logic library module to generate an analog circuit, calls the test module to test the analog circuit to obtain a simulation test result, and feeds the simulation test result back to the control module through the transmission module; and when the simulation test result is determined to be normal, connecting the chip to be tested through the test circuit, and testing the chip according to the test information. The chip to be tested is connected with the test circuit through the control module, the universality of chip testing is promoted in a matching mode, the simulation circuit is generated in a matching mode, and simulation can be performed before testing, so that the chip is protected before testing, the chip is prevented from being damaged due to testing, and the test information can be used for performing independent testing on the special structure or the function of the chip.

Description

Test circuit and chip

Technical Field

The invention relates to the field of chips, in particular to a test circuit and a chip.

Background

With the development of technology, chip application is ubiquitous, and many supports are provided for smart life and work, but chip testing is a relatively big problem, and it directly runs through the whole chip design and mass production process, and it requires one, two or more tests, especially Wafer testing, whether Wafer testing after Wafer flow (Wafer Test), Final testing after packaging (Final Test, also called packaging Test) or Final system level testing, and its Test objects are a large number of chips on the Wafer, these chips are dies (Die), they may be the same or different, the dies do not have packaged pins (Pin), i.e. pins seen by the Final user, only the silicon Wafer (Pad) finally packaged inside the chips, and the pins between Pad and Pin are connected through wires in the packaging stage, for example, by gold wire connection, and a complete Chip (Chip) is obtained after packaging.

Therefore, wafer testing is an important basis for the subsequent testing steps, but has great significance for chip quality control no matter package testing or system level testing.

Chinese patent with application time of 2015 and publication number CN105207657A discloses a circuit for entering a chip test mode by using a negative voltage, wherein a source of a switching tube M0 is connected to a power supply VDD, a drain of the switching tube M0 is connected to a chip pin P1 and a drain of the switching tube M1, a gate of the switching tube M0 is connected to a resistor RO, a gate of a switching tube M1, a gate of the switching tube M2, and a gate of the switching tube M3, the other end of the resistor RO is grounded, a source of the switching tube M3 is connected to the power supply VDD, a source of the switching tube M1 is connected to a source of a switching tube M2 and an input B of a not gate I9, an input a of the not gate I9 is connected to an ON pin of a flip-flop DFF5, and a CP pin of the flip-flop DFF5 is connected to. The invention provides a circuit which can multiplex an I/O pin and can enter a test mode only by applying negative voltage in a matching way, and under the condition that the process does not have nonvolatile storage, the circuit still can have a plurality of state modes after the chip is packaged, and the normal application of a client is not influenced.

Chinese patent with application time of 2016 and publication number of CN106407556A discloses a method for manufacturing an integrated chip, comprising: decomposing the target device into N first small devices; connecting the target device and the M second small devices in series or in parallel; whether the first small device or the second small device is connected is controlled by the on-off of the two MOS tubes; connecting the output end of the decoder with first grids in two MOS tubes, and connecting second grids in the two MOS tubes with a control port; the output end of the decoder is controlled to output different level signals by applying different levels to the input port of the decoder, the on-off of the MOS tube is controlled to control the access of each first small device or each second small device to adjust the size of the target device, and the final size of the target device is determined; and when the chip is packaged, fixing the electric potential of the port according to the level of the port corresponding to the final size. By the technical scheme, the technical problems of low debugging efficiency and increased development cost of the integrated chip in the prior art are solved.

Chinese patent with application time of 2018 and publication number CN111123066A discloses a chip test circuit, a memory and a wafer, and the chip test circuit provided by the embodiment of the disclosure includes: a test signal interface for receiving a test signal; one end of the first electrostatic protection circuit is connected with the test signal interface; and a first input end of the signal selection circuit is connected with the other end of the first electrostatic protection circuit, a second input end of the signal selection circuit is used for receiving a working signal, a control end of the signal selection circuit is used for receiving a characteristic signal related to the test signal, and an output end of the signal selection circuit is used for outputting the test signal or the working signal to a chip to be tested. The chip test circuit provided by the disclosed embodiment can obtain a test result which is closer to the normal working state of a chip, improves the reliability of the test result of the chip, and further can improve the yield in the production and processing of the chip.

That is, all tests must be based on chips, whether the chips are packaged on a wafer or a chip, but all tests have the problems of strong specificity and weak universality, lack of strong versatility, lack of independent important tests for special structures or functions, and lack of protection for chips before testing.

Disclosure of Invention

The invention provides a test circuit and a chip, and aims to solve the technical problems that: how to promote the versatility of chip testing, perform individual testing for specific structures or functions, protect chips from damage due to testing before testing, etc.

The technical scheme of the invention is as follows:

a test circuit includes a system unit and a test unit;

the system unit comprises a component library module, a logic library module, a processing module, a test module and a transmission module; the processing module is respectively connected with the component library module, the logic library module, the test module and the transmission module;

the test unit comprises a control module, a judgment module, a transceiver module and a test circuit, wherein the control module is respectively connected with the judgment module and the transceiver module, and the control module receives test information through the transceiver module;

the control module is connected with the transmission module through the test line and sends the test information to the transmission module through the transceiving module; the processing module receives the test information through the transmission module, calls the component library module and the logic library module to generate an analog circuit, calls the test module to test the analog circuit to obtain a simulation test result, and feeds the simulation test result back to the control module through the transmission module;

and the control module is also used for connecting a chip to be tested through the test circuit when the judgment module determines that the simulation test result is normal, and testing the chip according to the test information.

Preferably, the system unit further comprises a display module, the display module is connected to the processing module, and the display module is used for displaying the analog circuit and the analog test result; and/or the system unit further comprises a storage module, the storage module is connected with the processing module, and the storage module is used for storing the analog circuit and the analog test result.

Preferably, the test circuit further comprises a module unit, wherein the module unit comprises at least two groups of functional modules and connecting terminals thereof; the control module is further configured to generate at least one test signal of the functional module according to the test information when the judgment module determines that the simulation test result is normal, gate the connection terminal of the at least one functional module through the test line, send the test signal to the matched functional module through the transceiver module, and call the functional module to perform at least one functional test on the chip according to the test signal.

Preferably, at least one group of the functional modules is provided with components and connections thereof according to the structure of the chip.

Preferably, at least one group of the functional modules is provided with components and connections thereof according to a specific functional structure of the chip.

Preferably, the test circuit comprises a gating switch and at least two test branches connected with the gating switch, and each test branch is connected with one of the connection terminals in a matching manner; the control module is connected with each test branch circuit through the gating switch.

Preferably, the test unit further includes an interface circuit, the interface circuit is used for connecting to the plurality of chips, respectively, and the control module is further connected to the interface circuit through the test line.

Preferably, the test circuit further comprises a database, and the database is connected with the judgment module.

Preferably, the database is also connected with database clouds of other test circuits.

A chip implemented using the test circuit of any one of the above; or it may have a test process using the test circuit described in any of the above.

By adopting the scheme, the chip to be tested is connected with the control module through the test circuit, the universality of chip testing is improved by matching with the system unit, the simulation circuit is generated by matching the component library and the logic library with the processing module and can be simulated before testing, so that the chip is protected before testing, the damage to the chip caused by testing is avoided, and the test information can be used for independently testing the special structure or function of the chip, so that the chip testing device has high market application value.

Drawings

FIG. 1 is a schematic diagram of one embodiment of a test circuit of the present invention;

FIG. 2 is a schematic diagram of another embodiment of a test circuit of the present invention;

FIG. 3 is a schematic diagram of another embodiment of a test circuit of the present invention;

FIG. 4 is a schematic diagram of another embodiment of a test circuit of the present invention.

Detailed Description

In order to facilitate an understanding of the invention, the invention is described in more detail below with reference to the accompanying drawings and specific examples. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

One embodiment of the present invention is a test circuit including a system unit and a test unit; the system unit comprises a component library module, a logic library module, a processing module, a test module and a transmission module; the processing module is respectively connected with the component library module, the logic library module, the test module and the transmission module; the test unit comprises a control module, a judgment module, a transceiver module and a test circuit, wherein the control module is respectively connected with the judgment module and the transceiver module, and the control module receives test information through the transceiver module; the control module is connected with the transmission module through the test line and sends the test information to the transmission module through the transceiving module; the processing module receives the test information through the transmission module, calls the component library module and the logic library module to generate an analog circuit, calls the test module to test the analog circuit to obtain a simulation test result, and feeds the simulation test result back to the control module through the transmission module; and the control module is also used for connecting a chip to be tested through the test circuit when the judgment module determines that the simulation test result is normal, and testing the chip according to the test information. By adopting the scheme, the chip to be tested is connected with the control module through the test circuit, the universality of chip testing is improved by matching with the system unit, the simulation circuit is generated by matching the component library and the logic library with the processing module and can be simulated before testing, so that the chip is protected before testing, the damage to the chip caused by testing is avoided, and the test information can be used for independently testing the special structure or function of the chip, so that the chip testing device has high market application value.

Preferably, the test circuit comprises a system unit and a test unit; the system unit is used for carrying out simulation test according to the test information and providing a simulation test result; the test unit is used for controlling the system unit to perform simulation test according to the test information to obtain a simulation test result of the system unit, and testing the chip to be tested according to the test information when the simulation test result is normal. Therefore, simulation can be performed before testing, and damage to a large number of chips caused by testing errors is avoided.

Preferably, the system unit comprises a component library module, a logic library module, a processing module, a testing module and a transmission module; the processing module is respectively connected with the component library module, the logic library module, the test module and the transmission module; the component library module is used for storing component information, the logic library module is used for storing logic information, and the logic information comprises connection logic, test logic, control logic, judgment logic, abnormal logic and the like. The processing module can be realized by a microprocessor such as an MCU. The test module is used for carrying out simulation test according to the simulation circuit provided by the processing module. Preferably, the component library module, the logic library module and the test module are all software modules. Preferably, the transmission module may be a virtual port, an entity port, or data transmission hardware. The transmission module receives test information of a test unit or outside and transmits the test information to the processing module, the processing module calls the component library module and the logic library module to generate an analog circuit according to the test information, the processing module calls the test module to test the analog circuit to obtain a simulation test result, and the processing module feeds the simulation test result back to the test unit through the transmission module.

Preferably, the test unit comprises a control module, a judgment module, a transceiver module and a test circuit, the control module is respectively connected with the judgment module and the transceiver module, and the control module receives test information through the transceiver module; the receiving and sending module receives test information and transmits the test information to the control module; when the control module determines that the simulation test is needed, the control module sends the test information to the transmission module through the transceiving module; and the control module obtains a simulation test result from the transmission module through the transceiver module, and then the control module judges whether the simulation test result is normal through the judgment module, if so, the test can be started on the chip to be tested, wherein the test is usually large-scale batch operation, and can be single-thread, namely one chip tests in turn, or multi-thread, namely a plurality of chips are taken as a group, and simultaneously one group of chips is tested, and each group of chips tests in a round-robin manner. Therefore, the test risk can be controlled, and the chips are prevented from being damaged in batches.

Preferably, the control module is connected to the transmission module through the test line, and sends the test information to the transmission module through the transceiver module; the processing module receives the test information through the transmission module, calls the component library module and the logic library module to generate an analog circuit, calls the test module to test the analog circuit to obtain a simulation test result, and feeds the simulation test result back to the control module through the transmission module; preferably, the control module is further configured to connect a chip to be tested through the test line when the judgment module determines that the simulation test result is normal, and test the chip according to the test information. The control module can adopt a MCU or a plurality of existing chips. Preferably, the number of the test lines is plural; the test circuit can be a section of conducting wire, a switch circuit and the like. It should be noted that the control module is connected to the transmission module through the test line, and is connected to the chip to be tested through the test line, where the test lines are different, that is, two test lines, for example, two segments of wires insulated from each other, and so on in other embodiments, and details are not repeated below. During actual testing, by designing or regulating the test information, the chip can be completely tested, and the chip can also be separately tested for special structures or functions, for example, one chip only tests one part of the chips, so that high-speed testing and rapid delivery are realized when necessary; the method is particularly suitable for chips which are produced in large quantity, have no historical faults in part functions and only need to test some specific positions or specific structures or specific functions.

Preferably, the test circuit further comprises a module unit, wherein the module unit comprises at least two groups of functional modules and connecting terminals thereof; the control module is further configured to generate at least one test signal of the functional module according to the test information when the judgment module determines that the simulation test result is normal, gate the connection terminal of the at least one functional module through the test line, send the test signal to the matched functional module through the transceiver module, and call the functional module to perform at least one functional test on the chip according to the test signal. That is to say, the judging module judges whether the simulation test result is normal, if so, the judging module notifies the control module, the control module generates a test signal according to the test information, the test signal matches at least one of the functional modules, for the functional module matched with the test signal, the control module gates the connecting terminals of the functional modules through the test line, at this time, the control module communicates the functional modules through the transceiving module, the test line and the connecting terminals, and the control module sends the test signal to the related functional module through the transceiving module. Preferably, the control module is further configured to establish a logical association for at least two of the functional modules matched with the test signal when the test signal is matched with at least two of the functional modules, sequentially call each of the functional modules according to the logical association, and sequentially perform an association test of at least two functions on the chip according to the test signal. Therefore, the combined test of a plurality of related functions can be realized, the test efficiency is improved, and the accurate related function test can be realized. Preferably, at least one group of the functional modules is provided with components and connections thereof according to the structure of the chip. Preferably, at least one group of the functional modules is provided with components and connections thereof according to a specific functional structure of the chip. Preferably, the module unit is configured to set a fully-matched full-function module according to the chip, that is, to set a plurality of groups of function modules, which are configured to correspond to the function structures of the chip to be tested one to one. Therefore, the matched functional modules can be customized according to the needs, and the chip is particularly suitable for chips which are rapidly developed and changed, namely, if the chip is not changed greatly, the functional modules can be unchanged for a long time, and if the industry is rapidly developed and the technology change is large, the functional modules can be changed to realize accurate functional test; if necessary, the method can also perform full-function matching test, ensure the nondestructive test of the important chip to be tested as far as possible, and is particularly suitable for important sample wafers. Preferably, the test circuit comprises a gating switch and at least two test branches connected with the gating switch, and each test branch is connected with one of the connection terminals in a matching manner; the control module is connected with each test branch circuit through the gating switch. In this way, control of connection or disconnection of more branches can be realized, thereby enabling measurement of a plurality of chips at a time. Preferably, the test unit further includes an interface circuit, the interface circuit is used for connecting to the plurality of chips, respectively, and the control module is further connected to the interface circuit through the test line. Preferably, the interface circuit is used for alternately connecting a plurality of chips in a signal sequence electrifying mode, so that the control module can respectively test the plurality of chips at time intervals through one test line, and the test efficiency is improved. In order to facilitate the function simulation test before the formal test and avoid the chip damage caused by the test, preferably, the control module further generates a test signal according to the test information, the control module gates at least one connection terminal through the test line, sends the test signal through the transceiver module, performs the function test according to the test signal by the function module corresponding to the gated connection terminal to obtain a function test result, and feeds the function test result back to the control module; and the control module is also used for connecting a chip to be tested through the test circuit when the judging module determines that the simulation test result and the function test result are both normal, and testing the chip according to the test information. Therefore, the software simulation test and the hardware function test before the formal test can be realized, and the hardware function test can be a complete hardware function test or a partial hardware function test.

Preferably, as shown in fig. 1, a test circuit includes a system unit, a module unit and a test unit; the system unit comprises a component library module, a logic library module, a processing module, a test module and a transmission module; the processing module is respectively connected with the component library module, the logic library module, the test module and the transmission module; the module unit includes at least two groups of functional modules and their connection terminals, which are represented as a functional module N and its connection terminal N for convenience of illustration, where N is a natural number greater than or equal to 2, for example, the functional module 1 and its connection terminal 1, the functional module 2 and its connection terminal 2, and so on in other embodiments, and details are not described below. Each functional module is mutually independent and can be partially or completely connected when necessary; the test unit comprises a control module, a judgment module, a transceiver module and a test circuit, wherein the control module is respectively connected with the judgment module and the transceiver module, and the control module receives test information through the transceiver module; the control module is connected with the transmission module through the test line and sends the test information to the transmission module through the transceiving module; the processing module receives the test information through the transmission module, calls the component library module and the logic library module to generate an analog circuit, calls the test module to test the analog circuit to obtain a simulation test result, and feeds the simulation test result back to the control module through the transmission module; and the control module is also used for connecting a chip to be tested through the test circuit when the judgment module determines that the simulation test result is normal, and testing the chip according to the test information. The control module is further configured to generate at least one test signal of the functional module according to the test information when the judgment module determines that the simulation test result is normal, gate the connection terminal of the at least one functional module through the test line, send the test signal to the matched functional module through the transceiver module, and call the functional module to perform at least one functional test on the chip according to the test signal. As can be seen from fig. 1, when there is only one chip to be tested, the number of test lines is N +3 or N + 4. Other embodiments are analogized and will not be described in detail below.

Preferably, the system unit further comprises a display module, the display module is connected to the processing module, and the display module is used for displaying the analog circuit and the analog test result; as shown in fig. 2, the processing module is also connected to the display module. Preferably, the display module may be a display screen or other display terminal. Preferably, the system unit further includes a storage module, the storage module is connected to the processing module, and the storage module is configured to store the analog circuit and the analog test result. Preferably, the storage module is a nonvolatile memory. As shown in fig. 3, the processing module is also connected to the storage module. Or, preferably, the system unit further includes a display module, the display module is connected to the processing module, and the display module is configured to display the analog circuit and the analog test result; the system unit further comprises a storage module, the storage module is connected with the processing module, and the storage module is used for storing the analog circuit and the analog test result. As shown in fig. 4, the processing module is further connected to the display module and the storage module, respectively.

In order to make a faster and more accurate determination, it is preferable that the test circuit further includes a database, and the database is connected to the determination module. The database may be implemented using various prior art techniques, which are not described in detail herein. In order to improve the applicability of the database and fully utilize the advantages of the current big data network, preferably, the database is also connected with database clouds of other test circuits. In this way, a cloud database can be realized, and one test center can share the database of a plurality of test factories or laboratories in distributed arrangement.

In order to facilitate the improvement of the universality of chip testing on a wafer or before packaging during testing, the test circuit or the test unit also comprises a chip detection structure, and the chip detection structure comprises a support body, a circuit board, a probe seat and at least two probe sheets; the control module is connected with a circuit or a connection port of the circuit board through the test circuit, the support body is used for being fixed outside, the circuit board is fixedly arranged on the support body, and the probe seat is arranged on the support body; the probe sheet is provided with a plurality of probes which are arranged in an insulated manner, the probe seat is provided with at least two probe hole groups, each probe hole group corresponds to one probe sheet and is provided with probe holes which are insulated from each other, a conductive connecting end is filled in each probe hole, and the conductive connecting end is connected with the circuit of the circuit board through a lead; the probe seat is detachably provided with the probe sheet, two ends of each probe in the probe sheet protrude out of the probe sheet, the first end of each probe is vacant, and the second end of each probe is inserted into one probe hole and is in conductive connection with the conductive connecting end in the probe hole. Like this, can be through designing a probe seat of a plurality of probe piece sharing, the chip of multiple different designs on to a great extent adaptation wafer or before the encapsulation need not all newly design special probe card at every turn to promote the commonality of chip detection structure, circuit board and probe seat are also changeable moreover, so whole flexibility ratio is very high, can practice thrift test cost and promote efficiency of software testing. Preferably, the probe seat is arranged on the circuit board and arranged on the support body through the circuit board. Preferably, the support body is provided with a plurality of mounting portions, and the support body is fixed to the outside through the mounting portions, so that the chip detection structure is fixed. In practical applications, the chip detection structure may further include at least one of a voltage input structure, a current input structure, a voltage detection structure, a current detection structure, and an imaging structure. Preferably, the probe sheets have probes arranged in a matrix and insulated from each other, at least one of a row pitch and a column pitch of the matrix of each probe sheet being arranged differently from the matrix of the other probe sheets; each probe hole group is matched with one probe sheet and is provided with probe holes which are arranged in a matrix and are mutually insulated. Preferably, the probe may be in the shape or structure of an existing probe, or may be adjustable. To facilitate the detection, preferably, the probe has a widened end that matches the Pad. Preferably, the second end of the probe is in contact with the conductive connection end in the probe hole; preferably, the first end of the probe has a widened end portion that matches the Pad. Preferably, the second end of the probe has an expansion part and the probe hole is provided with an elastic conductive structure body matched with the expansion part, and the elastic conductive structure body is in conductive connection with the conductive connecting end in the probe hole. Preferably, the elastic conductive structure is in contact with the conductive connection terminal in the probe hole. Preferably, the elastic conductive structure and the conductive connecting end are integrally arranged. Preferably, the elastic conductive structure is a spring piece and is inserted into the slot of the conductive connecting end in an interference fit manner. In order to enhance the protection of the chip to be tested, especially the Pad portion, it is preferable that the probe sheet has pogo pins matched with the probes, and the second ends of the probes are inserted into one of the probe holes through the pogo pins and are conductively connected to the conductive connection terminals in the probe holes. That is, the pogo pin is inserted into one of the probe holes and is conductively connected to the conductive connection in the probe hole. Therefore, the elastic protection of the Pad can be realized to a certain degree, the probe can also be protected to a certain degree, and the damage of the probe, the Pad or the chip caused by misoperation is avoided. In order to protect the chip or Pad thereof, the conductive connecting end is filled in the probe hole through an elastic piece.

In order to facilitate the installation and replacement of the probe sheet, preferably, the probe seat is provided with a needle seat body, a buckling part and a pair of slide rails; the needle seat body is arranged on the support body and provided with at least two probe hole groups, and the buckling part is fixedly arranged on the needle seat body; and the probe piece is arranged in the pair of slide rails in a sliding manner and is used for being fixed on the needle seat body through the buckling part when sliding to a preset position. Preferably, the probe seat is further provided with at least four elastic telescopic parts, and each elastic telescopic part is fixedly arranged on the needle seat body respectively; each slide rail is arranged on the needle seat body through at least two elastic telescopic parts. Preferably, the height of the elastic expansion part is greater than the distance from the first end of the probe to the probe sheet. Like this, can realize quick dismantlement or installation probe piece, especially let the probe piece slide to probe punch combination assorted position with the slide rail, thereby make each probe on the probe piece can aim at a probe punch combination on the probe seat earlier, thereby the relative probe punch combination of probe has certain distance can avoid influencing probe piece and slide when the flexible portion helps the probe piece to slide again, then it makes the contact of the conductive connection end in probe and the probe hole realize electrically conductive to press down the flexible portion, last buckle portion is fixed, dismantle otherwise just can, it is all very convenient to dismantle or install, and guarantee the conductive connection end in probe and the probe hole and firmly electrically conductively connect. In order to reduce the volume of the probe seat, namely relative to the area of the chip to be detected, at least two probe hole groups are preferably arranged in a partially overlapped mode. That is, at least two of the probe hole sets have overlapping regions on the probe holder. Preferably, at least two of said sets of probe holes share a portion of said probe holes. That is, at least one of the probe holes belongs to at least two of the probe hole groups simultaneously. For example, three probe-well groups share one, two or more of the probe-wells. In order to facilitate positioning and aligning the detected chip, preferably, the probe seat or the probe sheet is provided with at least three positioning holes; preferably, each of said locating holes forms an apex of at least one triangle. Preferably, the probe seat or the probe sheet is provided with at least three positioning holes; the second end of the probe is in contact with the conductive connecting end in the probe hole; the conductive connecting end is filled in the probe hole through an elastic piece.

In order to facilitate accurate positioning of a wafer during testing and improve the universality of chip testing on the wafer, the test circuit further comprises at least one chip testing positioning structure; the chip testing and positioning structure comprises an active structure and a fixed structure; a wafer placing area and a gap area are formed between the active structure and the fixed structure, the gap area is located outside the wafer placing area, the wafer placing area is used for placing a wafer with chips to be tested and enabling the surface to be tested of the chips to be tested to face a probe card, and the probe card can be the probe sheet or the probe sheet and the probe seat; the fixed structure is fixedly arranged, and the active structure is movably arranged relative to the fixed structure and is used for adjusting the size of the wafer placing area; the wafer placing area is provided with a first arc-shaped edge, the wafer placing area is provided with a second arc-shaped edge, the first arc-shaped edge and the second arc-shaped edge jointly enclose the wafer placing area, the chip testing and positioning structure is provided with at least three abutting columns at the first arc-shaped edge and the second arc-shaped edge respectively, and each abutting column is used for abutting against an edge vacancy of the wafer to jointly fix the wafer. The wafer can be positioned by adopting one chip testing and positioning structure to test the chip, and a plurality of wafers can be positioned by adopting a plurality of chip testing and positioning structures to test the chip, so that the testing efficiency can be improved by realizing expandable positioning, the wafer testing and positioning structure can also be applied to wafers of various specifications, the applicability of a product is improved, the support columns are abutted against the edge vacancy of the wafer, and the wafers are jointly fixed by the support columns, the nondestructive positioning is realized, and the two sides of the wafer can be simultaneously tested when necessary. In order to solve the technical problem of positioning and fixing the wafer, preferably, the pillars include a first pillar and a second pillar; the driving structure comprises a driving body, a driving structure and at least one sliding assembly; the driving body is provided with a first arc-shaped edge and at least three first support columns; the sliding assembly comprises a sliding rail and a sliding part which are matched, the driving structure is connected with the driving body, the sliding part is fixed on the driving body, and the driving structure is used for driving the driving body to slide on the sliding rail through the sliding part; the fixing structure comprises a fixing body and at least three fixing parts, wherein the fixing body is provided with a second arc-shaped edge and at least three second support columns; each fixing part is fixedly connected with the fixing body. Thus, it is possible to accurately position the wafer and securely fix the wafer. Preferably, the initiative body matches first support the post and is equipped with first extending structure, each first support the post through one first extending structure connect in the initiative body or first arc edge, fixed body matches the second supports the post and is equipped with second extending structure, each second support the post through one second extending structure connect in fixed body or second arc edge, like this, can realize first support the flexible of post and second support the post, come the specification of different wafers of adaptation, for example 8 cun, 10 cun, 12 cun or the wafer of other specifications, greatly promoted chip test location structure's suitability. Preferably, the chip testing and positioning structure comprises a plurality of wafer target central points located on a preset straight line, the driving body is provided with a first rotating fine tuning structure matched with the first supporting columns, each first supporting column is connected with the driving body or the first arc-shaped edge through one first rotating fine tuning structure, the fixed body is provided with a second rotating fine tuning structure matched with the second support columns, each second support column is connected with the fixed body or the second arc-shaped edge through one second rotating fine tuning structure, the first rotating fine-tuning structure is used for adjusting the extending direction of the matched first supporting column, the second rotating fine-tuning structure is used for adjusting the extending direction of the matched second supporting column, the extending directions of the first support columns and the second support columns are all towards the same wafer target center point. Preferably, each of the first rotation fine-tuning structures and each of the second rotation fine-tuning structures are controlled in a linkage manner, so that the extending directions of each of the first supporting columns and each of the second supporting columns face the same wafer target center point on the preset straight line when the active structure moves. Therefore, fine adjustment of the directions of the first butting column and the second butting column can be realized, so that the specifications of different wafers are adapted, and the force application direction and the force application balance are ensured.

In order to solve the technical problem of avoiding damaging the wafer, preferably, one end of the support column, which is in contact with the edge vacancy, is provided with a flexible deformation structure, and the flexible deformation structure is used for deforming when the stress exceeds a certain degree. Preferably, the support column is provided with a support column body, a support column end, a sleeving part and a flexible deformation sucking disc part, the support column body is fixed on the first arc-shaped edge or the second arc-shaped edge, the support column end is respectively connected with the support column body and the flexible deformation sucking disc part, and the sleeving part is located between the support column end and the flexible deformation sucking disc part. Therefore, stable positioning and effective fixing can be realized, and meanwhile, the wafer or the upper chip is prevented from being damaged. In practical applications, when the chip is small, the edge vacancy may be small, and the pillars may contact the chip if the size of the pillars is too large, so that the pillars are preferably small in size, the pillars can be made very small in use, and the flexible deformation structure helps to avoid damaging the wafer. In order to facilitate the solution of the technical problems of simplified process and easy assembly, preferably, the fixing structure includes two fixing sets, each fixing set includes two fixing portions, and the two fixing sets are symmetrically arranged. Therefore, the fixing structure of the chip testing and positioning structure can be quickly positioned and accurately installed. In order to facilitate the solution of the technical problem of adapting to the wafer with a large specification change, preferably, the active structure further includes a first gap adjustment member, and the active body includes a first adjustment body and a second adjustment body, the first adjustment body and the second adjustment body respectively have the first arc-shaped edge and at least three parts of the first support columns, a first variable gap region is provided between the first adjustment body and the second adjustment body, and the first gap adjustment member is configured to adjust the first variable gap region to change the relative position of the first adjustment body and the second adjustment body. In order to better cooperate with the wafer with a large specification variation, preferably, the fixing structure further includes a second gap adjustment member, and the fixing body includes a third adjustment body and a fourth adjustment body, the third adjustment body and the fourth adjustment body respectively have the second arc-shaped edge and at least a part of the three second support posts, a second variable gap region is provided between the third adjustment body and the fourth adjustment body, and the second gap adjustment member is configured to adjust the second variable gap region to change a relative position of the third adjustment body and the fourth adjustment body. Thus, the wafer application effect under the condition that different specifications of a large number of different batches, particularly large differences, can be realized.

In order to solve the technical problem of accurately testing each chip in the wafer, preferably, the chip testing positioning structure further comprises a support, and the support is arranged on one side of the wafer placing area, which is away from the to-be-tested surface of the to-be-tested chip. Preferably, the support has a flexible bearing surface. Therefore, the support column can be matched with the support column to be integrally fixed to realize effective supporting effect. In order to facilitate solving the technical problem that a plurality of chip test positioning structures are adopted to position a plurality of wafers for testing chips at the same time, preferably, the test circuit further comprises a push-pull structure, an auxiliary positioning structure and at least two chip test positioning structures; the whole pushing structure is respectively connected with the active structure of each chip testing and positioning structure and is used for integrally driving the active structure to move relative to the fixed structure; the auxiliary positioning structures are respectively fixed with the fixing structures of the chip testing positioning structures. Preferably, the test circuit comprises two chip test positioning structure groups and two auxiliary positioning structures, and each chip test positioning structure group comprises at least two chip test positioning structures; the two chip testing and positioning structure groups comprise a first chip testing and positioning structure group and a second chip testing and positioning structure group, the first chip testing and positioning structure group and the second chip testing and positioning structure group are symmetrically arranged, the two auxiliary positioning structures comprise a first auxiliary positioning structure and a second auxiliary positioning structure, the first auxiliary positioning structure is respectively fixed with the fixing structure of each chip testing and positioning structure in the first chip testing and positioning structure group, and the second auxiliary positioning structure is respectively fixed with the fixing structure of each chip testing and positioning structure in the second chip testing and positioning structure group. In this way, chip testing of multiple or even large batches of wafers can be achieved.

One embodiment of the present invention is a chip, which is implemented by using the test circuit described in any of the embodiments; or it may have a test process using the test circuit described in any of the embodiments. Preferably, the chip is obtained by testing the test circuit in any embodiment. That is, the chip has a test process of the test circuit before it is sold or during its manufacture. Thus, the manufacturing process of the chip can be specified inversely from the testing process, thereby providing a more effective chip quality control mode.

Because the charge of the test factory is collected according to the quantity and the time, in order to simplify the test, promote the test efficiency, ensure the test safety, avoid damaging the chip because of the test, it is better that the said chip includes connecting end, register and functional structure; the register is used for storing an instruction set, the instruction set comprises at least one group of test instruction sets and test serial numbers thereof, each group of test instruction sets is provided with a plurality of test instructions, and each group of test instruction sets is matched with the test serial numbers thereof; the connecting end is used for receiving an external test signal, and the test signal has the test serial number; the register is also used for outputting at least one group of test instruction sets according to the test signals; the functional structure is used for testing according to at least one group of test instruction set to obtain a test result, and outputting the test result through the connecting end. Preferably, the chip comprises a plurality of registers, and each register is used for storing a group of test instruction sets and test sequence numbers thereof. Preferably, the chip comprises a connecting end, a register and a functional structure; the register is used for sending a test instruction to the functional structure according to the test signal, and the functional structure is used for testing according to the test instruction to obtain a test result. The embodiment of the invention is suitable for testing before or after packaging of the chip, simplifies the structure of the chip related to the test as much as possible, skillfully utilizes the connecting ends and the registers of a plurality of chips, writes data into the registers, presets test items in the registers, and can realize the automatic test items of the pre-grouped test instruction set as long as the test serial number of the test signal is obtained during the test, thereby greatly simplifying the test signal and quickening the analysis of the test signal. The functional structure includes, but is not limited to, a starting unit, a clock unit, an address unit, a cache unit, a storage unit, a processing unit, a judgment unit, an output unit, a gain compensation unit, a temperature protection unit, an overvoltage protection unit, a current limiting protection unit, a constant current source, a current mirror, a timer, an interrupt controller and/or an amplifier, etc. in the existing various chips; the various embodiments of the present invention are not particularly limited thereto.

Preferably, the register is provided with a plurality of latches or flip-flops. Preferably, the test sequence number is set according to the number of groups of the test instruction sets, for example, if there are only two test instruction sets, the test sequence number may be 01 or 10; for example, there are only three sets of test instruction sets, then the test sequence number may be 01 or 10 or 11. Other embodiments are analogized and will not be described in detail below. In this way, a very short test signal can be realized. Preferably, the register is a read-write register, and is configured to write the instruction set before testing, and erase each test instruction set and the test sequence number thereof after completing testing or packaging. Therefore, the register can be repeatedly utilized, and resources are saved. Some other embodiments of the present invention may employ a memory instead of the register. Preferably, the number of the connecting ends is multiple. Preferably, the connecting end is a silicon chip pin or a packaging pin. For the uncut chip on the wafer, the connecting end is a silicon chip pin; for packaged chips, the connections are package pins. Preferably, the test signal includes only the test serial number. Therefore, the test signal can be greatly simplified, the analysis is accelerated, the test is quickly started, and the test signal can be ensured not to deviate from the test instruction set preset in the register, so that all tests can be controlled, the test risk is reduced, and the method is particularly suitable for batch chip test. Preferably, the connection terminal is used for receiving an external test signal, wherein the test signal is at least two test serial numbers in sequence. Preferably, the test signal includes a plurality of test serial numbers arranged in sequence, so that a plurality of groups of test instruction sets can be tested in sequence, and sequential testing of multiple functions can be realized. Preferably, the register is further configured to output at least two sets of the test instruction sets in sequence according to the test signal; the functional structure is used for testing according to at least two groups of test instruction sets to obtain at least two test results, and outputting the at least two test results through the connecting end. It is noted that the test result may be T (true) or F (false) alone, or may be a string of values, including but not limited to binary values or octal values. It can be seen from the above embodiments that the increase of the chip cost is almost negligible, the test instruction set write register is only added in the process, but the test efficiency is greatly improved for the test, so the test cost is reduced as a whole, and all tests can be controlled, thereby reducing the test risk, and being particularly suitable for batch chip tests. Moreover, for newly added test items or test requirements, the implementation of the embodiment of the invention is very convenient, and the register can be written into a large number of chips in batch only by writing into the register, so that the test items are expanded, and the test efficiency is improved.

Further, the embodiments of the present invention further include a test circuit and a chip formed by combining the technical features of the above embodiments, wherein the test circuit may also be referred to as a test circuit system, and/or the chip may also be referred to as a test circuit system chip.

The technical features mentioned above are combined with each other to form various embodiments which are not listed above, and all of them are regarded as the scope of the present invention described in the specification; also, modifications and variations may be suggested to those skilled in the art in light of the above teachings, and it is intended to cover all such modifications and variations as fall within the true spirit and scope of the invention as defined by the appended claims.

Claims

1. A test circuit is characterized by comprising a system unit and a test unit;

2. The test circuit of claim 1, wherein the system unit further comprises a display module, the display module is connected to the processing module, and the display module is configured to display the analog circuit and the analog test result; and/or the system unit further comprises a storage module, the storage module is connected with the processing module, and the storage module is used for storing the analog circuit and the analog test result.

3. The test circuit of claim 1, further comprising a module unit including at least two groups of functional modules and their connection terminals;

the control module is further configured to generate at least one test signal of the functional module according to the test information when the judgment module determines that the simulation test result is normal, gate the connection terminal of the at least one functional module through the test line, send the test signal to the matched functional module through the transceiver module, and call the functional module to perform at least one functional test on the chip according to the test signal.

4. The test circuit of claim 3, wherein at least one group of the functional modules has components and connections thereof arranged therein according to a structure of the chip.

5. The test circuit of claim 4, wherein at least one group of the functional modules has components and connections thereof arranged therein according to a specific functional structure of the chip.

6. The test circuit of claim 3, wherein the test circuit comprises a gate switch and at least two test branches connected to the gate switch, each of the test branches being connected to one of the connection terminals; the control module is connected with each test branch circuit through the gating switch.

7. The test circuit of claim 1, wherein the test unit further comprises an interface circuit, the interface circuit is configured to be connected to a plurality of the chips, respectively, and the control module is further connected to the interface circuit through the test line.

8. The test circuit of any one of claims 1 to 7, further comprising a database, the database being coupled to the determination module.

9. The test circuit of claim 8, wherein the database is further connected to a database cloud of other test circuits.

10. A chip, characterized in that it is implemented using a test circuit according to any one of claims 1 to 9; or which has a test process using a test circuit as claimed in any one of claims 1 to 9.