CN214503692U

CN214503692U - Adapter for field effect transistor test

Info

Publication number: CN214503692U
Application number: CN202120210941.3U
Authority: CN
Inventors: 冯振平
Original assignee: CASIC Defense Technology Research and Test Center
Current assignee: CASIC Defense Technology Research and Test Center
Priority date: 2021-01-26
Filing date: 2021-01-26
Publication date: 2021-10-26
Anticipated expiration: 2031-01-26

Abstract

The utility model discloses an adapter for testing a field effect transistor, which comprises a testing mother board and a testing daughter board; the testing mother board is provided with a bottom board, at least three relays are installed on the bottom board, the bottom board is also provided with a pin connecting hole for inserting a field effect tube, a wiring hole connected with external testing equipment and a power supply interface for supplying power to the relays, and the pin connecting hole is electrically connected with the wiring hole through the relays; the test daughter board is provided with a test seat, a probe matched with the pin connecting hole on the test mother board is fixedly installed on the test seat, and an adapter assembly connected with the probe and used for changing the pin connecting point of the device is also installed on the test seat. The adapter utilizes discrete device test system design based on the development of SiZ918DT device test procedure, can once only realize the test demand of the whole parameters of device fast, has improved the measuring accuracy, has improved the efficiency of software test in-process greatly, and measuring accuracy is high, to advantages such as the device not damaged that is surveyed.

Description

Adapter for field effect transistor test

Technical Field

The utility model relates to an electrical property test technical field especially relates to an adapter is used in field effect transistor test.

Background

The input impedance of the field effect transistor amplifier is very high, so that the coupling capacitor can have small capacity, an electrolytic capacitor is not needed, and the high input impedance is very suitable for impedance transformation and is commonly used for the input stage of a multi-stage amplifier to carry out impedance transformation. The field effect transistor has wide application range, can be used as a variable resistor, can also be conveniently used as a constant current source, can also be used as an electronic switch, and has high flexibility in circuit design. In addition, the input impedance is high, the load of a signal source can be lightened, and the matching with a previous stage is easy; the circuit has the advantages of high input resistance (107-1015 omega), low noise, low power consumption, large dynamic range, easiness in integration, no secondary breakdown phenomenon and the like. Based on the above advantages, the current MOS package is also diversified.

The traditional test method is mainly realized by a probe contact mode, and tests are carried out by using two meter pen contacts, as shown in figure 1, because the device has small and dense pins, the contact is easy to short circuit, unnecessary damage can be caused to the device, the traditional test method is not suitable for the requirements of reliability screening and testing of components, and the test efficiency is low.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a reasonable in design improves the efficiency of software testing and the field effect transistor test of measuring precision of device and uses the adapter.

In order to achieve the above object, the present invention provides the following technical solutions:

the utility model relates to an adapter for testing a field effect transistor, which is characterized by comprising a testing mother board and a testing daughter board; the testing mother board is provided with a bottom board, at least three relays are installed on the bottom board, the bottom board is also provided with a pin connecting hole for inserting a field effect tube, a wiring hole connected with external testing equipment and a power supply interface for supplying power to the relays, and the pin connecting hole is electrically connected with the wiring hole through the relays; the test daughter board is provided with a test seat, the test mother board is arranged on the test seat, probes matched with the pin connecting holes on the test mother board are fixedly arranged on the test seat, and the test seat is also provided with a switching assembly connected with the probes and used for changing the pin connecting points of the devices.

Preferably, the needle connecting holes are at least provided with two groups, each group comprises two rows, and the two rows of the needle connecting holes in each group are connected by adopting a Kelvin connection method.

Preferably, 16-point pin holes are adopted as the pin connecting holes.

Preferably, the wiring hole is provided with a CS wiring port, a CF wiring port, an ES wiring port, an EF wiring port, a BS wiring port, a BF wiring port, and a GND wiring port.

Preferably, the test seat is a probe-type kelvin base.

Preferably, the switching assembly is composed of a circuit board and a switching line, the circuit board is provided with a switching point connected with one end of the switching line, and the other end of the switching line is connected with the probe.

Preferably, each adapting wire is sleeved with a vibration-proof magnetic ring.

Compared with the prior art, the test adapter of the utility model is based on the development of the SiZ918DT device test program, utilizes the design of the discrete device test system, can rapidly realize the test requirement of all parameters of the device at one time, improves the test precision, greatly improves the test efficiency in the production process of the product batch, and has the advantages of high test precision, no damage to the device to be tested and the like; moreover, the adapter is simple in structure, convenient and flexible, can be modified according to different pin distributions and different internal structure requirements, and is high in practicability; when the adapter is reconstructed according to the pin distribution of the device, the adapter only needs to be reconnected on the daughter board according to the different pins of the device, and the mother board does not need to be changed, so that the cost is saved; the adapter is reasonable in design and composition, easy to purchase and assemble and convenient to popularize and use.

Drawings

The accompanying drawings, which are described herein, serve to provide a further understanding of the invention and constitute a part of this specification, and the exemplary embodiments and descriptions thereof are provided for explaining the invention without unduly limiting it. In the drawings:

FIG. 1 is a schematic diagram of a conventional test method;

FIG. 2 is a structural diagram of a test mother board according to the present invention;

FIG. 3 is a structural diagram of the test daughter board of the present invention;

fig. 4 is an internal structure diagram of a SiZ918DT device according to an embodiment of the present invention;

fig. 5 is a schematic diagram of an embodiment of the present invention showing the outline of the SiZ918DT of the SiZ918DT device;

fig. 6 is a structural diagram of a relay according to an embodiment of the present invention.

Reference numerals:

the testing device comprises a base plate 1, a base plate 2, a relay 3, a relay 4, a pin connecting hole 5, a wire connecting hole 6, a power supply interface 7, a testing seat 8, a probe 9, a circuit board 10, a patch cord 11, a patch point 12 and a magnetic ring 13.

Detailed Description

In order to make the technical problem, technical solution and advantageous effects to be solved by the present invention more clearly understood, the following description is given in conjunction with the accompanying drawings and embodiments to illustrate the present invention in further detail. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Referring to fig. 1-3, the utility model provides an adapter for testing a field effect transistor, which comprises a testing mother board and a testing daughter board; the test motherboard is provided with a bottom plate 1, at least three

relays

2, 3 and 4 are installed on the bottom plate 1, the bottom plate 1 is also provided with pin connecting holes 5 for inserting field effect transistors, wiring holes 6 connected with external test equipment and a power supply interface 7 for supplying power to the relays, the pin connecting holes 5 are electrically connected with the wiring holes 5 through the

relays

2, 3 and 4, at least two groups of the pin connecting holes 5 are arranged, each group of the two rows of the pin connecting holes are connected by adopting a Kelvin connection method, the pin connecting holes adopt 16-point pin arranging holes, and the wiring holes 6 are provided with CS wiring ports, CF wiring ports, ES wiring ports, EF wiring ports, BS wiring ports, BF wiring ports and GND wiring ports;

the test daughter board is equipped with test seat 8, and the test motherboard dress is on test seat 8, probe formula kelvin base is chooseed for use to test seat 8, and fixed mounting has on the test seat 8 with test motherboard on connect pinhole 5 complex probe 9, still installs on the test seat 8 to be connected with probe 9 and be used for changing the switching subassembly of device pin tie point, the switching subassembly comprises circuit board 10 and patch cord 11, is equipped with the patch point 12 that meets with patch cord 11 one end on the circuit board 10, and the patch cord other end links to each other with the probe, all overlaps on every patch cord 11 to be equipped with and to prevent vibrating and use magnetic ring 13, avoids vibrating because device reason itself when the test to influence the accuracy of test result.

In the embodiment, referring to fig. 3-6, the VISHAY manufacturer, package 6 × 5 chip dual MOS, model SiZ918DT is taken as an example, and the test steps are as follows:

the first relay 2 controls G (gate), the second relay 3 controls D (drain), and the third relay 4 controls S (source).

And when the 1 st point and the 16 th point of the relay are not electrified, the 11 th point and the 13 th point are conducted, the 4 th point and the 6 th point are conducted, and the first group of MOS tubes are tested. When 5V voltage is given, the 9 th point and the 13 th point are attracted and conducted, and the 8 th point and the 4 th point are attracted and conducted, so that the second group of MOS tubes can be tested.

The 13 th point of the first relay is connected with the BS end, the 4 th point is connected with the BF end, the 6 th point is connected with the first row of holes of the 16-point row of pinholes of the first group, the 11 th point is connected with the 2 nd row of holes, the 8 th point is connected with the 3 rd row of holes, and the 9 th point is connected with the 4 th row of holes. The 13 th point of the second relay is connected to the CF end, the 4 th point is connected to the CS end, the 6 th point is connected to the 10 th row of holes of the 16 th-point row of pinholes in the first group, the 11 th point is connected to the 9 th row of holes, the 8 th point is connected to the 11 th row of holes, and the 9 th point is connected to the 12 th row of holes. And a 13 th point of a third relay is connected to the ES end, a 4 th point is connected to the EF end, a 6 th point is connected to a 10 th row of holes of a second group of 16-point row of pin holes, a 11 th point is connected to a 9 th row of holes, an 8 th point is connected to a 12 th row of holes, and a 9 th point is connected to a 11 th row of holes, and finally, different pins of the MOS transistor are respectively connected to the specified 16-point row of pins according to the definition of device material pins, and then the test is carried out from the wiring holes.

To sum up, before testing, the utility model is firstly reformed according to the pin distribution of the device, and rewiring is carried out on the daughter board according to the difference of the pins of the device; adapter's simple structure satisfies the requirement of components and parts reliability screening and test, is difficult to the short circuit, and the test is reliable, can realize the more accurate test of 6X 5 SMD two MOS pipe series, and the measuring accuracy is high, especially can improve the efficiency of software testing and the measuring accuracy of device in the batch production process.

The above description is only for the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present invention, and all should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. An adapter for testing a field effect transistor is characterized in that: the test system comprises a test mother board and a test daughter board; the testing mother board is provided with a bottom board, at least three relays are installed on the bottom board, the bottom board is also provided with a pin connecting hole for inserting a field effect tube, a wiring hole connected with external testing equipment and a power supply interface for supplying power to the relays, and the pin connecting hole is electrically connected with the wiring hole through the relays; the test daughter board is provided with a test seat, the test mother board is arranged on the test seat, probes matched with the pin connecting holes on the test mother board are fixedly arranged on the test seat, and the test seat is also provided with a switching assembly connected with the probes and used for changing the pin connecting points of the devices.

2. The adapter for testing the field effect transistor according to claim 1, wherein: the needle connecting holes are at least provided with two groups, each group comprises two rows, and the two rows of needle connecting holes of each group are connected by adopting a Kelvin connection method.

3. The adapter for testing the fet according to claim 2, wherein: the needle connecting holes adopt 16-point needle row holes.

4. The adapter for testing the field effect transistor according to claim 1, wherein: the wiring hole is provided with a CS wiring port, a CF wiring port, an ES wiring port, an EF wiring port, a BS wiring port, a BF wiring port and a GND wiring port.

5. The adapter for testing the field effect transistor according to claim 1, wherein: the test seat adopts a probe type Kelvin base.

6. The adapter for testing the field effect transistor according to claim 1, wherein: the switching assembly is composed of a circuit board and a switching line, a switching point connected with one end of the switching line is arranged on the circuit board, and the other end of the switching line is connected with the probe.

7. The adapter for testing the field effect transistor according to claim 6, wherein: each switching wire is sleeved with a magnetic ring for anti-vibration.